EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements

Transcription

1 EE241 - Spring 2007 Advanced igital Integrated Circuits Lecture 24: Advanced Flip-Flops Synchronization Announcements Homework 5 due on 4/26 Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1

2 Class Material Last lecture Intro to flip-flops Today s lecture Flip-flops Introduction to synchronization 3 Types of Flip-Flops Latch Pair (Master-Slave) Pulse-Triggered Latch ata L1 L2 L ata 4 2

3 Flip-Flop elay Sum of setup time and -output delay is the true measure of the performance with respect to the system speed T = T - + T Logic + T setup + T skew Logic N T - T Logic T Setup 5 elay vs. Setup/Hold Times 350 Minimum ata-output Output [ps] Setup Hold ata- [ps] 6 3

4 Master-Slave Latch Pairs Positive setup times Two clock phases:» distributed globally» generated locally Small penalty in delay for incorporating MUX Some circuit tricks needed to reduce the overall delay 7 Master-Slave Latch Pairs Case 1: PowerPC 603 (Gerosa, JSSC 12/94) b b 8 4

5 T-G Master-Slave Latch Feedback added for static operation Unbuffered input input capacitance depends on the phase of the clock over-shoot and under-shoot with long routes wirelength must be restricted at the input Clock load is high Low power Small clk-output delay, but positive setup 9 Master-Slave Latches Case 2: C 2 MOS Ck Ckb Ckb Ck Ck Ckb Ck Feedback added for static operation Locally generated clock Poor driving capability Ck Ckb 10 5

6 Master-Slave TSPC Flip-flops V V V V V V X Y (a) Positive edge-triggered flip-flop (b) Negative edge-triggered flip-flop V V V (c) Positive edge-triggered flip-flop using split-output latches 11 Pulse-Triggered Latches First stage is a pulse generator generates a pulse (glitch) on a rising edge of the clock Second stage is a latch captures the pulse generated in the first stage Pulse generation results in a negative setup time Frequently exhibit a soft edge property Note: power is always consumed in the pulse generator 12 6

7 Pulsed Latch Simple pulsed latch Kozu, ISSCC Intel/HP Itanium 2 Naffziger, ISSCC

8 Pulse-Triggered Latches Hybrid Latch Flip-Flop, AM K-6 Partovi, ISSCC HLFF Operation 1-0 and 0-1 transitions at the input with 0ps setup time 16 8

9 Hybrid Latch Flip-Flop Skew absorption Partovi et al, ISSCC Pulse-Triggered Latches AM K-7 Courtesy of IEEE Press, New York

10 Pulse-Triggered Latches Semi-ynamic Flip-Flop (SFF), Sun UltraSparc III, Klass, VLSI Circuits 98 Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transition Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists Small penalty for adding logic 19 Pulse-Triggered Latches 7474, from early 1960 s S R 20 10

11 Pulse-Triggered Latches Case 4: Sense-amplifier-based flip-flop, Matsui EC Alpha 21264, StrongARM 110 First stage is a sense amplifier, precharged to high, when = 0 After rising edge of the clock sense amplifier generates the pulse on S or R The pulse is captured in S-R latch Cross-coupled NAN has different propagation delays of rising and falling edges 21 Sense Amplifier-Based Flip-Flop Courtesy of IEEE Press, New York

12 Flip-Flop Performance Comparison Test bench ata Total power consumed internal power Clock data power clock power Measured for four cases no activity (0000 and 1111 ) maximum activity ( ) average activity (random sequence) 50fF elay is (minimum -) - + setup time 200fF 200fF Stojanovic, Oklobdzija JSSC 4/99 23 Flip-Flop Performance Comparison 70 Total power [uw] msaff HLFF SFF TG M-S C 2 MOS Original SAFF elay [ps] 24 12

13 Sampling Window Comparison Naffziger, JSSC 11/02 25 Local Clock Gating CKI I CKIB CKIB ata-transition Look-Ahead Pulse Generator XNOR CP CKIB CKI Clock on demand Flip-flop 26 13

14 Timing Overview Synchronization Approaches Synchronous Systems Timing methodologies Latching elements Clock distribution Clock generation Asynchronous Systems 27 References Chapter 10 in Rabaey Chapter 11 in Bowhill Clocked storage elements, by H. Partovi High-speed CMOS design styles, Bernstein, et al, Kluwer Unger/Tan IEEE Trans. Comp. 10/86 Harris/Horowitz JSSC 11/97 Messerschmitt JSAC 10/90 Stojanović/Oklobdžija JSSC 4/

15 Issues in Timing Messerschmitt, Oct 1990 Boolean signal - stream of 0 s and 1 s, generated by saturating circuits and bistable memory elements but finite rise and fall times inter-symbol interference metastability leads to non-deterministic behavior signal transitions are crucial typically defined with respect to slicer/sampler associated clock with uniformly spaced transitions 29 Issues in Timing Clock signal : f + Δf d/dt average frequency instantaneous frequency deviation Single Boolean signal equal Isochronous f + Δf = constant not equal Anisochronous f + Δf constant 30 15

16 Issues in Timing Two Boolean Signals together Synchronous f + Δf identical Δ(t) = 0 (or known) middle Mesochronous Δ(t) variable (but bounded) Asynchronous not together different Heterochronous Nominally ifferent freq near Plesiochronous Average Frequency almost the same 31 Some efinitions Signals that can only transition at predetermined times with respect to a signal clock are called {syn,meso,plesio}chronous An asynchronous signal can transition at any arbitrary time

17 Some efinitions (contd) Synchronous Signal: exactly the same frequency as local clock, and fixed phase offset to that clock. Mesochronous Signal: exactly the same frequency as local clock, but unknown phase offset. Plesiochronous Signal: frequency nominally the same as local clock, but slightly different Mesochronous and plesiochronous concepts are very useful for the design of systems with long interconnections, and/or multiple clock domains 33 Mesochronous Interconnect clock synchronous island ata synchronous island Phase Generator Select Clock (local) Phase etect ata R1 R2 Local Synchronization samples in certainty period of signal 34 17

18 Mesochronous Communication Variable elay Line Block A R 1 1 Interconnect elay 2 3 R 2 4 Block B A B Control Timing Recovery 35 Plesiochronous Communication Timing Cloc k C Clock C 2 1 Recovery Originating Module C 3 FIFO Receiving Module oes only marginally deal with fast variations in data delay 36 18

19 Anisochronous Interconnect 37 Next Lecture Timing 38 19