COMPUTER ENGINEERING PROGRAM

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1 COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 6 Introduction to Digital System Design: Combinational Building Blocks Learning Objectives 1. Digital Design To understand and design several common digital components 2. VHDL Modeling To understand and utilize concurrent statements in digital circuit design 3. Digital System Design To learn a basic approach to integrating several digital components into a single circuit To understand and utilize concurrent statements in VHDL and the relation to digital system design and implementation Introduction and Overview In this experiment, you will design and implement two standard digital circuits: a BCD to 7-Segment Display Decoder and a Priority Encoder. This experiment builds upon the VHDL skills and knowledge of the Xilinx tools you developed in Experiment 5. In particular, this experiment demonstrates the strengths of VHDL by facilitating the integration of several digital circuits into a larger design. This design approach represents one of the most basic tenets of digital design: the Modular System Design. Modular System Design Good digital design practices involve the ability to segment a larger system into small pieces that can be designed and tested independently. The independent design and testing of these smaller pieces facilitates the integration of these components into a larger system-level design. The modular approach to digital design enhances design efficiency by allowing the reuse of previously designed modules. The modular approach also promotes an understanding of the final digital system by first encouraging the understanding of the individual digital modules involved. The modules designed in this experiment will be used again in a later CPE 169 experiment, as components of a digital alarm system. A diagram of the digital alarm system that you will implement later is shown in Figure 1. Because the modules developed in this experiment are used again in the course, it is important that you design each component to fully meet the given specifications, and thoroughly test them to confirm this. Having previously-designed and fully-tested modules eases the integration of these modules into the more complex circuit implementing the complete digital alarm system. In this experiment, you will design and implement two components of the Digital Alarm System shown in Figure 1. The two modules on today s menu are the BCD-to-7-Segment Display Decoder and the Priority Encoder. These modules are designed separately, tested individually, and then integrated into a working system

2 7-Segment Displays Figure 1: A digital alarm system. The 7-segment display is one of the most common display devices in the universe. These devices are typically used to display the full set of decimal digits, and are also capable of displaying the full gamut of hexadecimal numbers (although the case, upper vs. lower, of the alphabetic hex characters will not be consistent). Each of the 7-segment displays provided on your development board is formed with seven LEDs (light emitting diodes). You have already used a more common type of LED display, LD0 LD7, the small colored indicators that light up occasionally during your experimentation. The LEDs used in this experiment have been specially elongated by tiny robotic trolls using small stretching racks ( well maybe not ) and arranged and connected so that each segment can be independently illuminated (or not) to form patterns that resemble each of the decimal digits. The LED is a two-terminal, polarity-sensitive device that turns on when the voltage conditions across the two terminals are correct. The two terminals of this device are referred to as the anode and the cathode. To make the LED emit light, you must provide a voltage on the anode side that is at least 0.7 Volts higher than the voltage on the cathode terminal. What this means to you in digital design land is that whether you need to provide the LED segment with a 1 or a 0 from the FPGA to make it light up depends on how the LED is wired into the circuit (i.e. which terminal of the diode you are driving and what voltage the other terminal is connected to). To find out exactly how the LED segments are connected, the common practice of future digital design superstars is to read the specification of the circuit board you re using. (It s waiting for you now on the CPE 169 website.) Representing particular decimal numbers on a display is accomplished by turning on specific combinations of the seven individual LED segments. Each of the seven segments is referenced by a unique letter identifier. The most common orientation of these segment identifiers is shown in Figure 2(a). On the development board, the signals connected to each of the LED segments uses these same identifiers, preceded by either an A or a C to indicate if the signal is connected to the anode or cathode side of the segment LED. Using the 7-segment display to create the appearance of the number 0 is demonstrated in Figure 2(b) by lighting all the segments except segment g. Figure 2(c) shows segments a, b, c, d, and g lit to display the number 3. As you ll see in the development board specification, lighting a particular LED segment is a two-step process. You need to both turn on the individual LED segment, and also activate one or more of the four available 7-segment displays on the board. Both of these actuation steps involve sending a logical 1 or 0

3 from the FPGA to the proper signals connected the display device. Consult the development board specification for the connection and control details (and then ask a bunch of questions). (a) (b) (c) Figure 2: The ultra-amazing 7-segment display. Digital System Design with VHDL One of the basic tenets of digital design with VHDL is the concept of concurrency. As you assuredly know from your perusing of the VHDL tutorial listed on the CPE 169 website, there are four types of concurrent statements: 1) simple signal assignment, 2) conditional signal assignment, 3) selective signal assignment, and 4) process statement. Any given architecture in VHDL can contain as many concurrent statements as your heart desires. The functionality described in these statements occurs concurrently in the circuit that is synthesized from your VHDL code. The circuit you created in the previous experiment contained four inputs (A, B, C, and D) and two outputs (F1 and F2). You probably implemented these circuits using two concurrent signal assignment statements. This was a rather basic VHDL design in that every signal associated with the circuit was also listed in the entity description. In other words, each of the signals used in the circuit was either an input or an output of the circuit. This is all well and good for simple circuits, but simple circuits are rather dull and uninspiring. The final circuit in this experiment requires that you use signals that can t be labeled as either input or output : they re just signals, conveying information from one internal part of the circuit to another. The VHDL code shown in Figure 3(b) is an implementation of the circuit shown in Figure 3(a). Not that it s necessarily good VHDL programming practice or anything like that, but it does show something new and useful. Since the signals named and1 and and2 have no external linkage (meaning they do not appear in the entity declaration as inputs or outputs), they must be declared internally within the architecture. This is done before the begin statement and after the architecture opening line. Note that the word signal is a keyword in VHDL. Also note that the signal declarations appearing in the architecture do not contain mode specifiers (in or out) as do the signal names appearing in the entity declaration (but they do still have the type declaration of std_logic). entity my_ckt is port ( A,B,C : in std_logic; F : out std_logic); end my_ckt; architecture ckt1 of my_ckt is -- intermediate signal declaration signal and1,and2 : std_logic; begin and1 <= (NOT A) AND C; and2 <= A AND B; F <= and1 AND and2; (a) end ckt1; (b) Figure 3: A simple circuit (a) and its new-fangled VHDL implementation (b).

4 Procedures Procedure Overview: In this experiment, you ll design two modules which are later integrated into one complete circuit system. An outline of the procedure is listed below. 1) Design, test, and implement a BCD to 7-segment Decoder. 2) Design, test, and implement a Priority Encoder. 3) Integrate the BCD to 7-segment decoder, priority encoder, and 7-segment displays into a system that will display the channel number of the highest priority input that is active on the priority encoder. Procedure 1: Binary Coded Decimal (BCD) to 7-Segment Display Decoder 1. Design a basic BCD to 7-Segment Display Decoder using VHDL. This circuit has four inputs (B 3 B 2 B 1 B 0, the 4 bits of a Binary Coded Decimal digit) and seven outputs (controlling the seven individual display segments). Complete a Truth Table like the one below to describe your circuit s intended behavior, and then design and implement your decoder using VHDL and the Xilinx ISE software environment. Design this basic display decoder with 7-segment display output signals that provide the correct logic levels to control the particular type of display found on your development board (common-cathode: active high display signals; or common-anode: active low display signals). In theory, you could design this decoder by writing and reducing a Boolean logic expression describing each of the seven segment outputs in terms of the 4 input signals, as you did in last week s lab (after tackling seven minimizations using Boolean Algebra or seven 4-variable K-Maps to produce the minimum cost solution). But now, you can instead use the descriptive power of VHDL and any type of concurrent statement you deem appropriate to describe and implement the desired circuit behavior more efficiently. A clever mind will write the VHDL code in such a way as to allow the VHDL compiler to do most of the grunt work of realizing an efficient implementation (so try to have a clever mind). BCD Input Digit 7-Segment Display Signals B3 B2 B1 B0 A B C D E F G Table 1: BCD to 7-Segment Display truth table (if common-cathode display: 1 = segment lit )

5 2. Adapt your basic display decoder design to the multiple-digit display provided on your development board. You should show the output digit determined by your decoder on just one of the four 7-segment displays on the development board. None of the LED segments in any of the other 3 displays on the board should be lit. Also, the decimal point LEDs that are part of each digit display should always be turned off. To accommodate the particular display configuration available on the development board, your revised VHDL code will need to include additional output signals to turn on or turn off each of the four available 7-segment displays, using the control signals provided in the board design. As shown in the Nexys or Nexys-2 Board Reference Manuals, each digit display has all of the terminals on one side of its 7 LED segments connected together; and this common signal (common anode or common cathode) is connected to a driving transistor that is controlled by an output of the FPGA. The logic output level (0 or 1) needed to turn on a display will again depend on which side of the LED is being driven, the type of transistor used, and how the transistor is connected. If you are not familiar enough with analyzing transistor circuits to determine which logic output level to apply to these signals based on the schematic diagram given in the Reference Manual, then just make an assumption for now (Display ON = 0 or 1? Take your pick). If three displays are lit instead of one when you implement and test the design, then you know that you guessed wrong. (Such is the beauty of programmable logic design using VHDL. If you make a mistake, it is easy and fast to revise your design; and no hardware modifications are needed! ) You will also need to add yet another output to your basic display decoder design to turn off the decimal point (DP) on the displays. The LED for the decimal point is controlled exactly the same way as the 7 LED segments in the display. 3. Simulate your enhanced design using ISim and include an annotated output of this simulation in your lab report. 4. Implement your design on your development board. Use the four left-most switches on your development board to input a BCD number B 3 B 2 B 1 B 0, respectively (most significant digit to the left). Display the output digit corresponding to the BCD code input on any one of the 7-segment displays on the development board. Verify your circuit is working correctly and demonstrate your working circuit to your instructor. Be sure to include a diagram of your BCD to 7-segment display decoder implementation and its connections to the display and switches in your lab report. NOTE: If you make any modifications to your VHDL code to fix problems found in this final implementation and visual verification step, be sure to repeat the ISim simulation on your revised design, and include just these corrected results in your lab report (with proper annotation, of course). Procedure 2: The Priority Encoder A priority encoder is a specialized digital device. Like any other combinational logic circuit, it is still simply a collection of outputs that are functions of the present input signals. However, the exact input/output relationship is generally not as straightforward as most of the other digital devices you have encountered so far. This requires that you clearly understand the specifications of the device before you begin implementation. It also means that you will need more sophisticated VHDL statements than simple signal assignments to describe the behavior of the priority encoder. In the digital world, circuit components often require some type of attention or response from other circuit components. Since several components may need attention at the same time, and responding immediately to certain components may be more critical than to others, there needs to be a way of treating some component s requests for attention as more important than another s. This is the job of the priority encoder.

6 A priority encoder encodes (produces a binary number on its outputs for) the highest number input channel having an asserted signal at any given moment. For example, if signals on inputs I 2, I 3, and I 6 are all asserted at the same time (if they are all in the 1 state), the priority encoder encodes a 6 and outputs Y 2 Y 1 Y 0 will be 110 (the binary representation for 6 ). When no inputs are asserted, Y 2, Y 1, and Y 0 will collectively be 000. For this circuit, a STROBE output is also provided, which is asserted whenever at least one input is asserted, and is otherwise unasserted. The STROBE signal indicates to other devices when the number appearing on the priority encoder s output signals (Y 2 Y 1 Y 0 ) is valid. The STROBE also provides a means of distinguishing if 000 appearing on the priority encoder output is due to channel I 0 being asserted (with the STROBE also asserted), or because NONE of the inputs is asserted at the moment (STROBE unasserted). A black-box diagram of the priority encoder is shown in Figure Design an 8:3 priority encoder. HINT: A specialized, abbreviated sort of truth table is a good starting point for this design. (Be creative so you don t have to create the 256 line truth table that an 8-input device would normally need!) Consider what the critical input signals and levels are that should cause each different output signal combination, and how to indicate that the other inputs are non-critical. The 3-bit output is the binary representation of the highest numbered input that is asserted. The STROBE output on your encoder should be asserted when one or more inputs are asserted. Include the special truth table you created for your priority encoder design in your report. Figure 4: Lo and behold, the awesome priority encoder. 2. In the same ISE project that you created for your BCD-to-7-segment Display Decoder, add a new VHDL module to the project and enter the VHDL description for your priority encoder design. Note that since you now have two different VHDL sources in the same project, you must indicate to the ISE tools which one you will be compiling and implementing. You do this by designating one of the VHDL modules as the Top Module. a. Add your new VHDL Module as a New Source to the project b. Right-click on your new VHDL Module in the Hierarchy window. c. Select Set as Top Module from the options that appear. 3. Simulate your priority encoder using ISim. For your simulation, you will need to develop a new approach to verifying that this device functions properly, as exhaustively testing it with every possible combination of values for the eight input signals is not practical (at least not if you are going to finish this lab any time soon). Therefore, try to determine an efficient set of test combinations that will thoroughly verify the operation of all functions and outputs of this device. Include an annotated output of your simulation in your lab report; including some notes to explain the methodology that you applied and to interpret the results you obtained. a. When you create the new test waveform source for the Priority Encoder, make sure that you associate it with the correct VHDL module. 4. Implement your circuit on the development board. Connect outputs Y2, Y1, and Y0 to the rightmost LEDs on the development board; connect the STROBE output to the left-most. Use the eight

7 switches for the encoder inputs, and consider the left-most switch to have the highest priority. The switch with the highest priority should be connected to the highest priority input of the encoder. Note that the ISE tools will only permit you to have one pin assignment user constraints file associated with a particular project; even if you have multiple VHDL modules in the project. Therefore, before adding the new user constraints file for the Priority Encoder to the project, you need to first remove the constraints file created in Procedure 1. a. Right-click on your old constraints (.ucf) file in the Hierarchy window (View: Implementation) b. Select Remove from the options that appear. This only disconnects the file from the project. The file itself remains in the project folder, and can be added back into the project ever if needed. c. Then, with the top module selected in the Hierarchy window, perform your new IO Pin Planning with Plan Ahead (Pre-Synthesis). Allow the tools to create a new User Constraints File associated with the top module for this step. 5. Demonstrate your working circuit to your lab instructor. Procedure 3: Component Integration You ve now designed two standard digital modules using VHDL. In this procedure, you integrate those modules into a single circuit that is used to visually verify the proper functioning of the circuit. 1. Design an integrated digital system that displays the output of the priority encoder on one of the four 7-segment displays using the BCD to 7-segment decoder to interpret the priority encoder output. The relation between the BCD to 7-segment decoder and the priority encoder is similar (but not identical) to that shown in Figure 1. As in the previous procedure, use the 8 switches on the development board for the inputs of the priority encoder, with the left-most switch having the highest priority. The STROBE signal should again be connected to the left-most LED on the development board, unless you can think of another clever use for it to improve how your system functions. Unused circuit inputs should be grounded (assigned a 0 value). To aid in your design, first draw a black-box diagram for your logic circuit, showing the inputs / outputs for the combined digital logic system to be described in your new VHDL code module. Also draw a block diagram for your complete system design, showing the priority encoder and display decoder modules as separate blocks; and showing all inputs, outputs (including the 7-segment display), and intermediate signals between modules. 2. Create the integrated VHDL description for this combined design in a single, new source code module. In the same ISE project that you designed the two other circuits, start a new circuit source module and combine all of the concurrent statements used in the previous designs of the two modules. You ll need to redefine the inputs and outputs of this combined design according to your black-box diagram, and use intermediate signals in order to complete this integration. HINT: Do not make major changes to the VHDL code for the individual modules from Procedure 1 and Procedure 2. These are now fully verified, proven, working designs. Most of your work in Procedure 3 should involve stitching together the BCD to 7-Segment Decoder and the Priority Encoder with as little change as possible (or better yet no changes) to the original code for each device. (Why risk breaking a design that you are sure works fine already?!) 3. Demonstrate your working circuit to the lab instructor. (No ModelSim simulation results are required for the integrated system.) 4. Be sure to save a copy of your Xilinx design files for future use. You will be using these devices again in several future labs ( design reuse!).

8 Final Notes Be sure to include all of the VHDL code you wrote during this experiment in your lab report. And as with all circuits you design and/or test, include schematic or block diagrams for all circuits implemented. Be sure to show the details of how you interconnected your two devices and handled all of their inputs and outputs in the diagram for Procedure 3. Your diagrams should match your implementations in the VHDL code, including using the same signal names in both. Your lab report should also include an output from each of the Isim simulations you performed. Again, be sure to save the VHDL code you wrote in this experiment for later experiments. Questions 1. Fully describe the operation of the circuit designed in Procedure 3. Your explanation should cover how the inputs to the circuit generate a given output. Your explanation should also include comments regarding the integration of the two circuits using VHDL. 2. In this experiment, you implemented two separate circuits and later integrated them into one system. Discuss the possibility and consequences of skipping Procedures 1 & 2 and implementing the circuit described in Procedure 3 directly. 3. The antiquated CPE segment decoder lab (the one that was formerly used by all students) forced students to implement the decoder using a set of seven K-maps and subsequently seven simple concurrent signal assignment statements. Compare and contrast the approach taken in the older lab and the approach taken in this lab; list pros and cons of each approach. 4. In Procedure 3, why was a 0 (as opposed to a 1 ) assigned to the most significant bit of the BCD value? 5. In the context of an alarm system, what could be the function of the STROBE signal if it operates as it was implemented in this experiment? Fully explain your answer. 6. The VHDL code shown in Figure 3 of this experiment used two concurrent statements and two intermediate signals. A similar circuit from Experiment 5 was modeled in VHDL using just one concurrent statement. Is there an advantage to one approach over the other? Would you think that this level of differences would change the appearance of the final circuit created by the VHDL synthesis tool? Fully explain your answer.