Testing Sequential Circuits
|
|
|
- Godfrey Reed
- 5 years ago
- Views:
Transcription
1 Testing Sequential Circuits 9/25/ Testing Sequential Circuits Test for Functionality Timing (components too slow, too fast, not synchronized) Parts: Combinational logic: faults: stuck /, delay Flip-flops: faults: input, output stuck /, delay no latch / capability Cases: Without feedback With feedback Our work Our work Testing Sequential circuits without feedback Register A Combinational circuit Register B. Generate tet vectors for the combinational circuit. 2. Place a vector in A 3. Examine response in B 4. 2,3 can be done using a. Machine instructions b. Microinstructions c. Specialized hardware 2 YKM
2 Testing Sequential Circuits 9/25/ BIST (Built-in self-test) Generator Combinational circuit Signature analyzer ALFSR: autonomous linear feedback shift register. Better generators include our antirandom test generator. Generator generates pseudorandom vectors. Often an ALFSR. Signature analyzer compresses all successive responses into a signature. Usually an LFSR. Compared with known good signature. Aliasing probability: prob. that a bad circuit can result in good signature. Very small. BILBO: PIPO, SA functions 3 Sequential Circuits with feedback x y Comb. z Storage elements Software testing correspondence? Example: processor control unit Input: status, opcode Output: control lines Structural testing: How to obtain a desired (x,y) vector How to propagate error Functional testing: Prove presence of all states Prove all transitions/outputs correct 4 YKM 2
3 Testing Sequential Circuits 9/25/ Sequential Circuits with feedback: Approaches Consider the sequential behavior: Design for testability: feedback-less during testing Scan Design: modes Parallel out Normal: parallel in/out Comb. Test: serial in/out Sequence Scan a vector: test mode Latch response: normal mode Scan response out: test mode Chain too long Multiple chain Serial out Partial scan Parallel in Serial in Model control 5 D-Algo: Sequential Circuits Equivalent iterative array model: x() x() x(2) y() comb Pseudo Flip-flop y() comb Pseudo Flip-flop y(2) comb Pseudo Flip-flop z() Frame () z() Frame () z(2) Frame (2) Q Din Q+ Din Q Psuedo-ff Psuedo-flipflop is a combinational block. Present state 6 YKM 3
4 Testing Sequential Circuits 9/25/ D-Algo.: Seq Circuit Extension One time-frame for each clock-period. Converts problem to combinational. Only 4 n distinct states possible (boolean values,, D,).? Assume faults in the combinational logic only.? Assume initial state given. Procedure: Get iterative array model, initial state D-algo. to drive D or towards an output z(k) Terminate when D or at an output. a state is repeated. when k>4 n. n=# of flipflops? 7 Seq D-Algo: Example x 5 z x()= x()= x(2)= x x 2 6 D z()= z()= z(2)=d Start: fault α s-a-, initial state, =(,) x Time frame : Since already, line α = For 4= need x()= Since 3= already, D 2 =. Also D = Next state Y()=(, ), z()= x α D 2 8 YKM 4
5 Testing Sequential Circuits 9/25/ Seq D-Algo: Ex (pt2) x 5 z x()= x()= x(2)= x x 2 6 D z()= z()= z(2)=d Time frame : Next state Y()=(, ), z()= x Time frame : error can not yet be propagated to z. For D = need x()=. Gives D 2 =. Y(2)=(,), Time frame 2: Since =D, choosing x(2)= gives z=d. Answer: Test sequence (,,) for initial state (,). x α D 2 9 Initialization Problem Power-up: state undefined How to get FSM in a known state?. Applying an input sequence 2. Resetting to an initial state Resetting always used in practice using a reset/clear line Computers: power-on sequence to initialize PC, SP, interface registers etc. Problem with reset mechanism: highly testable Hence we can neglect it YKM 5
6 Testing Sequential Circuits 9/25/ Functional Testing of FSMs Given: state table Objective: confirm it is obeyed Approaches:. Only outputs observable: Checking sequence a. Prove all states exist b. For all inputs for each state, these are correct Next state Outputs Complex and lengthy (we ll skip it for now) 2. State observable:. Much easier 2. Euler path, if it exists, can minimize testing Semiconductor RAMs Types: Static (cell is flip-flop), dynamic (charged capacitor) Organization: assume m address lines, assume bit wide chip External: words bits/word = 2 m Internal: m=r+q r lines for word-line selection q lines for bit-line selection 2 YKM 6
7 Testing Sequential Circuits 9/25/ RAM Chip Organization Read/write Data bit in r decoder Word-line cell Bit-line Coincident selection q dec selector Data bit out 3 RAM Fault Types Soft errors: temporary bit errors: require concurrent detection Corrective action: fault tolerance (retry or encoding) Hard defects Logical Parametric: access-time, leakage current etc. Tested during Manufacturing Power-up etc Highly regular design: allows systematic optimization 4 YKM 7
8 Testing Sequential Circuits 9/25/ Functional Fault Model By Abraham, Reddy etc One or more cells stuck-at or. Defects in cells Read/write electronics stuck-at / Decoding faults One or more cells fail to do or. Defects in cells One or more pair of cells coupled i,j coupled= or transition of i changes the state of j (not necessarily vice versa) Decoding faults, read/write electronics coupling More than one cells accessed during a read or write Decoding faults 5 RAM Testing: March Step : Write all s. Step 2: For i=,..n- do Read c i (=) c i Read c i (=) Step 3: For i=n-,.. do Read c i (=) c i Read c i (=) Step 4: Repeat steps -3 for complementary pattern... Trail: we know a new cell is being accessed each time Coupling with higher numbered cells.. Coupling with lower numbered cells Complexity: 2n 6 YKM 8
9 Testing Sequential Circuits 9/25/ Testing for Coupling To test for coupling between all cell pairs (i,j) Test bit i Test bit j Do some sequence of read, write operations for i & j Repeat for all i Repeat for all j Complexity: All i and j: const n n = k n 2 Same row & column only: k n (2 n) = k n.5 Careful sequencing can reduce complexity Suk & Reddy s test satisfies fault model with 4n. 7 Testing Complex Systems Approach: Assume a fault model for each component Assume a system model that takes into account interaction of components Device a testing strategy such that these are adequately tested each individual component Interaction of components A component may be a Physical component Segment of the functionality 8 YKM 9
10 Testing Sequential Circuits 9/25/ Incremental Testing Core L Layer Layer 2 Partition into layers such that layer i can be exercised using only layers,.. i-. Test components in each layer in the sequence L, L,..Ln. Layering may require Assumptions Disabling feedback during testing Proofs of complete coverage can be constructed. Fault isolation can be done. 9 Incremental testing: Example: Processor Based systems Self-test processor: Basic instructions Addressing modes Complex instructions Test Memory system and buses using processor Test I/O devices/ports Test peripheral devices Test software integrity 2 YKM
Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory. National Central University
Chapter 3 Basics of VLSI Testing (2) Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Testing Process Fault
CMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.
Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification
VLSI System Testing. BIST Motivation
ECE 538 VLSI System Testing Krish Chakrabarty Built-In Self-Test (BIST): ECE 538 Krish Chakrabarty BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)
UNIT IV CMOS TESTING. EC2354_Unit IV 1
UNIT IV CMOS TESTING EC2354_Unit IV 1 Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan EC2354_Unit
Testability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
Unit 8: Testability. Prof. Roopa Kulkarni, GIT, Belgaum. 29
Unit 8: Testability Objective: At the end of this unit we will be able to understand Design for testability (DFT) DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Level Sensitive
Lecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
Instructions. Final Exam CPSC/ELEN 680 December 12, Name: UIN:
Final Exam CPSC/ELEN 680 December 12, 2005 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary.
Based on slides/material by. Topic 14. Testing. Testing. Logic Verification. Recommended Reading:
Based on slides/material by Topic 4 Testing Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London!! K. Masselos http://cas.ee.ic.ac.uk/~kostas!! J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
Testing Digital Systems II
Testing Digital Systems II Lecture 5: Built-in Self Test (I) Instructor: M. Tahoori Copyright 2010, M. Tahoori TDS II: Lecture 5 1 Outline Introduction (Lecture 5) Test Pattern Generation (Lecture 5) Pseudo-Random
Unit V Design for Testability
Unit V Design for Testability Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan Slide 2 Testing
for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ
Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction
ECE 715 System on Chip Design and Test. Lecture 22
ECE 75 System on Chip Design and Test Lecture 22 Response Compaction Severe amounts of data in CUT response to LFSR patterns example: Generate 5 million random patterns CUT has 2 outputs Leads to: 5 million
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
Overview: Logic BIST
VLSI Design Verification and Testing Built-In Self-Test (BIST) - 2 Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut 23 April 2007 1 Overview: Logic BIST Motivation Built-in
Design for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
K.T. Tim Cheng 07_dft, v Testability
K.T. Tim Cheng 07_dft, v1.0 1 Testability Is concept that deals with costs associated with testing. Increase testability of a circuit Some test cost is being reduced Test application time Test generation
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Agenda Introduction to testing Logical
Digital Integrated Circuits Lecture 19: Design for Testability
Digital Integrated Circuits Lecture 19: Design for Testability Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec19 cwliu@twins.ee.nctu.edu.tw 1 Outline
Testing Sequential Logic. CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Testing Sequential Logic (cont d) Testing Sequential Logic (cont d)
Testing Sequential Logic CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Electrical and Computer Engineering University of Alabama in Huntsville In general, much more difficult than testing combinational
Built-In Self-Test (BIST) Abdil Rashid Mohamed, Embedded Systems Laboratory (ESLAB) Linköping University, Sweden
Built-In Self-Test (BIST) Abdil Rashid Mohamed, abdmo@ida ida.liu.se Embedded Systems Laboratory (ESLAB) Linköping University, Sweden Introduction BIST --> Built-In Self Test BIST - part of the circuit
Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
MC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
Based on slides/material by. Topic Testing. Logic Verification. Testing
Based on slides/material by Topic 4 K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html igital Integrated Circuits: A esign Perspective, Prentice
Scan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
Using on-chip Test Pattern Compression for Full Scan SoC Designs
Using on-chip Test Pattern Compression for Full Scan SoC Designs Helmut Lang Senior Staff Engineer Jens Pfeiffer CAD Engineer Jeff Maguire Principal Staff Engineer Motorola SPS, System-on-a-Chip Design
MODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
Design for Test. Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective.
Design for Test Definition: Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective. Types: Design for Testability Enhanced access Built-In
Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. Built-In Self Test 2
CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Built In Self Test (BIST) ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques VLSI Systems and
D Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
CS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 4: Latches, Flip-Flops, and Sequential Circuits Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
EE241 - Spring 2001 Advanced Digital Integrated Circuits. References
EE241 - Spring 2001 Advanced Digital Integrated Circuits Lecture 28 References Rabaey, Digital Integrated Circuits and EE241 (1998) notes Chapter 25, ing of High-Performance Processors by D.K. Bhavsar
Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison Fall 2014-2015 Final Examination CLOSED BOOK Kewal K. Saluja Date: December 14, 2014 Place: Room 3418 Engineering Hall
Lecture 18 Design For Test (DFT)
Lecture 18 Design For Test (DFT) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ASIC Test Two Stages Wafer test, one die at a time, using probe card production
Final Exam CPSC/ECEN 680 May 2, Name: UIN:
Final Exam CPSC/ECEN 680 May 2, 2008 Name: UIN: Instructions This exam is closed book. Provide brief but complete answers to the following questions in the space provided, using figures as necessary. Show
Slide Set 14. Design for Testability
Slide Set 14 Design for Testability Steve Wilton Dept. of ECE University of British Columbia stevew@ece.ubc.ca Slide Set 14, Page 1 Overview Wolf 4.8, 5.6, 5.7, 8.7 Up to this point in the class, we have
Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA M.V.M.Lahari 1, M.Mani Kumari 2 1,2 Department of ECE, GVPCEOW,Visakhapatnam. Abstract The increasing growth of sub-micron
Design for Testability Part II
Design for Testability Part II 1 Partial-Scan Definition A subset of flip-flops is scanned. Objectives: Minimize area overhead and scan sequence length, yet achieve required fault coverage. Exclude selected
The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
Random Access Scan. Veeraraghavan Ramamurthy Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL
Random Access Scan Veeraraghavan Ramamurthy Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL ramamve@auburn.edu Term Paper for ELEC 7250 (Spring 2005) Abstract: Random Access
Transactions Brief. Circular BIST With State Skipping
668 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 5, OCTOBER 2002 Transactions Brief Circular BIST With State Skipping Nur A. Touba Abstract Circular built-in self-test
UNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
Design of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
problem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2002 4/5/02 Midterm Exam II Name: Solutions ID number:
[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785
![[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785](/thumbs/84/89645202.jpg "[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785")
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY DESIGN AND IMPLEMENTATION OF BIST TECHNIQUE IN UART SERIAL COMMUNICATION M.Hari Krishna*, P.Pavan Kumar * Electronics and Communication
This Chapter describes the concepts of scan based testing, issues in testing, need
Chapter 2 AT-SPEED TESTING AND LOGIC BUILT IN SELF TEST 2.1 Introduction This Chapter describes the concepts of scan based testing, issues in testing, need for logic BIST and trends in VLSI testing. Scan
Chapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:
VLSI Design Verification and Test BIST II CMPE 646 Space Compaction Multiple Outputs We need to treat the general case of a k-output circuit.
Space Compaction Multiple Outputs We need to treat the general case of a k-output circuit. Test Set L m CUT k LFSR There are several possibilities: Multiplex the k outputs of the CUT. M 1 P(X)=X 4 +X+1
NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
Memory elements. Topics. Memory element terminology. Variations in memory elements. Clock terminology. Memory element parameters. clock.
Topics! Memory elements.! Basics of sequential machines. Memory elements! Stores a value as controlled by clock.! May have load signal, etc.! In CMOS, memory is created by:! capacitance (dynamic);! feedback
Scanned by CamScanner
NAVEEN RAJA VELCHURI DSD & Digital IC Applications Example: 2-bit asynchronous up counter: The 2-bit Asynchronous counter requires two flip-flops. Both flip-flop inputs are connected to logic 1, and initially
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September-2014 917 The Power Optimization of Linear Feedback Shift Register Using Fault Coverage Circuits K.YARRAYYA1, K CHITAMBARA
UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3)
Logic esign ( Part ) Sequential Logic- Finite State Machines (Chapter ) Based on slides McGraw-Hill Additional material 00/00/006 Lewis/Martin Additional material 008 Roth Additional material 00 Taylor
國立清華大學電機系 EE-6250 超大型積體電路測試. VLSI Testing. Chapter 7 Built-In Self-Test. Design-for-Testability
1 國立清華大學電機系 EE-6250 超大型積體電路測試 VLSI Testing Chapter 7 Built-In Self-Test esign-for-testability esign activities for generating a set of test patterns with a high fault coverage. Methodology Logic Automatic
Section 6.8 Synthesis of Sequential Logic Page 1 of 8
Section 6.8 Synthesis of Sequential Logic Page of 8 6.8 Synthesis of Sequential Logic Steps:. Given a description (usually in words), develop the state diagram. 2. Convert the state diagram to a next-state
L11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
Page 1 of 6 Follow these guidelines to design testable ASICs, boards, and systems. (includes related article on automatic testpattern generation basics) (Tutorial) From: EDN Date: August 19, 1993 Author:
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
Synchronous Sequential Logic
Synchronous Sequential Logic -A Sequential Circuit consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing
Sequencing. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Sequencing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2013 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Introduction Sequencing
System IC Design: Timing Issues and DFT. Hung-Chih Chiang
System IC esign: Timing Issues and FT Hung-Chih Chiang Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability
Built-In Self-Testing of Micropipelines
Built-In Self-Testing of Micropipelines O. A. Petlin, S. B. Furber Department of Computer Science University of Manchester Manchester, M13 9PL, UK email: {oleg, sfurber}@cs.man.ac.uk tel. +44 (0161) 275-3547
Logic Design Viva Question Bank Compiled By Channveer Patil
Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1
Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \
![Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \](/thumbs/84/89678649.jpg "Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \")
Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa
ECE 407 Computer Aided Design for Electronic Systems. Testing and Design for Testability. Instructor: Maria K. Michael. Overview
407 Computer Aided Design for Electronic Systems Testing and Design for Testability Instructor: Maria K. Michael MKM - 1 Overview VLSI realization process Role of testing, related cost Basic Digital VLSI
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
COMP2611: Computer Organization. Introduction to Digital Logic
1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once
Chapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
Experiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
Combinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
Combinational / Sequential Logic
Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output
IT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
Implementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters
IOSR Journal of Mechanical and Civil Engineering (IOSR-JMCE) e-issn: 2278-1684, p-issn: 2320-334X Implementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters N.Dilip
DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE
DESIGN OF RANDOM TESTING CIRCUIT BASED ON LFSR FOR THE EXTERNAL MEMORY INTERFACE Mohammed Gazi.J 1, Abdul Mubeen Mohammed 2 1 M.Tech. 2 BE, MS(IT), AMISTE ABSTRACT In the design of a SOC system, random
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
TKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics
EECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review. Announcements
EECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review September 1, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
Chapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
CPS311 Lecture: Sequential Circuits
CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem.
State Reduction The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem. State-reduction algorithms are concerned with procedures for reducing the
Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
EEE2135 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과
EEE235 Digital Logic Design Chapter 6. Latches/Flip-Flops and Registers/Counters 서강대학교 전자공학과 . Delay and Latches ) Signal Storage a. as voltage level static memory b. as charges dynamic memory 2) Delays
1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
hochschule fu r angewandte wissenschaften hamburg Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik
8 Shift Registers A Johnson counter contains the basic structure of a shift register which is made up by a chain of D- FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can
UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.
UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. Digital computer is a digital system that performs various computational tasks. The word DIGITAL
CS8803: Advanced Digital Design for Embedded Hardware
Copyright 2, 23 M Ciletti 75 STORAGE ELEMENTS: R-S LATCH CS883: Advanced igital esign for Embedded Hardware Storage elements are used to store information in a binary format (e.g. state, data, address,
CHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
Read-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus
Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable
Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari
Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory
Design of BIST Enabled UART with MISR
International Journal of Emerging Engineering Research and Technology Volume 3, Issue 8, August 2015, PP 85-89 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) ABSTRACT Design of BIST Enabled UART with
UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.