CDB5343. CDB5343: Evaluation Board for CS5343. Description. Features

Transcription

1 CD5343: Evaluation oar for C5343 CD5343 eatures Description Demonstrates Recommene Layout an Grouning Arrangements C8406 Generates /PDI an EIAJ-340- Compatible Digital Auio Requires Only an Analog ignal ource an Power upply for a Complete Analogto-Digital Converter ystem The CD5343 evaluation boar is an excellent means for quickly evaluating the C bit, stereo A/D converter. Evaluation requires a igital signal analyzer, an analog source, an a power supply. Also inclue is an C8406 igital auio interface transmitter that generates /PDI an EIAJ-340-compatible auio ata. The igital auio ata is available via RCA phone an optical connectors. ANALOG INPUT C , 96 k, Auio A/D Converter C8406 AE/EU /PDI TRANMITTER /PDI OUTPUT I/O OR CLOCK AND DATA Copyright Cirrus Logic, Inc (All Rights Reserve) AUGUT '06 D687D2

2 TALE O CONTENT CD YTEM OVERVIEW C C8406 DIGITAL AUDIO TRANMITTER CRYTAL OCILLATOR CLOCK & DATA I/O HEADER Clock & Data Routing MCLK ource ub-clock ource Data Routing POWER GROUNDING AND POWER UPPLY DECOUPLING ANALOG INPUT CONNECTOR JUMPER AND WITCH ETTING Jumper J witch C C MCLK CLK, LRCK PEED MCLK/LRCK Ratio REET EVALUATING THE C PERORMANCE PLOT CD PERORMANCE CURVE Total Harmonic Distortion + Noise (THD+N) Tlm CD CHEMATIC CD LAYOUT REVIION HITORY D687D2

3 LIT O IGURE CD5343 igure 1. T (-1 48 k)... 9 igure 2. T (, 48 k)... 9 igure 3. T (48 k, No Input)... 9 igure k, THD+N vs. Input req... 9 igure k, THD+N vs. Level... 9 igure k, ae-to-noise Linearity... 9 igure k, requency Response igure k, Crosstalk igure 9. T (-1 96 k) igure 10. T (, 96 k) igure 11. T (96 k, No Input) igure k, THD+N vs. Input req igure k, THD+N vs. Level igure k, ae-to-noise Linearity igure k, requency Response igure k, Crosstalk igure 17. CD5343 THD+N Performance igure 18. T from CD5343 Output igure 19. CD lock Diagram igure 20. C5343 Analog-to-Digital Converter igure 21. Analog Input igure 22. witches, Crystal Oscillator, an Clock Routing igure 23. C8406 /PDI Transmitter igure 24. Power igure 25. CD ilk-creen igure 26. Topsie Layer igure 27. ottomsie Layer LIT O TALE Table 1. ystem Connections... 6 Table 2. CD ettings... 6 D687D2 3

4 1. YTEM OVERVIEW CD5343 The CD5343 evaluation boar is an excellent tool for evaluating the C5343 Analog-to-Digital Converter (ADC). A minimum number of passive components conition the analog input signal prior to the C5343, an the on-boar C8406 igital auio interface transmitter provies an easy interface to igital auio signal analyzers incluing the majority of igital auio test equipment. Aitionally, the CD5343 features an interface heaer (J3) for clock an ata I/O. igures 19 through igures 27 show the CD5343 schematic an layout. 1.1 C5343 The C5343 ADC performs stereo 24-bit A/D conversion at sample rates of up to 108 k an generates I² auio format ata. urthermore, in both Master an lave Moes the C5343 supports MCLK/LRCK ratios of 256x an 384x. The C5343 prouct atasheet contains complete evice information. 2. C8406 DIGITAL AUDIO TRANMITTER The C8406 converts the C5343 output to a stanar /PDI ata stream. Given an MCLK/LRCK ratio equal to 256x, the C8406 can operate as clock master or clock slave, but the C8406 cannot be use with an MCLK/LRCK ratio of 384x on this boar. Moreover, by efault on this boar, the C8406 accepts only I² auio format; however, ection 11. on page 8 escribes the proceure of configuring the evice for Left-Justifie auio format. ee the C8406 ata sheet for complete evice information. 3. CRYTAL OCILLATOR Oscillator Y1 provies an on-boar system master clock. The oscillator is mounte in pin sockets, allowing for easy removal or replacement. The boar inclues a M crystal oscillator populate at Y1. 4. CLOCK & DATA I/O HEADER Heaer J3 makes interfacing to external systems easy. MCLK irection is controlle by switch 1, as is the irection of the sub-clocks, CLK an LRCK. The heaer pins associate with MCLK, CLK, an LRCK can accept 3.3 V or 5 V input signals, but are fixe at 3.3 V when set as outputs. DOUT is always a 3.3 V output. 4.1 Clock & Data Routing The user can configure the source an estinations of the clocks require to support the operation of the C5343. ection through ection iscuss vali configurations MCLK ource The C5343 an C8406 must receive a Master Clock. MCLK can come from either the crystal oscillator installe at Y1 or via heaer J3. Heaer J3 can accept a 3.3 V or 5 V logic-level MCLK when configure as an input, but will output MCLK only at 3.3 V when configure as an output ub-clock ource CLK an LRCK comprise the system sub-clocks an must be either provie to, or generate by, the C D687D2

5 CD5343 The C5343 generates sub-clocks when it is set for Master Moe via DIP switch 1. In this scenario, the C8406 shoul be set to lave Moe to receive sub-clocks. imilarly, the CLK, LRCK switch shoul be close to irect sub-clocks to the heaer. The sub-clock output of the J3 heaer is fixe at 3.3 V. If the user configures the C5343 for lave Moe, the evice must receive sub-clocks either from the C8406 or from an external source via heaer J3. If the C8406 is the intene sub-clock source, DIP switch 1 must be set such that the C8406 is in Master Moe an CLK, LRCK are route to the heaer. If both the C5343 an the C8406 are set to lave Moe, DIP switch 1 must inicate that the subclocks come ROM HDR. ub-clock input to heaer J3 may be either 3.3 V or 5 V Data Routing 5. POWER Auio ata from the C5343 DOUT pin is route to heaer J3 an the C8406. The DOUT pin of J3 is always a 3.3 V output. The C5343 prouces ata in only I² auio format; therefore the ata capture evice shoul be set accoringly. The C8406 accepts ata in I² auio format, which it converts to /PDI an EIAJ-340-compatible ata. This ata is available for capture from either the optical connector (J9) or the RCA jack (J6). Power must be supplie to the evaluation boar through the +5 V bining post (J2). The +5 V input must be reference to the single black bining post groun connector (J1). WARNING: Please refer to the C5343 ata sheet for allowable voltage levels. 6. GROUNDING AND POWER UPPLY DECOUPLING To optimize performance, PC esigns supporting the C5343 require careful attention to power supply, grouning, an signal routing. igures 26 an 27 show the basic component/signal interconnect for the CD5343, an igure 25 shows the component placement. These figures emonstrate the optimal layout of components use to support the C5343. or example, these figures show that the ecoupling capacitors are locate as close to the C5343 as possible. The layout also shows extensive use of groun plane fill which greatly reuces raiate noise. 7. ANALOG INPUT The user can input single-ene analog signals via the RCA connectors, J5 an J7. A 2 Vrms single-ene signal into the RCA connectors will rive the C5343 inputs to full scale (1 Vrms for VA = 5 V). The input network on the CD5343 was esigne to emonstrate that the C5343 will achieve full performance with a source impeance up to 2.5 kω (looking back from the C5343 inputs) while allowing for 2 Vrms inputs. Another avantage of this circuit is that it provies an input impeance of 10 kω, similar to many commercial auio proucts. D687D2 5

6 CD CONNECTOR Table 1 lists the connectors on the CD5343, the reference esignator of each connector, the irectionality, an the associate signal. CONNECTOR REERENCE DEIGNATOR INPUT/OUTPUT IGNAL +5V J2 INPUT +5 V power to crystal oscillator an DC voltage regulator GND J1 INPUT Groun connection from the power supply AINR J7 INPUT Analog input right channel AINL J5 INPUT Analog input left channel Co-axial J6 OUTPUT Digital auio (/PDI) output Optical J9 OUTPUT Digital auio (/PDI) output I/O HDR J3 INPUT/OUTPUT Master Clock, erial Clock, Left/Right Clock, DOUT 9. JUMPER AND WITCH ETTING The user can fully configure the CD5343 with a bank of six DIP switches (1) an a single jumper setting on heaer J Jumper J4 This jumper selects the magnitue of VA, either 3.3 V or 5 V. The C5343 is a single-supply evice; therefore the magnitue of VA affects the full-scale analog input voltage as well as the igital I/O voltage. Digital I/O is always fixe at VA, an the full-scale input is nominally 0.56xVA Vpp, as specifie in the C5343 ata sheet. If the user selects 5 V, the C5343 full-scale analog input voltage is 2.82 Vpp (1 Vrms) an the igital I/O is set to 5 V. If 3.3 V is selecte, the full-scale analog input voltage is 1.86 Vpp (660 mvrms) an igital I/O is 3.3 V. 9.2 witch 1 Table 2 shows the available settings for 1 with the efault settings. OPEN CLOED C5343 MATER (efault) LAVE C8406 MATER LAVE (efault) MCLK ROM HDR TO HDR (efault) CLK, LRCK ROM HDR TO HDR (efault) PEED DM M (efault) MCLK/LRCK 256x (efault) 384x C5343 Table 1. ystem Connections Table 2. CD ettings This switch configures the C5343 for either Master Moe or lave Moe operation. When set as clock Master, the C8406 must be set to lave an CLK, LRCK must be set to TO HDR. When C5343 is configure for lave Moe, the C8406 must be set for Master Moe, or CLK, LRCK must be set to ROM HDR. 6 D687D2

7 CD5343 Changing the state of this switch while the evice is running will have no effect on the C5343 as it must be reset to etect the change. Reset is accomplishe by removing an restoring power to the evice. Alternatively, removing an restoring MCLK will initiate a reset of the igital section, which is also sufficient for the C5343 to etect a change in moe settings C MCLK This switch sets the C8406 for either Master Moe or lave Moe. In Master Moe, the C5343 must be configure as a clock slave an CLK, LRCK set to TO HDR. In lave Moe, either the C5343 can be set to Master Moe or the user can set the CLK, LRCK switch to ROM HDR. MCLK can either come from the heaer, as selecte by ROM HDR, or from the on-boar crystal oscillator (Y1) as selecte by TO HDR CLK, LRCK PEED The sub-clocks, CLK an LRCK, are either prouce on boar by the C5343 or the C8406 or prouce externally. If generate by an external evice, this switch must be set to ROM HDR. If the C5343 or C8406 generate the sub-clocks, this switch must be set to ROM HDR. The C5343 can operate in ingle-pee Moe (M) or Double-pee Moe (DM) as escribe in the C5343 prouct atasheet. In Master Moe, the C5343 efaults to M base on an internal 100 kω pull-up resistor from the LRCK pin to VA. etting the PEED switch to DM will place a 10 kω pull-own resistor between LRCK an GND to select Double-pee Moe. ecause the C5343 etermines its Master Moe spee base on start-up options, the spee moe cannot be toggle uring operation. To change the spee in Master Moe, the evice must be reset by removing an restoring power or removing an restoring MCLK. This switch also configures the MCLK/LRCK ratio for the C8406. electing M configures the C8406 for a 512x MCLK/LRCK ratio while DM sets an MCLK/LRCK ratio of 256x. In this esign, the C8406 cannot support of a 384x MCLK/LRCK ratio MCLK/LRCK Ratio This switch will configure the C5343 for either a 256x MCLK/LRCK ratio or a 384x MCLK/LRCK ratio in Master Moe. In lave Moe the C5343 auto-etects the MCLK/LRCK ratio; therefore this configuration step is unnecessary in lave Moe. In Master Moe, selection of this parameter is performe via a startup option. An internal 100 kω pull-up resistor from the CLK pin to VA will select 256x by efault. An external 10 kω pull-own resistor from the CLK pin to GND will select an MCLK/LRCK ratio of 384x. Typical applications that use a 384x MCLK/LRCK ratio erive a 48 k LRCK from a M MCLK. Deriving MCLK from the inclue M crystal oscillator will result in a sample rate of 32 k. The C8406 is not configure to support a 384x MCLK/LRCK ratio in this esign; therefore analysis in this moe must be performe by retrieving ata through the interface heaer (J3). D687D2 7

8 10.REET CD5343 The C5343 features Power-On Reset which means that performing a full reset of the C5343 requires a powercycling the evice. On the CD5343, this can be accomplishe with by removing an restoring the power-supply or by removing an restoring the jumper on J3. Alternatively, removing an restoring MCLK to the evice will effect a reset of just the igital portion of the evice. The evice enters Power-Down Moe when MCLK is remove an raws less current. 11.EVALUATING THE C5344 The CD5343 comes with only the C5343 ADC installe, but some users may want to evaluate the pin-compatible C5344 ADC. The two evices perform equivalently, but the C5344 prouces only Left-Justifie auio format ata; whereas the C5343 creates only I² auio format ata. y following the four easy steps liste below, the user can moify the CD5343 to accommoate the C5344. tep 1: Remove C5343 populate at U6 tep 2: Install C5344 at U6 tep 3: Remove 0 Ω resistor populate at R36 (this resistor selects I² Auio ormat for the C8406) tep 4: Install 0 Ω resistor at R43 (this resistor selects LJ Auio ormat for the C8406) 8 D687D2

9 12.PERORMANCE PLOT CD igure 1. T (-1 48 k) igure 2. T (, 48 k) igure 3. T (48 k, No Input) igure k, THD+N vs. Input req +40 T T TT TTTT T T T T T r r igure k, THD+N vs. Level igure k, ae-to-noise Linearity D687D2 9

10 CD igure k, requency Response igure k, Crosstalk igure 9. T (-1 96 k) igure 10. T (, 96 k) igure 11. T (96 k, No Input) igure k, THD+N vs. Input req 10 D687D2

11 CD T T T T T T r r igure k, THD+N vs. Level igure k, ae-to-noise Linearity igure k, requency Response igure k, Crosstalk D687D2 11

12 12 D687D2 13.CD PERORMANCE CURVE 13.1 Total Harmonic Distortion + Noise (THD+N) igure 17 shows typical THD+N performance of the C5343 installe on the CD5343. Performance curves are isplaye for each channel with the C5343 running at ingle-pee in both Master an lave Moes an for VA voltages of both +3.3 V an 5 V. T k CD5343 (Rev A evice) THD+N vs. requency 4k 6k 8k 10k 12k 14k 16k 18k weep Trace Color Line tyle Thick Data Axis Comment 1 1 lue oli 1 DP Anlr.THD+N Ampl A Left 5V Master M 256x 1 2 lue oli 1 DP Anlr.THD+N Ampl Right 5V Master M 256x 2 1 Re oli 1 DP Anlr.THD+N Ampl A Left 5V lave M 256x 2 2 Re oli 1 DP Anlr.THD+N Ampl Right 5V lave M 256x 3 1 Green oli 1 DP Anlr.THD+N Ampl A Left 3.3 V lave M 256x 3 2 Green oli 1 DP Anlr.THD+N Ampl Right 3.3 V lave M 256x 4 1 Yellow oli 1 DP Anlr.THD+N Ampl A Left 3.3 V lave M 256x 4 2 Yellow oli 1 DP Anlr.THD+N Ampl Right 3.3 V lave M 256x igure 17. CD5343 THD+N Performance 20k CD5343

13 D687D Tlm igure 18 shows a typical T of the output from the C5343 on the CD5343 with a 2 Vrms, 1 k sinewave input. or this plot, the evice was configure for ingle-pee Moe with VA = 5 V. C5343 T, 1 k ull-scale Input, VA = 5 V, M Master Moe weep Trace Color Line tyle Thick Data Axis Comment 1 1 lue oli 1 ft.ch.1 Ampl Left 1 2 Re oli 1 ft.ch.2 Ampl Right igure 18. T from CD5343 Output CD5343

14 D687D CD CHEMATIC igure 19. CD lock Diagram CD5343

15 D687D2 15 igure 20. C5343 Analog-to-Digital Converter CD5343

16 CD5343 igure 21. Analog Input D687D2 16

17 D687D2 17 igure 22. witches, Crystal Oscillator, an Clock Routing CD5343

18 D687D2 18 igure 23. C8406 /PDI Transmitter CD5343

19 CD5343 igure 24. Power 19 D687D2

20 20 D687D2 15.CD LAYOUT igure 25. CD ilk-creen CD5343

21 CD5343 igure 26. Topsie Layer D687D2 21

22 CD5343 igure 27. ottomsie Layer 22 D687D2

23 CD REVIION HITORY Release D1 D2 Initial Release Ae Performance Plots Changes Contacting Cirrus Logic upport or all prouct questions an inquiries, contact a Cirrus Logic ales Representative. To fin the one nearest you, go to IMPORTANT NOTICE Cirrus Logic, Inc. an its subsiiaries ("Cirrus") believe that the information containe in this ocument is accurate an reliable. However, the information is subject to change without notice an is provie "A I" without warranty of any kin (express or implie). Customers are avise to obtain the latest version of relevant information to verify, before placing orers, that information being relie on is current an complete. All proucts are sol subject to the terms an conitions of sale supplie at the time of orer acknowlegment, incluing those pertaining to warranty, inemnification, an limitation of liability. No responsibility is assume by Cirrus for the use of this information, incluing use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of thir parties. This ocument is the property of Cirrus an by furnishing this information, Cirrus grants no license, express or implie uner any patents, mask work rights, copyrights, traemarks, trae secrets or other intellectual property rights. Cirrus owns the copyrights associate with the information containe herein an gives consent for copies to be mae of the information only for use within your organization with respect to Cirrus integrate circuits or other proucts of Cirrus. This consent oes not exten to other copying such as copying for general istribution, avertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATION UING EMICONDUCTOR PRODUCT MAY INVOLVE POTENTIAL RIK O DEATH, PERONAL INJURY, OR EVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATION ). CIRRU PRODUCT ARE NOT DEIGNED, AUTHORIZED OR WARRANTED OR UE IN AIRCRAT YTEM, MILITARY APPLICATION, PRODUCT URGICALLY IMPLANTED INTO THE ODY, AUTOMOTIVE AETY OR ECURITY DE- VICE, LIE UPPORT PRODUCT OR OTHER CRITICAL APPLICATION. INCLUION O CIRRU PRODUCT IN UCH APPLICATION I UNDER- TOOD TO E ULLY AT THE CUTOMER RIK AND CIRRU DICLAIM AND MAKE NO WARRANTY, EXPRE, TATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIE O MERCHANTAILITY AND ITNE OR PARTICULAR PURPOE, WITH REGARD TO ANY CIRRU PRODUCT THAT I UED IN UCH A MANNER. I THE CUTOMER OR CUTOMER CUTOMER UE OR PERMIT THE UE O CIRRU PRODUCT IN CRITICAL APPLICATION, CUTOMER AGREE, Y UCH UE, TO ULLY INDEMNIY CIRRU, IT OICER, DIRECTOR, EMPLOYEE, DITRIUTOR AND OTHER AGENT ROM ANY AND ALL LIAILITY, INCLUDING ATTORNEY EE AND COT, THAT MAY REULT ROM OR ARIE IN CONNECTION WITH THEE UE. Cirrus Logic, Cirrus, an the Cirrus Logic logo esigns are traemarks of Cirrus Logic, Inc. All other bran an prouct names in this ocument may be traemarks or service marks of their respective owners. D687D2 23