Lab 3 : CMOS Sequential Logic Gates

Transcription

1 CARLETON UNIERSITY epartment of Electronics ELEC-3500 igital Electronics September 30, 2005 Lab 3 : CMOS Seuential Logic Gates esign an Specification of Seuential Logic Gates an Librar Cell igital esigns are compose of combinational logic (gates like last week s IN, NAN an NOR) an seuential elements which contain memor (Flip-Flops an latches). Be warne, o NOT use latches in real life. The ONLY exception is in the lab below where ou buil a flip-flop out of two latches for eucational purposes. In this lab ou will first buil a MUX, then use it to make a latch an then use the latch to create a flip-flop. The seuence of circuits ou will buil are: a) The MUX, both analog an igital. b) The latch built from a MUX c) The master-slave flip-flop, mae from latches.. The Mux The MUX switches an output between two inputs as ictate b a control signal. Here: if(= =) =; else =; Transmission-Gate MUX. Buil a MUX out of two of the transmission gates an an inverter. You will nee to put voltmeters at an. Signal Inputs Set the input waveform = 2, an = 0.5. This allows to be seen to change when the MUX switches from to. Ctrl Ctrl MUX G FIGURE 2. FIGURE pF 0.5 Q. Finish builing the TXGATE MUX as shown in FIGURE 2 from the provie circuits. Plot the output waveforms showing the an signals. Explain what is happening when the is high an when the is low. /home/gallan/courses/350/350_04_ta_fromraghi/lab3f5.fm IGITAL ELECTRONICS J.Knight, /3/94, moifie b

2 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, Testing the MUX etermine the propagation ela between the time the rises an the switche output appears at. This is calle t CHY (time from Control High to Y ali). Most of these propagation elas are measure between 50% points. Make the rise an fall times fast enough (uner ns). Otherwise ou will be reporting that t CHY is proportional to the input rise/fall time. The Spice pulse generator can be set from its attributes as shown in FIGURE 2.3. t RISE t ELAY FIGURE 2.3 t CHY t FALL t PULWITH t PERIO Q2. Recor t CHY an the similar signal t CLY (Control Low Y ali). 2. The -latch Convert the MUX to a -Latch. FIGURE 2.5b will work for a MUX constructe of gates but not transmission gates. The conservation of energ has everthing to o with this. A gate has gain. Q3. A components to our latch work to make it work with transmission gates. FIGURE 2.4 MUX mae from gates In orer to check the setup time of the latch one must change an clk at the same time. Use two suare-wave generators, has a perio about 0.25 ns faster than but with [(/2 perio) + 2ns] larger initial ela (TELAY). This will allow the an clk input eges to slie past each other. FIGURE 2.5 FIGURE 2.5b latch from a MUX MUX G 20K T L T L T L T L Testing The Latch Make sure our latch functions as a transparent latch. If the output ecas with time, ou are just looking at the storage on a charge capacitor. This is not a static latch! It will forget if the clock is slow. The 0K loa resistor was use to be sure the output eca woul be fast enough to see easil Q4. Sketch our circuit an the part of our test waveform that proves the latch functions as a transparent latch. FIGURE 2.6 C LATCH 0K. The emonstration Pspice is limite to 0 transistors. You will have to use the inverter mae without transistors or use the full Pspice simulator. Electronic Engineering September 30, 2005 page 2, of 5

3 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, The Setup Time If the input changes too close to the ege the input will not be capture as. However if the input is stable at least a setup time before the ege, the at stable value will be capture. Q5. Measure the setup time using our sliing waveforms. You ma want to exten the time of the simulation. Show a plot of where ou measure the setup time. Setup time approximate Note was capture as FIGURE 2.7 The smbol for a transmission gate is or Your latch shoul be as shown in FIGURE 2.8 or FIG- URE 2.9. A a 0.5pf capacitive loa to an see if that effects the setup time. Q6. Measure the new setup time. Comment on wh an output loa woul change the setup time which woul appear to be associate onl with the input. Commercial latches a an extra inverter as a buffer amplifier to keep the loa from influencing the setup time. Q The Hol Time Q The hol time is the length of time the signal must be stable after the clock changes FIGURE 2.9 to be sure of capturing the correct value. Goo latches have zero or even a negative hol time. The same sliing waveforms use to measure the setup time can also measure the hol time. Q7. Measure the hol time. FIGURE 2.0 testing for zero hol time 3. The Flip-Flop The master-slave flip-flop is mae b connecting two latches in series. The two are transparent on opposite clock eges. X FIGURE K Longer hol time neee Zero hol time Less than zero hol time STORE Q M STORE Q S Q MASTER SECTION FIGURE 2. SLAE SECTION /home/gallan/courses/350/350_04_ta_fromraghi/lab3f5.fmseptember 30, 2005 page 3, of 5

4 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, When the master is high it hols the output an the transparent slave lets it through. When the master goes transparent, the slave hols the previous output so it oes not change. CLOCK LOW CLOCK HIGH FIGURE 2.2 HOL HOL esign esign a flip-flop an implement a moel in Spice. Use the moel to etermine the following specifications: (i) the setup time, (ii) the hol time, (iii) the clock to output time t CHQ, eliverables: - Fill out a cover sheet. - emo our work to a TA. - Answer all uestions. Electronic Engineering September 30, 2005 page 4, of 5

5 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, /home/gallan/courses/350/350_04_ta_fromraghi/lab3f5.fmseptember 30, 2005 page 5, of 5