DATA SHEET. TDA8376; TDA8376A I 2 C-bus controlled PAL/NTSC TV processors INTEGRATED CIRCUITS Jan 26

Transcription

1 INTEGRATED CIRCUITS DATA SHEET I 2 C-bus controlled PAL/NTSC TV processors File under Integrated Circuits, IC Jan 26

2 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Video switches 7.2 Integrated video filters, peaking and black stretcher 7.3 Synchronization circuit 7.4 Colour decoder 7.5 RGB output circuit and black-current stabilization 8 I 2 C-BUS SPECIFICATION 8.1 Start-up procedure 8.2 Inputs Input control bits Output control bits 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 QUALITY SPECIFICATION 11.1 Latch-up 12 CHARACTERISTICS 13 TEST AND APPLICATION INFORMATION 13.1 East-West output stage 13.2 Adjustment of geometry control parameters 14 PACKAGE OUTLINES 15 SOLDERING 15.1 Introduction 15.2 SDIP Soldering by dipping or by wave Repairing soldered joints 15.3 QFP Reflow soldering Wave soldering Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I 2 C COMPONENTS 1996 Jan 26 2

3 1 FEATURES Source selection with 2 CVBS inputs and a Y/C (or extra CVBS) input Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor Video identification circuit which is independent of the synchronization for stable On Screen Display (OSD) under no-signal conditions Integrated chrominance trap with pre-shoot compensation and bandpass filters (automatically calibrated) Integrated luminance delay line Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function Black stretcher circuit in the luminance channel PAL/NTSC colour decoder with automatic search system Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications RGB control circuit with black-current stabilization and white point adjustment; to obtain a good grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment Two linear RGB inputs and fast blanking Horizontal synchronization with two control loops and alignment-free horizontal oscillator Vertical count-down circuit Geometry correction by modulation of the vertical and E-W drive Vertical and horizontal zoom possibility for 16 : 9 applications (TDA8376A only) I 2 C-bus control of various functions Low dissipation (700 mw) Small amount of peripheral components compared with competition ICs Y, U and V inputs and outputs. 2 GENERAL DESCRIPTION The TDA8376 and TDA8376A are alignment-free I 2 C-bus controlled video processors which contain a PAL/NTSC colour decoder, luminance processor, sync processor, RGB-control and deflection processor. The circuits have been designed for use with the baseband chrominance delay line TDA4665 and for DC-coupled vertical and East-West (E-W) output stages. Both ICs are pin compatible. The TDA8376A has a flexible horizontal and vertical zoom possibility for 16 : 9 applications. The supply voltage for the ICs is 8 V. The ICs are available in an SDIP package with 52 pins and in a QFP package with 64 pins (see Chapter 4). The pin numbers indicated in this document are referenced to the SDIP52; SOT247-1 package; unless otherwise indicated Jan 26 3

4 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT Supply V P supply voltage 8.0 V I P supply current 75 ma Input voltages V 9,13(p-p) CVBS input voltage (peak-to-peak value) 1.0 V V 27(p-p) S-VHS luminance input voltage (peak-to-peak value) 1.0 V V 6(p-p) S-VHS chrominance input voltage (burst amplitude) (peak-to-peak 0.3 V value) V i(p-p) RGB input voltage (peak-to-peak value) 0.7 V Output voltages V 38(p-p) TXT output voltage (peak-to-peak value) 1.0 V V 11(p-p) PIP output voltage (peak-to-peak value) 1.0 V V 30(p-p) (R Y) output voltage (peak-to-peak value) 525 mv V 29(p-p) (B Y) output voltage (peak-to-peak value) 675 mv V 19,20,21(p-p) RGB output signal voltage amplitudes (peak-to-peak value) 2.0 V Output currents I 40 horizontal output current 10 ma I 47,48 vertical output current 1 ma I 46 E-W drive output current 0.5 ma 4 ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION TDA8376 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 TDA8376AH QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body mm SOT Jan 26 4

5 1996 Jan GND1 42 GND2 V P1 (+8 V) SCL SDA HOUT PH1LF DEC BG DEC DIG TDA8376(A) 45 GND3 V P2 (+8 V) SW CVBS SWITCH 9 13 I 2 C-BUS TRANSCEIVER CONTROL DACs 16 x 6 bits 2 x 4 bits VIDEO IDENTIFICATION TRAP BAND PASS SW S-VHS SWITCH CVBS/Y HUE dbook, full pagewidth VCO AND CONTROL SYNC SEPARATOR AND 1st LOOP VERTICAL SYNC SEPARATOR FILTER TUNING PAL/NTSC DECODER DET DEC FT CVBS EXT PIPO 4.4 CVBS INT CHROMA CVBS/TXT MHz SEC ref ref MHz ref XTAL2 XTAL1 FBI PH2LF 2nd LOOP AND HORIZONTAL OUTPUT HORIZONTAL/ VERTICAL DIVIDER BLACK STRETCHER DELAY, PEAKING AND CORING G-Y MATRIX AND SAT CONTROL TDA4665 SAT SCO WHITE POINT EW GEOMETRY VERTICAL GEOMETRY BLACK CURRENT STABILIZER BRI CONTR RGB MATRIX AND OUTPUT RGB INPUT AND SWITCH RYO BYO RYI BYI Fig.1 Block diagram (SDIP52; SOT247-1). LUMIN LUMOUT RI1 GI1 BI1 RGBIN EWD EHTO VDR (p) VDR (n) VSC I ref C BLK BLKIN BCLIN RO GO BO RGBIN2 RI2 GI2 BI2 MGE078 5 BLOCK DIAGRAM Philips Semiconductors

6 6 PINNING PIN SYMBOL SDIP52 QFP64 DESCRIPTION DEC DIG 1 11 decoupling digital supply C BLK 2 12 black peak hold capacitor SCL 3 13 I 2 C-bus serial clock input SDA 4 14 I 2 C-bus serial data input/output DEC BG 5 16 band gap decoupling CHROMA 6 17 chrominance input (S-VHS) CVBS/Y 7 18 external CVBS/Y input V P main supply voltage (+8 V) CVBS INT 9 22 internal CVBS input GND ground 1 PIPO picture-in-picture output DEC FT decoupling filter tuning CVBS EXT external CVBS input RGBIN RGB insertion input 2 RI red input 2 GI green input 2 BI blue input 2 BLKIN black-current input BO blue output GO green output RO red output BCLIN beam current limiter input RI red input 1 GI green input 1 BI blue input 1 RGBIN RGB insertion input 1 LUMIN luminance input LUMOUT luminance output BYO (B Y) signal output RYO (R Y) signal output BYI (B Y) signal input RYI (R Y) signal input XTAL MHz crystal connection XTAL /3.58 MHz crystal connection DET loop filter phase detector SEC ref SECAM reference output V P horizontal oscillator supply voltage (+8 V) CVBS/TXT CVBS/TXT output 1996 Jan 26 6

7 PIN SYMBOL SDIP52 QFP64 DESCRIPTION SCO sandcastle output HOUT horizontal output FBI flyback input GND ground 2 PH2LF phase-2 filter PH1LF phase-1 filter GND ground 3 EWD 46 1 east-west drive output VDR (p) 47 3 vertical drive 1 positive output VDR (n) 48 4 vertical drive 2 negative output EHTO 49 5 EHT/overvoltage protection input VSC 50 7 vertical sawtooth capacitor I ref 51 8 reference current input n.c not connected n.c. 6 not connected n.c. 9 not connected n.c. 10 not connected n.c. 15 not connected n.c. 19 not connected n.c. 33 not connected n.c. 48 not connected n.c. 50 not connected n.c. 52 not connected V P3 21 supply voltage 3 (+8 V) GND4 61 ground 4 GND5 64 ground Jan 26 7

8 handbook, halfpage DEC DIG 1 52 n.c. C BLK 2 51 I ref SCL 3 50 VSC SDA 4 49 EHTO DEC BG 5 48 VDR (n) CHROMA 6 47 VDR (p) CVBS/Y 7 46 EWD V P GND3 CVBS INT 9 44 PH1LF GND PH2LF PIPO GND2 DEC FT FBI CVBS EXT RGBIN TDA8376(A) 39 HOUT SCO RI CVBS/TXT GI V P2 BI SEC ref BLKIN DET BO XTAL2 GO XTAL1 RO RYI BCLIN BYI RI RYO GI BYO BI LUMOUT RGBIN LUMIN MGE076 Fig.2 Pin configuration (SDIP52) Jan 26 8

9 handbook, full pagewidth EWD 1 51 GND5 PH1LF PH2LF GND4 GND3 FBI HOUT SCO CVBS/TXT V P2 SEC ref DET n.c. XTAL2 n.c n.c. VDR (p) 3 49 XTAL1 VDR (n) 4 48 n.c. EHTO 5 47 RYI n.c BYI VSC 7 45 RYO I ref 8 44 BYO n.c LUMOUT n.c. 10 TDA8376(A) 42 LUMIN DEC DIG RGBIN1 C BLK BI1 SCL GI1 SDA RI1 n.c BCLIN DEC BG RO CHROMA GO CVBS/Y BO n.c n.c. MGE077 V P1 V P3 CVBS INT GND1 GND2 PIPO DEC FT CVBS EXT RGBIN2 RI2 GI2 BI2 BLKIN Fig.3 Pin configuration (QFP64) Jan 26 9

10 7 FUNCTIONAL DESCRIPTION 7.1 Video switches The circuit has two CVBS inputs and a Super-Video Home System (S-VHS) input. The input can be chosen by the I 2 C-bus. The input selector also has a position in which CVBS EXT is processed, unless there is a signal on the S-VHS input. When the input selector is in this position it switches to the S-VHS input if the S-VHS detector detects sync pulses on the S-VHS luminance input. The S-VHS detector output can be read by the I 2 C-bus. When the S-VHS option is not used the luminance input can be used as a second input for external CVBS signals. The choice is made via the CVS bit (see Table 1). The video switch circuit has two outputs which can be programmed in a different way. The input signal for the decoder is also available on the TXT output. Therefore this signal can be used to drive the teletext decoder and the SECAM add-on decoder. The signal on the PIP output can be chosen independent of the TXT output. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. The circuit contains a video identification circuit which checks whether a video signal is available at the selected video input. This circuit is independent of the synchronization circuit. The information of this identification circuit can also be used to switch the phase-1 (ϕ 1 ) loop to a low gain when no signal is received so that a stable OSD display is obtained. The video identification circuit can be switched on and off via the I 2 C-bus. 7.2 Integrated video filters, peaking and black stretcher The circuit contains a chrominance bandpass and trap circuit. The chrominance trap filter in the luminance path is designed for a symmetrical step response behaviour. The filters are realized by gyrator circuits and they are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by gyrator circuits. During SECAM reception the centre frequency of the chrominance trap is set to a value of approximately 4.2 MHz to obtain a better suppression of the SECAM carrier frequencies. The peaking function is achieved by two luminance delay cells each with a delay of 165 ns. The resulting peaking frequency is 3 MHz. The peaking is asymmetrical so that the overshoots in the direction of black are approximately two times higher than those in the direction of white. This provides a better picture impression than a symmetrical peaking. The circuit contains a coring circuit to prevent the noise content of the video signal being amplified by the peaking circuit. This coring circuit can be switched-off when required. It is possible to connect a Colour Transient Improvement (CTI) or Picture Signal Improvement (PSI) IC to the TDA8376. The luminance signal which has passed the filter and delay line circuit is available externally. The output signal of the transient improvement circuit must be applied to the luminance input circuit. When the CTI function is not required the two pins must be AC-coupled. The luminance signal below 50 IRE can be stretched in accordance with the difference between the peak black level and the blanking level of the back-porch of the video signal. The black level stretcher can be switched-off by connecting pin 2 to the positive supply line. 7.3 Synchronization circuit The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is only used to detect whether the line oscillator is synchronized and not for transmitter identification. The first Phase-Locked Loop (PLL) has a very high-statical steepness so that the phase of the picture is independent of the line frequency. To prevent the horizontal synchronization being disturbed by anti-copy signals such as Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The position of this pulse is asymmetrical and the width is approximately 22 µs. The horizontal output signal is generated by an oscillator which operates at twice the line frequency. Its frequency is divided-by-two to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched on Jan 26 10

11 To obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty factor of the output pulse has such a value that maximum safety is obtained for the output stage To protect the horizontal output transistor the horizontal drive is switched off when a power-on reset is detected. The drive signal is switched on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. To prevent the horizontal output transistor being switched on during flyback the horizontal drive output is gated with the flyback pulse. The vertical sawtooth generator drives the vertical output and E-W correction drive circuits. The geometry processing circuits provide control of horizontal shift, E-W width, E-W parabola/width ratio, E-W corner/parabola ratio, trapezium correction, vertical shift, vertical slope, vertical amplitude, and the S-correction. All these controls can be set via the I 2 C-bus. The geometry processor has a differential current output for the vertical drive signal and a single-ended output for the E-W drive. Both the vertical drive and the E-W drive outputs can be modulated for EHT compensation. The EHT compensation pin is also used for overvoltage protection. The TDA8376A geometry processor also offers the possibility for a flexible vertical and horizontal zoom mode for 16 : 9 applications. Because of this feature an additional control can be added on the remote control so that the viewer can adjust the picture. In addition the de-interlace of the vertical output can be set via the I 2 C-bus. To avoid damage of the picture tube when the vertical deflection fails, the guard output current of the TDA8350 can be supplied to the sandcastle output. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled by the EVG bit of subaddress 0A (see Table 1). 7.4 Colour decoder The colour decoder contains an alignment-free crystal oscillator, a killer circuit and the colour difference demodulators. The 90 phase shift for the reference signal is made internally. The demodulation angle and gain ratio for the colour difference signals for PAL and NTSC are adapted to the standard. The colour decoder is very flexible. Together with the SECAM decoder TDA8395 an automatic multistandard decoder can be designed. In the automatic mode the SECAM identification is accepted only when the vertical frequency is 50 Hz. In the forced mode the system can also identify signals with a vertical frequency of 60 Hz. Which standard the IC can decode depends on the external crystals. If a 4.4 MHz and a 3.5 MHz crystal are used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be decoded. If two 3.5 MHz crystals are used PAL N and M can be decoded. If one crystal is connected only PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The crystal frequency of the decoder is used to tune the line oscillator. Therefore the value of the crystal frequency must be given to the IC via the I 2 C-bus. For a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (XA and XB) are not corrupted (see Table 6). For this reason the crystal bits (SXA and SXB) can be read in the output bytes so that the software can check the I 2 C-bus transmissions (see Table 38). 7.5 RGB output circuit and black-current stabilization The colour-difference signals are matrixed with the luminance signal to obtain the RGB-signals. For the RGB-inputs linear amplifiers have been chosen so that the circuit is suited for signals coming from the SCART connector. The RGB2 inputs (pins 14 to 17) have priority over the RGB1 inputs (pins 23 to 26). Both fast blanking inputs can be blocked by I 2 C-bus controls. The contrast and brightness controls operate on internal and external signals Jan 26 11

12 The output signal has an amplitude of approximately 2 V black-to-white at nominal input signals and nominal settings of the controls. The black current stabilization is realized by feedback from the video output amplifiers to the RGB control circuit. The black current of the 3 guns of the picture tube is internally measured and stabilized. The black level control is active during 4 lines at the end of the vertical blanking. During the first line the leakage current is measured and the following 3 lines the 3 guns are adjusted to the required level. The maximum acceptable leakage current is ±100 µa. The nominal value of the black current is 10 µa. The ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point. The input impedance of the black-current measuring pin is 15 kω. Therefore the beam current during scan will cause the input voltage to exceed the supply voltage. The internal protection will start conducting so that the excessive current is bypassed. When the TV receiver is switched on the black current stabilization circuit is not active, the RGB outputs are blanked and beam current limiting input pin is short-circuited. Only during the measuring lines will the outputs supply a voltage of 5 V to the video output stage so that it can be detected if the picture tube is warming up. These pulses are switched on after a waiting time of approximately 0.5 s. This ensures that the vertical deflection is activated so that the measuring pulses are not visible on the screen. As soon as the current supplied to the measuring input exceeds a value of 190 µa the stabilization circuit is activated. After a waiting time of approximately 0.8 s the blanking and the beam current limiting input pin are released. The remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. 8 I 2 C-BUS SPECIFICATION handbook, halfpage A6 A5 A4 A3 A2 A1 A /0 Valid subaddresses: 00 to 13 (TDA8376) or 00 to 16 (TDA8376A); subaddress FE is reserved for test purposes. Auto-increment mode is available for subaddresses. 8.1 Start-up procedure Fig.4 Slave address (8A). R/W MLA743 Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, the procedure previously mentioned must be carried out to restart the IC. When this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip Jan 26 12

13 8.2 Inputs Table 1 Input status bits FUNCTION SUBADDRESS DATA BYTE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 Source select 00 INA INB INC IND FOA FOB XA XB Decoder mode 01 FORF FORS DL STB POC CM2 CM1 CM0 Hue A5 A4 A3 A2 A1 A0 Horizontal shift (HS) A5 A4 A3 A2 A1 A0 E-W width (E-W) A5 A4 A3 A2 A1 A0 E-W parabola/width (PW) A5 A4 A3 A2 A1 A0 E-W corner parabola (CP) A5 A4 A3 A2 A1 A0 E-W trapezium (TC) A5 A4 A3 A2 A1 A0 Vertical slope (VS) 08 NCIN 0 A5 A4 A3 A2 A1 A0 Vertical amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0 S-correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0 Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0 White point R 0C EXP (1) CL (1) A5 A4 A3 A2 A1 A0 White point G 0D 0 CVS A5 A4 A3 A2 A1 A0 White point B 0E MAT 0 A5 A4 A3 A2 A1 A0 Peaking 0F YD3 YD2 YD1 YD0 A3 A2 A1 A0 Brightness 10 RBL COR A5 A4 A3 A2 A1 A0 Saturation 11 IE1 IE2 A5 A4 A3 A2 A1 A0 Contrast A5 A4 A3 A2 A1 A0 Spare Spare Spare Vertical zoom (VX, 76A) A5 A4 A3 A2 A1 A0 Note 1. The bits EXP and CL in subaddress 0C are only valid for the TDA8376. For the TDA8376A these two bits must be set to logic 0. Table 2 Output status bits FUNCTION SUBADDRESS DATA BYTE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 Output status bytes 00 POR FSI STS SL XPR CD2 CD1 CD0 01 NDF IN1 IN2 IFI AFA X (1) SXA SXB Note 1. X = don t care Jan 26 13

14 8.2.1 INPUT CONTROL BITS Table 7 Forced field frequency Table 3 Source select 1 INA INB DECODER AND TXT 0 0 CVBS INT 0 1 CVBS EXT 1 0 S-VHS 1 1 S-VHS (CVBS EXT ) Table 4 Source select 2 INC IND PIP 0 0 CVBS INT 0 1 CVBS EXT 1 0 S-VHS 1 1 S-VHS (CVBS EXT ) Table 5 Note 1. X = don t care. Phase 1 (ϕ 1 ) time constant FOA FOB MODE 0 0 normal 0 1 slow 1 X (1) fast FORF FORS FIELD FREQUENCY 0 0 auto (60 Hz when line not synchronized) Hz; note Hz; note auto (50 Hz when line not synchronized) Note 1. When the forced mode is selected the divider will only switch to that position when the horizontal oscillator is not synchronized. Table 8 Table 9 Interlace DL 0 interlace 1 de-interlace Standby STB 0 standby 1 normal Table 10 Synchronization mode STATUS MODE Table 6 Crystal indication XA and XB POC MODE XA XB CRYSTAL 0 0 two 3.6 MHz 0 1 one 3.6 MHz (pin 33) 1 0 one 4.4 MHz (pin 34) MHz (pin 33) and 4.4 MHz (pin 34) 0 active 1 not active Table 11 Colour decoder mode CM2 CM1 CM0 DECODER MODE not forced, own intelligence forced NTSC 3.6 MHz forced PAL 4.4 MHz forced SECAM forced NTSC 4.4 MHz forced PAL 3.6 MHz (pin 33) forced PAL 3.6 MHz (pin 34) no function 1996 Jan 26 14

15 Table 12 Vertical divider mode NCIN VERTICAL DIVIDER MODE 0 normal operation 1 switched to search window Table 13 Video identification mode VID VIDEO IDENTIFICATION MODE 0 ϕ 1 loop switched on and off 1 not active Table 14 Long blanking mode LBM BLANKING MODE 0 adapted to standard (50 or 60 Hz) 1 fixed in accordance with 50 Hz standard Table 15 EHT tracking mode HCO TRACKING MODE 0 EHT tracking only on vertical 1 EHT tracking on vertical and E-W Table 16 Enable vertical guard (RGB blanking) Table 20 Condition Y/C input CVS Y-INPUT MODE 0 switched to Y/C mode 1 switched to CVBS mode Table 21 PAL/NTSC matrix MAT MATRIX 0 adapted to standard 1 PAL Table 22 Y-delay adjustment; note 1 YD0 to YD3 Y-DELAY YD3 YD3 160 ns + YD2 YD2 80 ns + YD1 YD1 40 ns + YD0 YD0 40 ns Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. This is only valid for a CVBS signal without group delay distortions. EVG VERTICAL GUARD MODE 0 not active 1 active Table 17 Service blanking Table 23 RGB blanking RBL 0 not active 1 active RGB BLANKING SBL SERVICE BLANKING MODE 0 off 1 on Table 18 Overvoltage input mode PRD OVERVOLTAGE MODE 0 detection mode 1 protection mode Table 19 Vertical deflection mode (TDA8376 only) EXP CL VERTICAL DEFLECTION MODE 0 0 normal 0 1 compress 1 0 expand 1 1 expand and lift Table 24 Noise coring (peaking) COR NOISE CORING 0 off 1 on Table 25 Enable fast blanking RGB1 IE1 FAST BLANKING 0 not active 1 active Table 26 Enable fast blanking RGB2 IE2 FAST BLANKING 0 not active 1 active 1996 Jan 26 15

16 8.2.2 OUTPUT CONTROL BITS Table 33 Output vertical guard Table 27 Power-on reset POR 0 normal 1 power-down MODE NDF VERTICAL OUTPUT STAGE 0 OK 1 failure Table 34 Indication RGB1 insertion Table 28 Field frequency indication FSI FREQUENCY 0 50 Hz 1 60 Hz IN1 RGB INSERTION 0 no (pin 26 LOW) 1 yes (pin 26 HIGH) Table 35 Indication RGB2 insertion Table 29 S-VHS status STS 0 no signal 1 signal S-VHS INPUT IN2 RGB INSERTION 0 no (pin 14 LOW) 1 yes (pin 14 HIGH) Table 36 Output video identification Table 30 Phase 1 (ϕ 1 ) lock indication SL INDICATION 0 not locked 1 locked Table 31 X-ray protection XPR OVERVOLTAGE 0 no overvoltage detected 1 overvoltage detected Table 32 Colour decoder mode CD2 CD1 CD0 STANDARD no colour standard identified NTSC 3.6 MHz PAL 4.4 MHz SECAM NTSC 4.4 MHz PAL 3.6 MHz (pin 33) PAL 3.6 MHz (pin 34) spare IFI VIDEO SIGNAL 0 no video signal identified 1 video signal identified Table 37 IC version indication AFA IC 0 TDA TDA8376A Table 38 Crystal indication SXA and SXB SXA SXB CRYSTAL 0 0 two 3.6 MHz 0 1 one 3.6 MHz 1 0 one 4.4 MHz and 4.4 MHz 1996 Jan 26 16

17 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V P supply voltage 9.0 V T stg storage temperature C T amb operating ambient temperature 0 70 C T sol soldering temperature for 5 s 260 C T j operating junction temperature 150 C V es electrostatic handling all pins; notes 1 and V all pins; notes 1 and V Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 kω; C = 100 pf. 3. Machine Model (MM): R = 0 Ω; C = 200 pf. 10 THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT R th j-a thermal resistance from junction to ambient in free air SDIP52 40 K/W QFP64 50 K/W 11 QUALITY SPECIFICATION In accordance with SNW-FQ-611E. The number of the quality specification can be found in the Quality Reference Handbook. The handbook can be ordered using the code Latch-up At T amb =70 C all pins meet the following specification. I trigger 100 ma or 1.5V DD(max) I trigger 100 ma or 0.5V DD(max) Jan 26 17

18 12 CHARACTERISTICS V P =8V; T amb =25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies MAIN SUPPLY (PIN 8) V P1 supply voltage V I P1 supply current 75 ma P tot total power dissipation 650 W HORIZONTAL OSCILLATOR SUPPLY (PIN 37) V P2 supply voltage V I P2 supply current 6 ma CVBS and S-VHS input switch INTERNAL AND EXTERNAL CVBS INPUTS (PINS 9 AND 13) V 9(p-p) CVBS input voltage note V (peak-to-peak value) I 9 CVBS input current 4 µa SS CVBS suppression of non-selected CVBS input signal notes 2 and 3 50 db S-VHS INPUT (PINS 6 AND 7) V 7(p-p) luminance input voltage V (peak-to-peak value) I 7(p-p) luminance input current 4 µa V 6(p-p) chrominance input voltage (burst amplitude) (peak-to-peak value) note V Z i chrominance input impedance 50 kω TXT AND PIP OUTPUT SIGNALS (PINS 38 AND 11) V o(p-p) output signal voltage amplitude 1.0 V (peak-to-peak value) Z o output impedance 250 Ω V TS top sync voltage level tbf V 1996 Jan 26 18

19 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RGB inputs, colour difference inputs, luminance inputs and outputs RGB INPUTS (PINS 15 TO 17 AND 23 TO 25); note 5 V i(p-p) input signal voltage amplitude for an output signal of 2 V (black-to-white) at nominal controls (peak-to-peak value) V i(p-p) V o input signal voltage amplitude before clipping occurs (peak-to-peak value) difference between black level of internal and external signals at the outputs note V note V 20 mv I i input currents no clamping; note µa t d delay difference for the three channels note ns FAST BLANKING (PINS 14 AND 26) V i input voltage no data insertion 0.4 V data insertion 0.9 V V 14,26(max) maximum input pulse data insertion 3.0 V t d delay time from RGB input to data insertion; note ns RGB output t d delay difference between data insertion to RGB output and RGB input to RGB output data insertion; note 5 50 ns I 14,26 input current 0.2 ma SS int suppression of internal RGB signals notes 1 and 2; data 55 db insertion; f i = 0 to 5 MHz SS ext suppression of external RGB signals notes 1 and 2; no data 55 db insertion; f i = 0 to 5 MHz V 14 input voltage to insert black level at the RGB outputs to facilitate OSD signals being applied to the outputs 4 V COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32) V 32(p-p) input signal amplitude (R Y) note V (peak-to-peak value) V 31(p-p) input signal amplitude (B Y) note V (peak-to-peak value) I 31,32 input current for both inputs note µa 1996 Jan 26 19

20 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28) V 28(p-p) output signal voltage amplitude top sync to white V (peak-to-peak value) V TS top sync voltage level 2.5 V Z o output impedance 250 Ω V 27(p-p) input signal voltage amplitude 0.45 V (peak-to-peak value) I clamp clamping current during burst key 200 µa pulse I i input current no clamping 0.5 µa Chrominance filters CHROMINANCE TRAP CIRCUIT f trap trap frequency f osc MHz during SECAM reception 4.2 MHz QF trap quality factor note 8 2 SR colour subcarrier rejection 20 db CHROMINANCE BAND-PASS CIRCUIT f c centre frequency f osc MHz QBP band-pass quality factor 3 Delay line, peaking circuit and black stretcher Y DELAY LINE t d delay time note ns t d1 tuning range delay time 8 steps ns B bandwidth of internal delay line note 2 5 MHz PEAKING CONTROL; note 9 f c(p) peaking centre frequency 3 MHz t W width of preshoot or overshoot at 50% of pulse; note ns OS overshoot positive 20 % negative 36 % peaking control curve 16 steps see Fig.5 G W wave gain negative half wave gain positive half wave gain CORING STAGE S coring range 15 IRE BLACK LEVEL STRETCHER (PIN 2); note 10 BLS max maximum black level shift IRE LSH level shift 100% of peak-white IRE 50% of peak-white 1 +3 IRE 15% of peak-white IRE 1996 Jan 26 20

21 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Horizontal synchronization circuits SYNC VIDEO INPUTS (PINS 7, 9 AND 13) V 7,9,13 sync pulse voltage amplitude note mv SL HS slicing level for horizontal sync note % SL VS slicing level for vertical sync 30 % HORIZONTAL OSCILLATOR f fr free running frequency Hz f fr spread of free running frequency ±2 % f/ V P frequency variation with respect to V P =8V±10%; note % the supply voltage f (max) maximum frequency variation with temperature T amb = 0 to 70 C; note 2 80 Hz FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 44); note 12 f HR frequency holding range PLL ±0.9 ±1.2 khz f CR frequency catching range PLL note 2 ±0.6 ±0.9 khz S/N signal-to-noise ratio of the video input signal at which the time constant is switched 20 db HYS hysteresis at the switching point 1 db SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 43) ϕ i / ϕ o control sensitivity 150 µs/µs t cr control range from start of horizontal output to flyback at nominal shift position µs t shift horizontal shift range 63 steps ±2 µs ϕ dync control sensitivity for dynamic 5.3 µs/v compensation V 43 voltage to switch on the flash note 13 6 V protection I 43 input current during protection 1 ma HORIZONTAL OUTPUT (PIN 40); note 14 V OL LOW level output voltage I OL =10mA 0.3 V I O(max) maximum allowed output current 10 ma V O(max) maximum allowed output voltage V P V δ duty factor note 2 50 % note 2; V HOUT = high; 75 % during switch-on/switch-off f switch frequency during switch-on and 2f HOUT Hz switch-off t switch(on) switch-on time 50 ms t switch(off) switch-off time RGB drive maximum 100 ms RGB drive minimum 50 ms 1996 Jan 26 21

22 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT FLYBACK PULSE INPUT (PIN 41) V HSW switching voltage level for horizontal 0.4 V blanking V ϕ2(sw) switching level for phase-2 loop 4.0 V V 41(max) maximum input voltage note V Z i input impedance note 7 10 MΩ SANDCASTLE PULSE OUTPUT (PIN 39) V 39 output voltage during burst key V during blanking V t W pulse width burst key pulse µs vertical blanking (50 Hz) 25 lines vertical blanking (60 Hz) 21 lines V clamp clamping voltage level for vertical 2.7 V guard detection I 39(min) minimum input current to activate 0.5 ma guard detection I 39(max) maximum allowable input current 2.5 ma t d delay of start of burst key to start of sync 5.4 µs Vertical synchronization and geometry correction VERTICAL OSCILLATOR; note 15 f fr free running frequency 50/60 Hz f lock locking frequency range Hz divider value not locked 625/525 lines LR locking range lines/ frame VERTICAL RAMP GENERATOR (PIN 50) V 50(p-p) sawtooth voltage amplitude (peak-to-peak value) VS = 1FH; C = 100 nf; R = 39 kω 3.5 V I dis discharge current 1 ma I charge charge current set by external note µa resistor VS vertical slope control range 63 steps % I 50 charge current increase f = 60 Hz 20 % V 50L LOW level voltage of ramp 2.07 V VERTICAL DRIVE OUTPUTS (PINS 47 AND 48) I diff(p-p) differential output current VA = 1FH 0.95 ma (peak-to-peak value) I CM common mode output current 400 µa V o output voltage V 1996 Jan 26 22

23 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 49); note 13 V 49 input voltage V SMR scan modulation range 5 +5 % ϕ vert vertical sensitivity 6.3 %/V ϕ EW E-W sensitivity when switched-on 6.3 %/V I eq E-W equivalent output current µa V 49 overvoltage detection level 3.9 V DE-INTERLACE first field delay 0.5H E-W WIDTH; note 17 CR control range 63 steps TDA % TDA8376A % I eq equivalent output current TDA µa TDA8376A µa V o E-W output voltage range V I o E-W output current range TDA µa TDA8376A µa E-W PARABOLA/WIDTH CR control range 63 steps 0 22 % I eq equivalent output current E-W = 3FH; CP = 00H µa E-W CORNER/PARABOLA CR control range 63 steps 43 0 % I eq equivalent output current PW = 3FH; E-W = 3FH µa E-W TRAPEZIUM CR control range 63 steps 5 +5 % I eq equivalent output current µa VERTICAL AMPLITUDE CR control range 63 steps % I eqdiff(p-p) equivalent differential vertical drive output current (peak-to-peak value) SC = 00H µa VERTICAL SHIFT CR control range 63 steps 5 +5 % I eqdiff(p-p) equivalent differential vertical drive output current (peak-to-peak value) µa S-CORRECTION CR control range 63 steps 0 30 % 1996 Jan 26 23

24 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VERTICAL EXPANSION (ZOOM) MODE (TDA8376A ONLY); note 18 Output current variation compared with nominal scan: VEF vertical expansion factor % output current limiting and RGB 1.06 % blanking Colour demodulation part CHROMINANCE AMPLIFIER ACC cr ACC control range note db V variation in amplitude of the output 2 db signals over the ACC range THR on threshold colour killer ON db HYS off hysteresis colour killer OFF strong signal conditions; +3 db S/N 40 db; note 2 noisy input signals; note 2 +1 db REFERENCE PART Phase-locked loop; note 20 f CR frequency catching range ±360 ±600 Hz ϕ phase shift for a ±400 Hz deviation of the oscillator frequency note 2 2 deg Oscillator TC osc f osc temperature coefficient of the oscillator frequency note 2 tbf Hz/K oscillator frequency deviation with respect to the supply note 2; V P =8V±10% tbf Hz R i(min) minimum negative input resistance 1 kω C L(max) maximum load capacitance 15 pf HUE CONTROL HUE cr hue control range 63 steps; see Fig.6 ±35 ±40 deg HUE hue variation for ±10% V P note 2 0 deg HUE/ T hue variation with temperature T amb = 0 to 70 C; note 2 0 deg 1996 Jan 26 24

25 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DEMODULATORS (PINS 29 AND 30) V 30(p-p) (R Y) output voltage amplitude note V (peak-to-peak value) V 29(p-p) (B Y) output voltage amplitude note V (peak-to-peak value) G gain ratio between both demodulators G(B Y) and G(R Y) V spread of voltage amplitude ratio note db PAL/NTSC Z o output impedance (R Y)/ (B Y) note Ω output B bandwidth of demodulators 3 db; notes 7 and khz V 29,30(p-p) residual carrier output f=f osc ; (R Y) output 5 mv (peak-to-peak value) f=f osc ; (B Y) output 5 mv f=2f osc ; (R Y) output 5 mv f=2f osc ; (B Y) output 5 mv V 30(p-p) H/2 ripple at (R Y) output 25 mv (peak-to-peak value) V o / T variation of output voltage amplitude note %/K with temperature V o / V P variation of output voltage amplitude note 2 ±0.1 db with supply voltage ϕ e phase error in the demodulated signals ±5 deg COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT PAL or (SECAM mode with TDA8395); (R Y) and (B Y) not affected (G Y)/(R Y) ratio of demodulated signals 0.51 ±10% (G Y)/(B Y) ratio of demodulated signals 0.19 ±25% NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting) (B Y) (B Y) signal (B Y) (R Y) (R Y) signal 1.39(R Y) 0.07(B Y) (G Y) (G Y) signal 0.46(R Y) 0.15(B Y) 1996 Jan 26 25

26 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 36); note 22 f ref reference frequency 4.43 MHz V 36(p-p) output voltage amplitude V (peak-to-peak value) V o output voltage level PAL/NTSC identified 1.5 V no PAL/NTSC identified; SECAM (by TDA8395) identified 5.0 V I 36 Control part required current to stop PAL/NTSC identification circuit during SECAM 150 µa SATURATION CONTROL; note 6 SAT CR saturation control range 63 steps; see Fig.7 52 db CONTRAST CONTROL; note 6 CON CR contrast control range 63 steps 20 db tracking between the three channels over a control range of 10 db see Fig db BRIGHTNESS CONTROL BRI CR brightness control range 63 steps; see Fig.9 ±0.7 V RGB OUTPUT SIGNALS (PINS 19, 20 AND 21) V 19,20,21(p-p) V BWmax(p-p) V RED(p-p) output voltage amplitude (peak-to-peak value) maximum voltage amplitude (black-to-white) output voltage amplitude for the red channel (peak-to-peak value) at nominal luminance input signal, nominal contrast and white-point adjustment; note 6 at maximum white point setting tbf 2.0 tbf V 3.0 V note V at maximum white point 3.6 V setting at nominal settings for contrast and saturation control and no luminance signal to the input (R Y, PAL) tbf 2.1 tbf V V blank blanking level at the RGB outputs V I bias internal bias current of NPN emitter 1.5 ma follower output transistor I o available output current 5 ma Z o output impedance 150 Ω CR bl control range of the black-current stabilization nominal brightness and white-point adjustment (with respect to the measuring pulse); V blk = 2.5 V ±1 V 1996 Jan 26 26

27 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V bl black level shift with picture content note 2 20 mv V o output voltage of the 4-L pulse after 4.2 V switch-on bl/ T variation of black level with note mv/k temperature bl relative variation in black level between the three channels during variations of note 2 S/N V res(p-p) supply voltage (±10%) nominal controls tbf mv saturation (50 db) nominal contrast tbf mv contrast (20 db) nominal saturation tbf mv brightness (±0.5 V) nominal controls tbf mv temperature (range 40 C) tbf mv signal-to-noise ratio of the output RGB input; note db signals CVBS input; note db residual voltage at the RGB outputs at f osc 15 mv (peak-to-peak value) at 2f osc plus higher 15 mv harmonics in RGB outputs B bandwidth of output signals RGB input; at 3 db 8 MHz CVBS input; at 3 db; 2.8 MHz f osc = 3.58 MHz CVBS input; at 3 db; 3.5 MHz f osc = 4.43 MHz S-VHS input; at 3 db 5 MHz WHITE-POINT ADJUSTMENT I 2 C-bus setting for nominal gain HEX code 20H G inc(max) maximum increase of the gain HEX code 3FH % G dec(max) maximum decrease of the gain HEX code 00H % BLACK-CURRENT STABILIZATION (PIN 18); note 25 I bias bias current for the picture tube nominal white point setting 10 µa cathode I leak acceptable leakage current 100 µa I scan(max) maximum current during scan 0.3 ma 1996 Jan 26 27

28 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT BEAM CURRENT LIMITING (PIN 22); note 23 V CR contrast reduction starting voltage 3.5 V V diffcr voltage difference for full contrast 2.0 V reduction V BR brightness reduction starting voltage 2.5 V V diffbr voltage difference for full brightness 1.0 V reduction V bias internal bias voltage 4.5 V I ch(int) internal charge current 25 µa I disch discharge current due to peak-white limiting 200 µa Notes 1. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. This parameter is measured at nominal settings of the various controls. 4. Indicated is a signal for a colour bar with 75% saturation (chrominance : burst ratio = 2.2 : 1). 5. The RGB1 inputs (pins 14 to 17) have priority over the RGB2 inputs (pins 23 to 25). 6. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum 10 db. In the nominal brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses. 7. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 8. The 3 db bandwidth of the circuit can be calculated by means of the following equation: 1 = f osc Q f 3dB 9. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 10. For video signals with a black level which deviates from the back-porch blanking level the signal is stretched to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.10). The black level is detected by the capacitor connected to pin 2. The black level stretcher can be made inoperative by connecting pin 2 to the positive supply line. The values given are valid only when the luminance input signal (pins 7, 9 and 13) has a value of 1 V (p-p). 11. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch) Jan 26 28

29 12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I 2 C-bus. Therefore the circuit contains a noise detector and the time constant is switched to slow when too much noise is present in the signal. In the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatically or overruled by the I 2 C-bus. The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be defeated via the I 2 C-bus. To prevent that the horizontal synchronization being disturbed by anti-copy guard signals like Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 µs, the phase position around the sync pulse is asymmetrical. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various conditions are shown in Table The ICs have two protection inputs. The protection on pin 43 is intended to be used as flash protection. When this protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow start procedure. The protection on pin 49 is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive can be switched-off (via the slow stop procedure). It is also possible to continue the horizontal drive and to set the protection bit (XPR) in the output bytes of the I 2 C-bus. The choice between the two modes of operation is made via the PRD bit. 14. During switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (V HOUT = high). After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double value and the RGB drive is set to maximum so that the EHT capacitor is discharged. After approximately 100 ms the RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off. 15. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation: a) Search mode large window. This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode narrow window. This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz). When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider requires some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress Jan 26 29

30 16. Conditions: frequency is 50 Hz; normal mode; VS = 1FH. 17. The E-W output current range of the TDA8376A is higher than that of the TDA8376 because of the horizontal zoom function of the TDA8376A. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µa variation in E-W output current is equivalent to 20% variation in picture width. 18. The TDA8376A has a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 75 to 138% of the nominal scan. At an amplitude of 106% of the nominal scan the output current is limited and the blanking of he RGB outputs is activated. This is illustrated in Fig.21. In addition to the variation of the vertical amplitude the vertical slope control range is also increased. This allows variation of the position of the bottom part of the picture independent of the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical zoom DAC. 19. At a chrominance input voltage of 660 mv (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mv (p-p)] the dynamic range of the ACC is +6 and 20 db. 20. All frequency variations are referenced to a 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series with a series capacitance of 18 pf. The oscillator circuit is rather insensitive to the spurious responses of the crystal. Provided the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal parameters for the crystals are: a) load resonance frequency f 0 (C L = 20 pf) = or MHz b) motional capacitance C M = 20.6 ff (4.43 MHz crystal) or 14.7 ff (3.58 MHz crystal) c) parallel capacitance C 0 = 5 pf for both crystals. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures given in are therefore valid for the specified crystal series. In this, tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: C M Detuning range: C C L The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. The actual series capacitance in the application should be C L = 18 pf to account for parasitic capacitances on and off chip. For 3-normal applications with two crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pf. 21. The (R Y) and (B Y) signals are demodulated with a phase difference of the reference carrier of 90 and a gain ( B Y) ratio. The matrixing to the required signals is achieved in the control part. ( = R Y) The subcarrier output signal can be supplied to the TDA8395 but it can also be used as drive signal for external comb filters. For this reason the signal is continuously available at the output. Only when SECAM has been identified the subcarrier signal is available only during the vertical retrace time. This is to avoid cross-talk between the SECAM input signal and the subcarrier signal. An external DC load on this pin is not allowed because this current will disturb the reliability of the communication between the TDA8376/TDA8376A and the TDA At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input. 24. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 25. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a result the black-current of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment Jan 26 30