Scalable Readout System

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1 Scalable Readout System 2018 system hardware 6/19/2018 1

SRS system components a typical small system Frontend Concentrator (FEC) Frontend Adapter (ADC, DVM) Detector GEM / MicroMega / Frontend links (HDMI, CAT6.

2 SRS system components a typical small system Frontend Concentrator (FEC) Frontend Adapter (ADC, DVM) Detector GEM / MicroMega / Frontend links (HDMI, CAT6..) Frontend hybrids APV / VMM / Crates Mini, Euro DAQ Online/Offline/Controls Mesh trigger pickup, HV APIC Backend links CAT6 up 10Gb, optical up 100 Gb Readout Unit DTCC link, CTF, SRU, network switch 6/19/2018 Hans.Muller@cern.ch 2

SRS from APV to VMM APV VMM Analogue 128 channels with single chip Embargo list countries 1/2 W per hybrid Cooling negligible No

peaking time 50-80 ns Noise ca 2000 e- @ C det ~ 50 pf Max. C det ~ 50 pf fixed CSA gain -> limited dyn.

Zero suppression Trigger rates up O(1 MHz /channel) timing resolution O(1ns) clustering logic 8 different preamp gains 0.

3 SRS from APV to VMM APV VMM Analogue 128 channels with single chip Embargo list countries 1/2 W per hybrid Cooling negligible No zero supression Max trigger rate O(5kHz / hybrid) Timing resolution O(5 ns) No clustering logic fixed preamp gain 65mV/fC fixed peaking time ns Noise ca 2000 C det ~ 50 pf Max. C det ~ 50 pf fixed CSA gain -> limited dyn. Range non-linearity over full dyn range Digital 128 channels with 2 chips No embargo 3W for 128 channel hybrid Cooling important Zero suppression Trigger rates up O(1 MHz /channel) timing resolution O(1ns) clustering logic 8 different preamp gains mV/fC 4 different peaking times ns Noise ca 1200 C det ~ 50pF Max. C det ~ 1nF large dynamic range linear over full dyn. range 6/19/2018 Hans.Muller@cern.ch 3

4 new HRS connector Production of 24 pilot hybrids VMM3a imminent -VMM3a available for prototypes -new PCB s expected this week -Component mounting scheduled -Wire bonding following -glob-tobbing following 6/19/2018 Hans.Muller@cern.ch 4

5 Adapters for the connector transition Panasonic (130 pin obsolete) > HRS(140 pin new ) Panasonic HRS HRS Panasonic tbd whether flex or rigid PCB 5 March 2018 Hans.Muller@cern.ch 5

1A P1 GND P2 IPL-103-01-L-RA-K mount only for auxiliary power.

6 auxiliary power connector Auxiliary VMM power connector P2 = 1.8V -> IC5,6,7,9 ->1.2V 2x VMM: 1.8A GND =middle pin P1 = 3.3V ->IC8 -> 2.5V FPGA/Flash: 0.1A P1 GND P2 IPL L-RA-K mount only for auxiliary power. Matches with cable connector IPD1-03-S-K (with latch) J2 The Power AUX connector is required for test purposes or when voltage dropoff over HDMI cables is an issue. 5 March 2018 Hans.Muller@cern.ch 6

via control bit smx = 1 Oscilloscope with 1M termination analogue MO

7 access to analogue VMM signals M0 PD0 TDO Monitoring output Peak detector output Time detector output on MO: analogue output selected via control bit smx = 1 Oscilloscope with 1M termination analogue MO signal output for different pulser amplitudes 5 March 2018 Hans.Muller@cern.ch 7

analogue readout via I2C ADCs Access pins PDO, PTO, MO PDO,PTO,MO signals also accessible via 3 testpins, one for each VMM3 chip The analogue channels ( PTO,PDO, MO) of each VMM chip can be read out

8 analogue readout via I2C ADCs Access pins PDO, PTO, MO PDO,PTO,MO signals also accessible via 3 testpins, one for each VMM3 chip The analogue channels ( PTO,PDO, MO) of each VMM chip can be read out via two micropower 12 bit ADCs on the VMM3a Hybrids. These ADC s allow to monitor -pulser DAC (after multiplexer) -threshold DAC -band-gap reference -VMM temperature sensor -analogue pulse signal ch analogue time ramp signals ch PDO,PTO, MO testpins VMM U2 ( ch. 0-64) I2C ADC s on VMM3a hybrid 5 March 2018 Hans.Muller@cern.ch PDO,PTO, MO testpins 8 VMM U3 ( ch )

9 Test charge using integrated test pulser DV test pulser DAC DV amplitude DQ T = C T 1+ C T C in C f = (charge-gain) -1 A ~ 10 4 (estimated) C in ~O( ) pf DV ~ C T [ 1- C T C in ] DV C det C c 1M C T DQ T -A C f shaper C in ~A*C f U= DQ T / C f VMM 1 channel measured on VMM3: DV[mV] = * DAC + 55[mV] C T C in << 1 MO analogue shaper output U peak ~ DQ T DQ T ~ C T *DV Example: For DAC = 0x190: DV = 284 mv C T1 =0.3pF : DQ T = 85 fc C T2 =3 pf: DQ T = 850 fc 5 March 2018 Hans.Muller@cern.ch 9

clustering and channel direction Self-triggered if channel peak is above discriminator. Clustering mode: enable neighboring channel for readout.

10 clustering and channel direction Self-triggered if channel peak is above discriminator. Clustering mode: enable neighboring channel for readout. Works also between adjacent VMM hybrids connected via the SETTA and SETTB connectors. The direction of channels is shown. J3 J2 Note: The channel counting on VMM hybrids is inversed with respect to APV hybrids 5 March 2018 Hans.Muller@cern.ch 10

11 Master / Slave HDMI links J2 = double BW Slave J3 = DIRECT mode Master OR double bandwidth mode master cable to J3 slave cable to J2 J2 J3 5 March 2018 Hans.Muller@cern.ch 11

12 Frontend links: HDMI cables A-D(micro)* VMM hybrid to DVMcard or Powerbox A! pin assignments different on D side! A D Twisted pair lines: 4 x shielded, 3Gbps twisted pairs Data-1M (1,3) uplink, Data-2 MS (4,6) uplink Controls (7,9) downlink, CLK (10,12) downlink 1 x shielded twisted pair (14,19) (Ethernet HDMI 1.4) = power P2 1 x pair ( I2C) (15 SCL downlink -16 SDA bidir) Single lines: 1 x M/S (13 sense bidir ) 1 x power (18 = P1) 6 x GND 2,5,8,11,17,shell *max. 5m, like CERN SCEM March 2018 Hans.Muller@cern.ch 12

DVM card FEC V6 adapter for VMM hybrids with autoswitch for Direct or Master/Slave mode DIRECT mode: 5 m cable to 8 VMM hybrids J3 (max 1k ch) M/S mode: requires powerbox, long cables, 16 VMM hybrids

13 DVM card FEC V6 adapter for VMM hybrids with autoswitch for Direct or Master/Slave mode DIRECT mode: 5 m cable to 8 VMM hybrids J3 (max 1k ch) M/S mode: requires powerbox, long cables, 16 VMM hybrids J2 and J3 (2k ch) LED indicator Direct / Powerbox 8 x HDMI link ports Pushbutton VMM Power reset RJ45 for CAT6 cable (common clock and I2C) to Powerbox DCDC converters SATA power cable from ATX (only required for Direct mode) From ATX +12V 4A (+5V) +3V3 1.5A Autoswitch relays: Direct <-> M/S LED 1 on PCB = 3V3 SATA OK LED 3 on PCB = 12 V SATA OK 5 March 2018 Hans.Muller@cern.ch 13

prototype 2017 2018: revised version with M/S auto-selection coming

14 DVMcard for SRS digital frontends ( VMM etc ) DCDC converters SATA power ( 30W for 8 hybrids) from ATX power supply Photo DCARD prototype : revised version with M/S auto-selection coming very soon 8 x HDMI ports 11/9/2017 Hans.Muller@cern.ch for GDD lab CERN 14

15 Initial small systems ( max. 2k ch with 2 FECs in a Minicrate ) DIRECT frontend links 5m to DVMcards (no powerbox) (max. 8 VMMs per max. 5 m ) 1 GbEthernet (Single FEC) 2x RG45 DTCC 800Mbps SFP+ SFP+ Trig IN NIM Single EFC NIM Out SRU, CTF for multiple FECs) SRS Mini-crate DDR3 Virtex6 FEC ATX -SATA FEC HDMI ports DCDC 30W Auto-switch = DIRECT RJ45 Not used DVM up to 8 x HDMI 1.4 cables A-D max 5m M/S =1on all lines VMM-M VMM-M VMM-M VMM-M VMM-M VMM-M VMM-M VMM-M all cables connected to J3 all hybrids in Master mode M 15 5 March 2018 Hans.Muller@cern.ch

16 2019: scaling up (>2k ch, >5m) Powerbox - Master/Slave 8-FEC/Eurocate SRU* * BW upgrade of SRU needed for more than 10 GBps 5 March 2018 Hans.Muller@cern.ch 16

mounted box - 3 ports 5Gbps, 1 port 10 GBE 24 ports DTCC

17 Large SRS systems ( rack environment with SRU) Eurocrate with FEC cards DTCC links ( CAT6 cables) SRU in 1 U rack mounted box - 3 ports 5Gbps, 1 port 10 GBE 24 ports DTCC links FPGA LX240 Virtex6 6/19/2018 Hans.Muller@cern.ch 17

18 Scaling beyond 10 Gbit Points for a very high BW SRU upgrade Project - Replace FPGAs ( like in SRU) by SoC multi-processors ( D.Pfeiffer et al ) - easier to program in C than in Verilog - chip-integrated with multiple10 Git link protocols - Insert large data buffers in Readout ( DDR3 etc) ( see talk Yan Huang ) - equilibrate trigger statistics ->smooth uplink - allow for L2 triggering to reduce uplink BW - Commercial SRU-like cards in utca crates with high BW backplanes (tbd) - buy hardware & put effort into software - Mux Optical FEC links ( 5-10 GBps) to utca crate(s) (tbd) - use streaming concepts like adoped by LHC experiment for Gbit data uplinks 6/19/2018 Hans.Muller@cern.ch 18

FEC V6 FEC V6* Working Horse SRS frontend concentrator * designed 2013 by J.

network support - 2 x SFP + ports, 5 Gbit each, J11 defaults to 1 GBE/UDP link - NIM I/O

for SRS adapter cards - plugin-ddr3 memory 2 Gbyte - reconfigurable firmware (JTAG) via

19 FEC V6 FEC V6* Working Horse SRS frontend concentrator * designed 2013 by J.Toledo, UPV Valencia Photo DDR3 memory plugin FEC V6 bottom side - Virtex 6 FPGA with network support - 2 x SFP + ports, 5 Gbit each, J11 defaults to 1 GBE/UDP link - NIM I/O and 2x RJ45 for DTCC links - User I/O plug above SRS powerbus plug - 3 x PCIe connectors for SRS adapter cards - plugin-ddr3 memory 2 Gbyte - reconfigurable firmware (JTAG) via SPI Flash New Firmware by Yan Huang: enable DDR3 event-buffer for VMM data 6/19/2018 Hans.Muller@cern.ch 19

20 New SRS crates Eurocrate V1: 4 FEC + 1 CTF Eurocrate V2: 8 FEC + 1 CTF Minicrates AB => Minicrates ABC C = 3 rd slot for CTF 6/19/2018 Hans.Muller@cern.ch 20

New 160W ATX adapter for SRS -> for new Euro- and Mini-crates New DC-DC generator for -5V@15W New resettable PCT fuses ATX 20W ballast resistor New New 8 x LED On-off reset switch On-off remote

21 New 160W ATX adapter for SRS -> for new Euro- and Mini-crates New DC-DC generator for New resettable PCT fuses ATX 20W ballast resistor New New 8 x LED On-off reset switch On-off remote connector 24 pin connector for 450W ATX power supply New New low-profile connection Faston 15A power cable connectors for 8 SRS Voltages as required by FEC, SRU etc 1V8-10A (orange LED) 3V3-10A (orange LED) 4V2-10A (red LED) +5V -10A ( red LED) +5V standby - 0.3A (green LED) +12V0-0.5A (blue LED) -12V0-0.3A (blue LED) -5V0-5A (yellow LED) 6/19/2018 Hans.Muller@cern.ch 21

new ATX adapter V2 Eurocrate Important: you must place a ventilator unit below Photo

22 New SRS V2 Eurocrate ( 8 FECs up 16 k channels ) V1 : 4 FEC + 1 CTF slot: 1 x 450 W power supply 1 x new ATX adapter V2 : 8 FEC + 1 CTF slot: 2 x 450 W power supply 2 x new ATX adapter V2 Eurocrate Important: you must place a ventilator unit below Photo V2 Eurocrate proto 2018 for ALICE Focal 11/9/2017 Hans.Muller@cern.ch for GDD lab CERN 22

23 New Minicrate ABC A,B slots for 2 FECs ( max 4k channels) C slot and power for CTF ( common clock and trigger) Remote Power on/off (coax cable ) Power panel (banana plugs for +12V,+5V,+3V3 ) 6/19/2018 Hans.Muller@cern.ch 23

24 CTF card common clock and trigger for up 8 FECs ( see RD51 Miniweek Dec WG5, Givi Sekhniaize ) CTF card is required for SRS systems with > 1 FEC - common clock and trigger - same cable / pinout as SRU - Eurocrate slot 9 reserved for CTF - New Minicrate ABC slot C reserved for CTF - External NIM or internal auto-trigger - External LVDS clock ( LHC) or internal 40 MHz New CTF V6 cards successfully tested ready for production 6/19/2018 Hans.Muller@cern.ch 24

APIC pickup amplifier-shaper-trigger NIM-IN-a-BOX see Miniweek Febr. 2018 WG5 H.Muller User manual APIC V4.1: https://indico.cern.

25 APIC pickup amplifier-shaper-trigger NIM-IN-a-BOX see Miniweek Febr WG5 H.Muller User manual APIC V4.1: /APIC_V4.1_Manual_HM pdf APIC summary features CSA preamplifier preset to: 1mV/fC ( 0.5-2mV/fC via trimmer) CSA output: 2 ns max risetime, 50 OHM, +/- 3pC => +/- 3V, 1us fall-time Pole-Zero: asymptotic return to zero ( trimmer for externally connected CSA) Fast shaper default: tp =30ns, 50 OHM max 1V, 1M max 2V, pos. or neg. Slow shaper: tp = 400 ns, 50 OHM max 1V, 1M max 2V, pos. or neg. Shaper gain: relative to CSA output Test pulse external: NIM 50 OHM, LVTTL@ 50 OHM, 1kHz- 100kHz Test pulse internal: 187 fc pos an neg, tf=202ps, tr=608 ps Baseline +/- 150mV Trigger TOT/TBT: on slope of CSA, pos or neg, complementary 50 OHM NIM, 50 ns External Trigger Input=> 3 functions: 1 direct out, 2 gated with TOT, 3 gated with TBT Pulse stretcher on NIM trigger out 50 OHM NIM, ns Trigger Buzzer: from NIM trigger out Battery max 31Wh storage, good for h autonomous operation (depending on enabled units) 6/19/2018 Hans.Muller@cern.ch 25

26 Summary VMM frontend: 2 nd life for SRS applications Major SRS hardware upgrades & developments done: Hybrids, Connectors, FEC- Adapters, Crates, CTF, Powerbox, APIC (HV and Trigger) Pending for larger systems: upgrade of SRU backend Need developers and users for pilot systems 6/19/2018 Hans.Muller@cern.ch 26

27 VMM frontend: A 2 nd life for SRS applications Major SRS hardware upgrades & developments Hybrids, Connectors, FEC- Adapters, Crates, CTF, Powerbox, APIC (HV and Trigger) Manpower & resources needed for Firmware & Software Larger systems: upgrade of SRU backend High rate systems: DDR buffering Main issue: developers and users for pilot systems 6/19/2018 Hans.Muller@cern.ch 27

28 Auxiliary slides 6/19/

may even be responsible for defecting bond connections New globtop adhesive better adapted for large-surface

29 VMM globtop revision VMM ASICs on SRS hybrids are wire-bonded globtop Epoxy adhesives are used to protect the ASIC and to provide thermal flux for cooling globtop on our VMM protoypes ( photo) appears to have side-effects, may even be responsible for defecting bond connections New globtop adhesive better adapted for large-surface ASICs and high thermal coefficient just arrived and will be tested on next VMM3 hybrids 6/19/2018 Hans.Muller@cern.ch 29

alternative to already existing +HV bias ( 10-100V) for Si Diodes External preamplifiers (powered by

30 APIC V4.x new plugins being worked on HV plugin for MicroMegas: generate +HV and -HV relative to GND as alternative to already existing +HV bias ( V) for Si Diodes External preamplifiers (powered by APIC) low-noise preamps for high-c det Diodes fast preamplifiers for psec applications Peakfinder (powered by APIC): digitization of fast shaper peaks voltages by slow ADCs (Arduino etc) 6/19/2018 Hans.Muller@cern.ch 30

FRONT-END AND READ-OUT ELECTRONICS FOR THE NUMEN FPD

FRONT-END AND READ-OUT ELECTRONICS FOR THE NUMEN FPD D. LO PRESTI D. BONANNO, F. LONGHITANO, D. BONGIOVANNI, S. REITO INFN- SEZIONE DI CATANIA D. Lo Presti, NUMEN2015 LNS, 1-2 December 2015 1 OVERVIEW