AIDA Advanced European Infrastructures for Detectors at Accelerators. Milestone Report. Pixel gas read-out progress

Transcription

1 AIDA-MS41 AIDA Advanced European Infrastructures for Detectors at Accelerators Milestone Report Pixel gas read-out progress Colas, P. (CEA) et al 11 December 2013 The research leading to these results has received funding from the European Commission under the FP7 Research Infrastructures project AIDA, grant agreement no This work is part of AIDA Work Package 9: Advanced infrastructures for detector R&D. The electronic version of this AIDA Publication is available via the AIDA web site < or on the CERN Document Server at the following URL: < AIDA-MS41

2 Grant Agreement No: AIDA Advanced European Infrastructures for Detectors at Accelerators Seventh Framework Programme, Capacities Specific Programme, Research Infrastructures, Combination of Collaborative Project and Coordination and Support Action MILESTONE REPORT PIXEL GAS READ-OUT PROGRESS MILESTONE: MS41 Document identifier: Due date of milestone: End of Month 23 (December 2012) Report release date: 11/12/2013 Work package: Lead beneficiary: Document status: WP9: Advanced infrastructures for detector R&D UBONN Final Abstract: Subtask (CEA, DESY, FOM): Common readout systems for gaseous detectors. Auxiliary electronics for the read-out of pixelated front-end chips, aimed at highly granular pixel read-out of gaseous detectors. MS40. Deliverable D9.6 (Task 9.2.3) Grant Agreement PUBLIC 1 / 6

3 Copyright notice: Copyright AIDA Consortium, 2013 For more information on AIDA, its partners and contributors please see The Advanced European Infrastructures for Detectors at Accelerators (AIDA) is a project co-funded by the European Commission under FP7 Research Infrastructures, grant agreement no AIDA began in February 2011 and will run for 4 years. The information herein only reflects the views of its authors and not those of the European Commission and no warranty expressed or implied is made with regard to such information or its use. Delivery Slip Name Partner Date Authored by P.Colas, K. Desch, N. Hessey, J. Kaminski, M. Lupberger CEA, FOM, UBONN 13/11/13 Edited by P.Colas, K. Desch, N. Hessey, J. Kaminski, M. Lupberger CEA, FOM, UBONN 29/11/13 Reviewed by L Serin [Scientific coordinator] CNRS 11/12/13 Approved by L Serin [Scientific coordinator] 11/12/13 Grant Agreement PUBLIC 2 / 6

4 TABLE OF CONTENTS 1. INTRODUCTION ACTIVITIES IN BONN ACTIVITIES IN NIKHEF REFERENCES... 6 Grant Agreement PUBLIC 3 / 6

5 1. INTRODUCTION It has been agreed that the pixelated front-end chip mentioned in the subtask description will be the Timepix chip and its possible evolution [1]. It has also been agreed between the participating institutes that FOM (NIKHEF) will develop a readout system for the Timepix 3 chip and UBONN and CEA will design a Timepix readout system. 2. ACTIVITIES IN BONN The goal of the activities in Bonn is to develop a system which can be scaled from a single chip readout to a multi-chip application of up to several hundred chips. This readout will be based on the Scalable Readout System (SRS) [2] developed by the RD51 collaboration at CERN. This system consists of a common part and a part that users have to design for a different front end chip. The SRS is mounted in a Eurocrate with ARX power supply. The common part consists of front end card (FEC), which carries a Virtex 5 PFGA (Virtex 6 in 2013 version). The FPGA code consists of both a common part and a chip specific part which has to be adapted to the chip-specific commands by the user. The FEC is connected by PCI plugs to the user specific part: the adapter board. As a starting point for the FPGA code, a readout system for the Timepix chip developed at the University of Mainz [3] has been used. This system is based on the Xilinx ML506 evaluation board hosting a Virtex 5 FPGA. The system also includes an adapter board with power supply for a single Timepix chip and a C++ DAQ software with basic functionality. A copy of this system was set up at the University of Bonn. The FPGA code was then transferred to a Virtex 6 FPGA on a ML605 evaluation board for further development. The expansion of the FPGA firmware functionality was always accompanied by DAQ software development. The readout speed was enhanced to reach 99% of the theoretical maximum readout speed for the Timepix chip. Zero suppression has been introduced in the FPGA firmware. Readout rates of 53Hz at chip clock frequency of 50 MHz could be reached. The rate is only limited by the time to read the data from the chip ( bit). Data transfer (multi-threading in the FPGA) and handling (multi-threading in the DAQ software) are performed during read out of the next frame. A first version for the SRS adapter board was designed in Bonn. It is passive and transfers the Timepix data and control signals via VHDCI cable to the intermediate board holding the chip carrier board. The FPGA firmware was adapted to the SRS ethernet communication modules and specifications of the FEC. Moreover, the firmware and software was expanded to control and read out octoboards, a matrix of 8 Timepix chips in a daisy chain. First a single chip was operated with the SRS on an octoboard. The other seven chips followed one by one after calibration has been done for the chips on the board. The DAQ software was modified to provide more functionalities such as DAC scans, threshold scans, Grant Agreement PUBLIC 4 / 6

6 threshold equalisation, calibration, fast data acquisition, several ways of readout (not zero suppressed, zero suppressed with and without multi- threading). A test beam is planed with an eight-timepix chip module in April Functionality of the Timepix SRS readout system will be demonstrated. For the future a second version of the adapter board for the FEC is planned. It will come along with a new intermediate board that hosts the chip carriers. The cabling from the FEC to the intermediate board will be changed from VHDCI to HDMI to be able to put the SRS crate outside the radiation area in a possible application. I2C will be used to transfer the control signals to the intermediate board. This board will then host DACs to control a MUX to generate test pulses for calibration. It will also host an ADC to read back DAC voltages, LVDs drivers and I2C electronics. At the moment 2 setups for a read-out of pixelated front-end chips are operated at Bonn: A single-chip Timepix readout based on a Xilinx ML605 evaluation board A single-chip Timepix readout based on the SRS The readout system based on the Xilinx ML605 board will be further developed and will be used at the CAST experiment for a Timepix InGrid detector. The SRS-based system will be further developed and will be used as readout for a 96 Timepix chip module as a demonstrator for a pixelated TPC for a future linear collider. 3. ACTIVITIES IN NIKHEF In 2012, the progress on the development of the read-out system has continued on several tracks. Primarily, work has been done to program the FPGA to control the read-out chip, in our case the Medipix3 chip. We have also chosen to work with a Xilinx Virtex-6 ML605 Evaluation board to fully develop the whole system before designing a compact version. The basic functionality has been implemented and is ready to be tested. The work that was planned to run in parallel on the development of the hardware libraries was delayed unfortunately. This work has to allow the data collected from the chip by the FPGA to be understood by a general user interface, such that we can run scripts to scan all kinds of parameters to test the chip and allow the FPGA code to be tested more thoroughly than can be done with simulations or a limited set of instructions. The extension-board, which will carry four read-out chips was made and tested with the basic functionality to be operational. In the meantime work has been ongoing on the microprocessor that we want to implement inside the FPGA, i.e. the LEON. Currently, we have not yet implemented such an internal microprocessor, because we preferred to be able to have direct control over the chip and not via a black-box. As soon as the currently implemented functionality has been tested, we ll implement the LEON and with this increase the read-out speed and reduce the command set to more encompassing instructions. This will make things easier for the user and less prone to errors. Grant Agreement PUBLIC 5 / 6

7 Below there is a picture of the Xilinx Virtex-6 ML605 Evaluation board with on the top side an extension board that can carry up to four read-out chips, which are read out in parallel. At the time of the redaction of this report, the Timepix3 chip just came back from foundry and the first tests for reading them out with the SPIDR system are being carried out. Figure 1: The SPIDR board with a Medipix3 chipboard mounted as a mezzanine. 4. REFERENCES [1] X. Llopart, R. Ballabriga, M. Campbell, L. Tlustos, and W. Wong. Timepix, a 65k programmable pixel readout chip for arrival time, energy and/or photon counting measurements. Nuclear Instruments and Methods in Physics Research Section A: 581(1-2): , VCI Proceedings of the 11th International Vienna Conference on Instrumentation. [2] S. Martoiu, H. Muller and J. Toledo Front-End Electronics for the Scalable Readout System of RD51, IEEE Nucl. Sci. Symp. Conf. Rec., Valencia, October [3] Entwicklung eines Datenerfassungssystems für die Auslese des TimePix-Chips, Michael Zamrowski, August 2009, Johannes Gutenberg-Universität Mainz. Grant Agreement PUBLIC 6 / 6