«Trends in high speed, low power Analog to Digital converters»

Transcription

1 «Trends in high speed, low power Analog to Digital converters» Laurent Dugoujon Data-Converters Design Mgr. STMicroelectronics

2 Outline Introduction/Generalities ADC challenges ST ADC products Power Optimisation Design views ADC Trends Conclusion

3 Introduction/Generalities DEFINITIONS STMicroelectronics

4 Analog to Digital Converter (ADC) analog input ANALOG INPUT Ex:4 bits A/D converter. t ADC TSA04XX D0 D1 D2 D DIGITAL OUTPUT Full scale amplitude LSB=Full scale/2 N 62mV for 1V/4bits Sampling Clock signal 16 possible output codes output binary codes reconstructed signal t

5 ADC MAIN PARAMETERS ADC functionality parameters: Number of output bits Sampling frequency noted F S Number of channels ADC performance parameters: Static parameters: DNL, INL Dynamic parameters: SNR, SINAD, ENOB, Analog input bandwidth. Power consumption, Area, Package

6 Generalities ADC Market, Applications STMicroelectronics

7 ADC Market Source:WSTS ADC, DAC, SWITCHES & MUX Regions Year 2000 US 42% Europe 22% Japan 18% A/P 16% 1.8B$ total value 646Mu total volume

8 High Energy Physics Electronic chain Detector PA ADC Data Processor DAQ DCS Sensor Signal formating Events acquisition Storage Control Analysis

9 Hi-volumes & Hi-tech Applications Nbr. bits 10 Consumer Audio Industrial Control Consumer Video HEP HEP Detectors requirements Telecom + low Power + no. channels RF/Military Sampling Frequency 10MHz AP Astro-Physics

10 ADC Challenge ACCURACY and SPEED? STMicroelectronics

11 Speed-Accuracy coupling Fundamental relation (Heisenberg): DE. DT m h/2.p Vin DE = (LSB/2) 2 / R DT = T/2 T/2 Applied to A/D Converter: R=50 Ohms, 2 N.LSB = 1Volt, h= N.Fsamp <= ex: 12 bits/840gsamples/s Or 18bits/10Gsamples/s LSB/2 Time

12 Real signals world How many Gigabit/s on a wire? Today commercial 10Gbit/s with ECL levels Power, EMI, Integrity loss, Package parasitics,.. Are the limiting factors against higher rates!

13 Clock accuracy problems Generation of Clock signal: Clock signal is usually the fastest signal of the acquisition system and determines the sampling instants: signal jitter clock

14 Low-jitter Clock generation Clock jitter: It characterizes the Quality of the time reference, often expressed in ps pk-to-pk or rms. Available generator technologies: RC + Logic Xtal, VCXO Sp. Plls Jitter ps ps ps Cost ~0.1$ ~1$ ~10$

15 Clock Quality vs ADC specs Aperture time and Clock jitter for a Nbit ADC sampling an Analog signal of FIN frequency must be less than: 1/(PI x FIN x 2 (N+1) ) In order not to add degradation in the achieved Signal/Noise Ratio. Example: 10 bit conversion of 10MHz input needs less than 16ps jitter. (good quality Xtal oscillator is OK) 12bit of same 10MHz input needs 4ps max jitter!

16 Effect. bits Accuracy/speed 1ps jitter Heisenberg 4 2 Sample 0 rate S/s 10K 100K 1M 10M 100M 1G 10G 100G

17 Sampling rate trend summary Today best system clock jitter is 1ps Corresponding to 12bit resolution of 40MHz input signal Prototypes ADCs reach 0.5ps aperture time (8bit/1.3GHz) Going beyond 12bit-40MHz will require sub-ps jitter clock generator preferably integrated to the ADC chip for noise, power and cost reductions.

18 Resolution Problems Resolution of real conversion systems is limited by the «noise floor» resulting from differents noise sources: thermal noise, transistors intrinsic noise, Input-referred noise can be expressed as: R eq Noiseless <vn 2 > = 4 ktr eq F s /2 Rnoise ADC Vin Equiv. This should be less than Quantization noise that is: Q 2 /12, Q=Full scale/2 N Then : N < Log 2 {Vfs 2 /(6kTR eq Fs)} 1/2 1 Given a 2Volts full scale and 1000ohms Req, it gives 19bit sampling at 100Ksps (or 16bit at 10Msps)

19 Effect. bits Accuracy/speed 1Kohm thermal 1ps jitter Heisenberg 4 2 Sample 0 rate S/s 10K 100K 1M 10M 100M 1G 10G 100G

20 High-speed ADCs ST products & services TSA0801: 8-bit, single-channel, 40Msps, 40mW TSA1001: 10-bit, single-channel, 25Msps, 35mW TSA1002: 10-bit, single-channel, 50Msps, 50mW TSA1201: 12-bit, single-channel, 50Msps, 130mW TSA1203: 12-bit, dual-channel, 40Msps, 230mW TSA1204: 12-bit, dual-channel, 20Msps, 120mW TSA1005: 10-bits, dual Channel, 40 Msps, 200mW 2.5V supply voltage TQFP48 + Evaluation boards, Applications notes, support, IP integration, consulting

21 Effect. bits ST ADCs Accuracy/speed products 1Kohm thermal 1ps jitter Heisenberg 4 prototypes 2 Sample 0 rate S/s 10K 100K 1M 10M 100M 1G 10G 100G

22 Power optimisation MeritFig.=2 ENOB x F s / Power ( x ) ADCs V supply =2.5V TSA b, 25Msps 35mW MF=5.9 TSA b, 50Msps 50mW MF=8.3 TSA b, 50Msps 130mW MF=5.6 TSA1203 (dual) 10.5b, 40Msps 230mW MF=5 TSA b, 40Msps 40mW MF=2.4 Closest competitor MF=1.2 Closest competitor MF=3.2 Closest competitor MF=4.2 Closest competitor MF=4.7 Competitors V supply = 5V or 3.3V Closest competitor MF=2

23 Design architectures Resolution (n) Sigma Delta Audio Dual Slope Sensors Instrumentation Successive Approximation Pipelined Folded High Speed Basestation Instrumentation IF sampling 5 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 Sampling Frequency (Fs) (Hz) Flash Radars, RF

24 MUX 12:1 COMP MUX 12:1 Very High Speed ADC (8bits/2Gsps) Interleaved SAR ADCs 0.18mm CMOS V SA ADC 1 SA ADC IN SA ADC S/H SA ADC 24 8 DAC 24 // unitary SAR ADC Die: 4mm 2, IP: 0.45mm 2

25 Pipelined ADCs 1 pipeline stage Vi-1 S/H x2 Vi 2bit 2bit Digital correction Output bits

26 Folded-cascode Amplifier VDD 2.5V / 0.25mm CMOS inm pol inp vcp op om vcn Vtp=Vtn=0.7V G=90dB THD=-86dB BW 3dB =100MHz GND

27 CERN Alice-TPC ALTRO chip

28 CERN ALTRO chip: Layout and Package 7.7 mm 24mm TQFP mm 3.8 mm 8.3 mm 12 mm Data Memory 1K x 40 Processing Logic Pedestal Memory 1K x 10 Process STM HCMOS-7 (0.25 µ) Area 64 mm 2 Dimensions mm 2 Transistors 6 Million Embedded Memory 800-Kbit No. ADCs 16 Supply Voltage 2.5V Power Consumption 10 MSPS Package TQFP-176

29 ENOB ENOB CERN ALTRO ADC results ENOB vs Sampling Frequency ENG RUN (internal resistor - 90KW) kw 6 MPW (external resistor - 20KW) kw fs (MHz) ENOB vs Signal Frequency ENG RUN (internal resistor - 90KW) kw MPW (external resistor - 20KW) kw fin (MHz) MAX sampling rate in the TPC BW at PASA output TPC requirement: ENOB > 9

30 bits mw ADC Power Consumption Optimised ADC power in ALTRO 12 Power and ENOB ADC Operating Point Effective Number of Bits Power Consumption per Channel mw mw 0 20 kw 90 kw Rpol (kw) MPW values Engineering Run values Measured Analogue Power Consumption: 80 ma (st.dev = 1.12 ma) 12.5 mw / channel

31 dbc dbc CERN ALTRO spectrum analysis 0 Without Readout Clock 0 With Readout Clock HD2 HD3 HD HD2 HD3 RDO clock HD f (MHz) f (MHz)

32 ALTRO chip: Digital Processor Performance INPUT SIGNAL AFTER 1 st BASELINE CORRECTION AFTER TAIL CANCELLATION AFTER 2 nd BASELINE CORRECTION

33 ADC Trends Resolution-Speed Paralelism to exploit technology intrinsic speed of successive generations technology (X2 every 2years) Intensification of integrated Digital Post-processing Number of channels Lower core sizes and power will allow higher integration Associated Functions Internal Clock re-generation will appear, Built-In-Self-Test, Power New low-voltage cells/architectures for 1V technology on the way Packages Parasitics and size reduction associated to better dissipation

34 Conclusions ADCs are used in many applications HEP is not so specific in terms of need Application Environment can degrades ADC perf. High Merit-figure ADC design needs large efforts Multi-ADCs integration is a powerfull path Digital integration is the same natural path We will use Moore s law to buy resolution.speed