FPGA 设计实例 基于 FPGA 的图形液晶显示面板应用. Graphic LCD panel. FPGAs make great video controllers and can easily control graphic LCD panels.

Size: px
Start display at page:

Download "FPGA 设计实例 基于 FPGA 的图形液晶显示面板应用. Graphic LCD panel. FPGAs make great video controllers and can easily control graphic LCD panels."

Transcription

1 FPGA 设计实例 基于 FPGA 的图形液晶显示面板应用 Graphic LCD panel FPGAs make great video controllers and can easily control graphic LCD panels. This project is split in 4 parts: 1. Introduction 2. Video generator 3. Graphics 4. Text Here's a view of one LCD panel used for this project:

2 Graphic LCD panel - Introduction Graphic LCD panels use a digital interface and are easy to interface to FPGAs. The different interfaces Graphic LCD panels come in 2 flavors: 1. With a Video-like interface 2. With a CPU-peripheral-like interface Advantages 1. Video-like interface Low cost & widely available (used in notebook computers for example) Easy to control from an FPGA Freedom on what is displayed 2. CPU-peripheral-like interface Easy to attach to microcontrollers A frame-buffer memory is integrated

3 (frame-buffer/on-the-fly video/sprites/hardware mouse cursor... or any combination of these) to the panel Disadvantages Requires a video controller (FPGA or dedicated chip) Requires some external memory (for the frame-buffer, character generator,...) Higher cost & lower availability For frame-buffer applications only How it works Uses a video signal - with HSync (horizontal sync) and VSync (vertical sync) pulses Similar to a VGA signal, but with digital RGB video signals The panel appears like a memory (SRAM) to the microcontroller The CPU writes to the SRAM and the data appears on the screen This project uses "type-1" panels - since we use FPGAs here, that's the most appropriate. Graphic LCD panel - video generator Prior to be able to display anything on the panel, we need to generate video-sync signals (H-sync and V-sync). The LCD used for this project has the following characteristics: Monochrome, with a 480x320 resolution (about pixels). Synchronous interface, 4-bits data interface (4 pixels are entered for each clock). No off-screen period. With a 4-bits data input, we need 480/4=120 clocks horizontally. With 320 lines, a complete video frame takes 120x320=38400 clocks. The code looks like that: parameter ScreenWidth = 480; parameter ScreenHeight = 320;

4 reg [6:0] CounterX; // counts from 0 to 119 reg [8:0] CounterY; // counts from 0 to 319 wire CounterXmaxed = (CounterX==ScreenWidth/4-1); wire CounterYmaxed = (CounterY==ScreenHeight-1); clk) begin if(counterxmaxed) CounterX <= 0; else CounterX <= CounterX + 1; end clk) if(counterxmaxed) begin if(counterymaxed) CounterY <= 0; else CounterY <= CounterY + 1; end reg HSync, VSync; clk) begin HSync <= CounterXmaxed; VSync <= CounterYmaxed; end Now, let's provide data to be displayed - first some graphics, then some text. Graphic LCD panel - Graphics Let's investigate 3 ways to generate graphical video data.

5 Rasterized bitmaps The classical (and easy) way to display graphics on an LCD is to hold rasterized bitmap data into a RAM. We are going to use a blockram here (see here to learn what are blockrams). We display a small 128x32 pixels bitmap here (fits nicey into a 4Kbits blockram): // Use a blockram to hold the graphical data wire [7:0] BitmapData; blockram_8x512 RAM_bitmap(.clk(clk),.rd_adr({CounterY[4:0],CounterX[4:1]}),.data_out(Bit mapdata)); // Let's say we need 4 bits at a time wire [3:0] LCD_Bitmap4 = CounterX[0]? BitmapData[3:0] : BitmapData[7:4]; // Display the data into a chessboard pattern wire [3:0] LCD_BitmapChessboard = (CounterY[5] ^ CounterX[5])? 4'b000 : LCD_Bitmap4 ^ {4{CounterY[5]}}; Not shown above is how the RAM is written. The easiest is to treat it as a ROM (the RAM content is part of the FPGA configuration, and doesn't change while the FPGA is running). Here's a macro shot:

6 The drawback of rasterized bitmaps is that you require a large enough RAM to hold the state of each pixel of the bitmap. That's expensive using internal FPGA RAM, so external RAM is often used instead. Now, let's explore more original ways to create graphics. Curve y=f(x) Let's say we want to display an y=f(x) waveform, like a sine. That's surprisingly easy to do. We hold the "Y" values into a blockram and generate the picture line by line by reading the RAM and comparing the values against "CounterY" (the current line number). // We assume CounterX and CounterY are available: // CounterX is the pixel number of the current line // CounterY is the line number // We use a RAM to hold the "Y" values // Y=F(CounterX) wire [7:0] RAM_Y_value;

7 blockram_8x512 RAM_FXY(.clk(clk),.rd_adr(CounterX),.data_out(RAM_Y_value)); // check for equality between the "Y" values and "CounterY" reg grcpeq1; clk) grcpeq1 <= (RAM_Y_value==CounterY); reg grcpeq2; clk) grcpeq2 <= grcpeq1; // check for "greater-than" between the "Y" values and "CounterY" reg grcp1; clk) grcp1 <= (RAM_Y_value>CounterY); reg grcp2; clk) grcp2 <= grcp1; // display a pixel if equality, or if "CounterY" is between 2 successive "Y" values wire FXpix= grcpeq2 (grcp1 ^ grcp2); Here's the result using F(x)=cos(x*2*pi/480)*sin(x*2*pi/480*4):

8 Rotozoom A Rotozoom is an efficient method to display a bitmap with linear geometric distortions. In particular, that allows easy rotating and zooming of a picture. In the following implementation, we display a rotated chessboard pattern on the screen. reg [15:0] X0, Y0, X1, Y1; clk) if(vsync) begin X0 <= 0; Y0 <= 0; X1 <= 0; Y1 <= 0; end else if(hsync) begin X0 <= X1-100; Y0 <= Y ; X1 <= X1-100; Y1 <= Y ; end else begin X0 <= X ; Y0 <= Y ; end // Display a chessboard pattern by XOR'ing the MSB of X and Y counters // You could also display a rotozoomed bitmap by feeding X and Y to a bitmap in a RAM wire rotozoom_pix = X0[15] ^ Y0[15];

9 This is simplified because the increment values are fixed (400 and 100 above). You'd want to vary them in a real implementation. By varying the coefficients, you rotate and zoom the chessboard. Here's the result, mixed with the previous waveform: You can then mix that with some text... Graphic LCD panel - Text Let's try to display characters on our panel. This way, the panel can be used as a text terminal. Our 480x320 sample panel can be used as a 80 columns x 40 lines console (using 6x8 characters font) or 60 columns x 40 lines console (using 8x8 character font). We are going to use a "character generator" technique. Character generator

10 Let's assume the word "Hello" is somewhere on the screen. In ASCII, that uses 5 bytes (0x48, 0x65, 0x6C, 0x6C, 0x6F). Our simple character generator uses one RAM to hold the characters to display, and one ROM to hold the font. "Font ROM" contains the representation of each possible characters. Here're sample sets: Changing the content of the "Character RAM" makes characters appear on the panel. 8x8 font implementation On the panel, a 6x8 font looks somewhat nicer than a 8x8 font, but 8x8 is easier to implement, so that's what we try first. By using a 2Kbytes RAM for the "Character RAM", we can have 32 lines of 64 characters... so 5 bits to count the lines and 6 bits to count the columns. By keeping all the numbers a power of two, the implementation stays as simple as possible. Here's what we got:

11 We use 6 bits from CounterX, and 8 bits from CounterY (5 bits for the "Character RAM", plus 3 bits for the "Font ROM"). "Font ROM" uses a total of 11 bits. The design goes as follow: wire [7:0] CharacterRAM_dout; ram8x2048 CharacterRAM(.clk(clk),.rd_adr({CounterY[7:3],CounterX[6:1]}),.data_out(CharacterRAM_dout) ); wire [7:0] raster8; rom8x2048 FontROM(.clk(clk),.rd_adr({CharacterRAM_dout, CounterY[2:0]}),.data_out(raster8) ); wire [3:0] LCDdata = CounterX[0]? raster8[7:4] : raster8[3:0]; A few details: Because my LCD panel takes 4-pixels per clock, we need 2 clocks for 1 character width (1 character width=8 pixels). That's why "Character RAM" uses "CounterX[6:1]" instead of "CounterX[5:0]" above. In an FPGA, it makes sense that the "Font ROM" is actually a RAM. This way, the font can be loaded or changed at runtime. The mechanism to write the RAMs is not shown above.

12 Here's a shot of the LCD with an 8x8 font: 6x8 font implementation The 6x8 font allows for more characters to be displayed (and looks better on the panel too!). My particular panel width is 480 pixels, which translates conveniently into 80 columns. The 6x8 font is more complicated to handle than 8x8 because the font width (6) is not a power of 2. That means we don't display the same part of a character at each clock cycle anymore. With CounterX=0, we display the first 4 pixels of CHAR[0] With CounterX=1, we display the last 2 pixels of CHAR[0] and the first 2 pixels of CHAR[1] With CounterX=2, we display the last 4 pixels of CHAR[1] With CounterX=3, we display the first 4 pixels of CHAR[2] With CounterX=4, we display the last 2 pixels of CHAR[2] and the first 2 pixels of CHAR[3]... That is done using a simple case statement wire [3:0] charfont0, charfont1; clk) begin case(cnt_mod3) 2'b00: LCDdata <= charfont0;

13 2'b01: LCDdata <= {charfont0[3:2], charfont1[3:2]}; 2'b10: LCDdata <= {charfont1[3:2], charfont0[1:0]}; endcase end with a modulus-3 counter (it counts 0, 1, 2, 0, 1, 2, 0, 1,...) reg [1:0] cnt_mod3; clk) if(cnt_mod3==2) cnt_mod3 <= 0; else cnt_mod3 <= cnt_mod3 + 1; but we also need a character-counter for the "Character RAM" // character-counter (increments only twice every 3 clocks) reg [6:0] cnt_charbuf; clk) if(cnt_mod3!=1) cnt_charbuf <= cnt_charbuf + 1; wire [11:0] CharacterRAM_rdaddr = CounterY[8:3]*80 + cnt_charbuf; wire [7:0] CharacterRAM_dout; ram8x2048 CharacterRAM(.clk(clk),.rd_adr(CharacterRAM_rdaddr),.data_out(CharacterRAM_dout) ); and two "Font ROMs". // remember the previous character displayed reg [7:0] RAM_charbuf_dout_last; clk) CharacterRAM_dout_last <= CharacterRAM_dout; // because we need it when we display 2 half characters at once wire [10:0] readaddr0 = {CharacterRAM_dout, CounterY[2:0]}; wire [10:0] readaddr1 = {CharacterRAM_dout_last, CounterY[2:0]}; // The font ROMs are split in two blockrams, holding 4 pixels each // (half of the second ROM is not used, since we need only 6 pixels) rom4x2048 FontROM0(.clk(clk),.rd_adr(readaddr0),.data_out(charfont0));

14 rom4x2048 FontROM1(.clk(clk),.rd_adr(readaddr1),.data_out(charfont1)); Here's a shot of the LCD with an 6x8 font: Hardware cursor Let's implement a blinking cursor that can be placed on any character on the panel. First we use a video-frame counter to "time" the blinking. Using 6 bits, the cursor blinks every 64 frames. reg [5:0] cnt_cursorblink; clk) if(vsync & hsync) cnt_cursorblink <= cnt_cursorblink + 1; wire cursorblinkstate = cnt_cursorblink[5]; // cursor on for 32 frames, off for 32 frames Now let's assume the cursor address position is available in a "CursorAddress" register. // Do we have a cursor-character match? wire cursorblink_adrmatch = cursorblinkstate & (CharacterRAM_rdaddr==CursorAddress); // When we have a match, "invert" the character // First for charfont0 wire [3:0] charfont0_cursor = charfont0 ^ {4{cursorblink_adrmatch}};

15 // Next for charfont1 reg cursorblink_adrmatch_last; clk) cursorblink_adrmatch_last <= cursorblink_adrmatch; wire [3:0] charfont1_cursor = charfont1 ^ {4{cursorblink_adrmatch_last}}; Whoa, we can display graphics and text! All this is applicable to monochrome and color LCDs. Here's what happens when we get carried away on a color LCD... Your turn to experiment!

Design and Implementation of an AHB VGA Peripheral

Design and Implementation of an AHB VGA Peripheral Design and Implementation of an AHB VGA Peripheral 1 Module Overview Learn about VGA interface; Design and implement an AHB VGA peripheral; Program the peripheral using assembly; Lab Demonstration. System

More information

EECS150 - Digital Design Lecture 13 - Project Description, Part 3 of? Project Overview

EECS150 - Digital Design Lecture 13 - Project Description, Part 3 of? Project Overview EECS150 - Digital Design Lecture 13 - Project Description, Part 3 of? March 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec13-proj3 Page 1 Project Overview A. MIPS150 pipeline structure B. Memories, project

More information

Lab # 9 VGA Controller

Lab # 9 VGA Controller Lab # 9 VGA Controller Introduction VGA Controller is used to control a monitor (PC monitor) and has a simple protocol as we will see in this lab. Kit parts for this lab 1 A closer look VGA Basics The

More information

TSIU03: Lab 3 - VGA. Petter Källström, Mario Garrido. September 10, 2018

TSIU03: Lab 3 - VGA. Petter Källström, Mario Garrido. September 10, 2018 Petter Källström, Mario Garrido September 10, 2018 Abstract In the initialization of the DE2-115 (after you restart it), an image is copied into the SRAM memory. What you have to do in this lab is to read

More information

VGA Controller. Leif Andersen, Daniel Blakemore, Jon Parker University of Utah December 19, VGA Controller Components

VGA Controller. Leif Andersen, Daniel Blakemore, Jon Parker University of Utah December 19, VGA Controller Components VGA Controller Leif Andersen, Daniel Blakemore, Jon Parker University of Utah December 19, 2012 Fig. 1. VGA Controller Components 1 VGA Controller Leif Andersen, Daniel Blakemore, Jon Parker University

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP Digital Blocks Semiconductor IP General Description The Digital Blocks core is a full function equivalent to the Motorola MC6845 device. The interfaces a microprocessor to a raster-scan CRT display. The

More information

Using the Renesas Graphics API to Create a User Interface

Using the Renesas Graphics API to Create a User Interface Using the Renesas Graphics API to Create a User Interface Renesas Electronics America Inc. Renesas Technology & Solution Portfolio 2 Renesas Technology & Solution Portfolio 3 Microcontroller and Microprocessor

More information

Video. Updated fir31.filtered on website Fall 2008 Lecture 12

Video. Updated fir31.filtered on website Fall 2008 Lecture 12 Video Generating video sync signals Decoding NTSC video -- color space conversions Generating pixels -- test patterns -- character display -- sprite-based games Lab #4 due Thursday, project teams next

More information

Display Technology.! Images stolen from various locations on the web... Cathode Ray Tube

Display Technology.! Images stolen from various locations on the web... Cathode Ray Tube Display Technology! Images stolen from various locations on the web... Cathode Ray Tube 1 Cathode Ray Tube Raster Scanning 2 Electron Gun Beam Steering Coils 3 Color Shadow Mask and Aperture Grille 4 Liquid

More information

Display Technology. Cathode Ray Tube. Images stolen from various locations on the web...

Display Technology. Cathode Ray Tube. Images stolen from various locations on the web... Display Technology Cathode Ray Tube Images stolen from various locations on the web... Cathode Ray Tube Raster Scanning Electron Gun Beam Steering Coils 1 Color Shadow Mask and Aperture Grille Liquid Crystal

More information

IMS B007 A transputer based graphics board

IMS B007 A transputer based graphics board IMS B007 A transputer based graphics board INMOS Technical Note 12 Ray McConnell April 1987 72-TCH-012-01 You may not: 1. Modify the Materials or use them for any commercial purpose, or any public display,

More information

USER MANUAL Nokia 5110 LCD

USER MANUAL Nokia 5110 LCD USER MANUAL Nokia 5110 LCD Introduction: This 84x48 pixel black and white LCDs are what you might have found in an old Nokia 3310 or 5110 cell phone. They re not flashy, not colorful and there s no touch

More information

L14 - Video. L14: Spring 2005 Introductory Digital Systems Laboratory

L14 - Video. L14: Spring 2005 Introductory Digital Systems Laboratory L14 - Video Slides 2-10 courtesy of Tayo Akinwande Take the graduate course, 6.973 consult Prof. Akinwande Some modifications of these slides by D. E. Troxel 1 How Do Displays Work? Electronic display

More information

Design of VGA Controller using VHDL for LCD Display using FPGA

Design of VGA Controller using VHDL for LCD Display using FPGA International OPEN ACCESS Journal Of Modern Engineering Research (IJMER) Design of VGA Controller using VHDL for LCD Display using FPGA Khan Huma Aftab 1, Monauwer Alam 2 1, 2 (Department of ECE, Integral

More information

Video Graphics Array (VGA)

Video Graphics Array (VGA) Video Graphics Array (VGA) Chris Knebel Ian Kaneshiro Josh Knebel Nathan Riopelle Image Source: Google Images 1 Contents History Design goals Evolution The protocol Signals Timing Voltages Our implementation

More information

An Efficient SOC approach to Design CRT controller on CPLD s

An Efficient SOC approach to Design CRT controller on CPLD s A Monthly Peer Reviewed Open Access International e-journal An Efficient SOC approach to Design CRT controller on CPLD s Abstract: Sudheer Kumar Marsakatla M.tech Student, Department of ECE, ACE Engineering

More information

TV Character Generator

TV Character Generator TV Character Generator TV CHARACTER GENERATOR There are many ways to show the results of a microcontroller process in a visual manner, ranging from very simple and cheap, such as lighting an LED, to much

More information

VGA Port. Chapter 5. Pin 5 Pin 10. Pin 1. Pin 6. Pin 11. Pin 15. DB15 VGA Connector (front view) DB15 Connector. Red (R12) Green (T12) Blue (R11)

VGA Port. Chapter 5. Pin 5 Pin 10. Pin 1. Pin 6. Pin 11. Pin 15. DB15 VGA Connector (front view) DB15 Connector. Red (R12) Green (T12) Blue (R11) Chapter 5 VGA Port The Spartan-3 Starter Kit board includes a VGA display port and DB15 connector, indicated as 5 in Figure 1-2. Connect this port directly to most PC monitors or flat-panel LCD displays

More information

Lecture 14: Computer Peripherals

Lecture 14: Computer Peripherals Lecture 14: Computer Peripherals The last homework and lab for the course will involve using programmable logic to make interesting things happen on a computer monitor should be even more fun than the

More information

Hitachi Europe Ltd. ISSUE : app084/1.0 APPLICATION NOTE DATE : 28/04/99

Hitachi Europe Ltd. ISSUE : app084/1.0 APPLICATION NOTE DATE : 28/04/99 APPLICATION NOTE DATE : 28/04/99 Design Considerations when using a Hitachi Medium Resolution Dot Matrix Graphics LCD Introduction Hitachi produces a wide range of monochrome medium resolution dot matrix

More information

FPGA Laboratory Assignment 4. Due Date: 06/11/2012

FPGA Laboratory Assignment 4. Due Date: 06/11/2012 FPGA Laboratory Assignment 4 Due Date: 06/11/2012 Aim The purpose of this lab is to help you understanding the fundamentals of designing and testing memory-based processing systems. In this lab, you will

More information

Display Technology. Images stolen from various locations on the web... Cathode Ray Tube

Display Technology. Images stolen from various locations on the web... Cathode Ray Tube Display Technology Images stolen from various locations on the web... Cathode Ray Tube Cathode Ray Tube Raster Scanning Electron Gun Beam Steering Coils Color Shadow Mask and Aperture Grille Liquid Crystal

More information

Design and Implementation of Timer, GPIO, and 7-segment Peripherals

Design and Implementation of Timer, GPIO, and 7-segment Peripherals Design and Implementation of Timer, GPIO, and 7-segment Peripherals 1 Module Overview Learn about timers, GPIO and 7-segment display; Design and implement an AHB timer, a GPIO peripheral, and a 7-segment

More information

Spartan-II Development System

Spartan-II Development System 2002-May-4 Introduction Dünner Kirchweg 77 32257 Bünde Germany www.trenz-electronic.de The Spartan-II Development System is designed to provide a simple yet powerful platform for FPGA development, which

More information

AD9884A Evaluation Kit Documentation

AD9884A Evaluation Kit Documentation a (centimeters) AD9884A Evaluation Kit Documentation Includes Documentation for: - AD9884A Evaluation Board - SXGA Panel Driver Board Rev 0 1/4/2000 Evaluation Board Documentation For the AD9884A Purpose

More information

VGA 8-bit VGA Controller

VGA 8-bit VGA Controller Summary This document provides detailed reference information with respect to the VGA Controller peripheral device. Core Reference CR0113 (v3.0) March 13, 2008 The VGA Controller provides a simple, 8-bit

More information

Lab 3: VGA Bouncing Ball I

Lab 3: VGA Bouncing Ball I CpE 487 Digital Design Lab Lab 3: VGA Bouncing Ball I 1. Introduction In this lab, we will program the FPGA on the Nexys2 board to display a bouncing ball on a 640 x 480 VGA monitor connected to the VGA

More information

Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel

Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel Application Note This application note explains how to determine if a specific LCD panel is supported by the Élan TM

More information

A * Rockwell. R6500 Microcomputer System DATA SHEET CRT CONTROLLER (CRTC) r- r- 31 O PART NUMBER R FEATURES DESCRIPTION O 30-4 O O

A * Rockwell. R6500 Microcomputer System DATA SHEET CRT CONTROLLER (CRTC) r- r- 31 O PART NUMBER R FEATURES DESCRIPTION O 30-4 O O PART NUMBER R6545-1 A * Rockwell R6500 Microcomputer System DATA SHEET CRT CONTROLLER (CRTC) DESCRIPTION The R6545-1 CRT Controller (CRTC) is designed to interface an 8-bit microprocessor to CRT raster

More information

Video Display Unit (VDU)

Video Display Unit (VDU) Video Display Unit (VDU) Historically derived from Cathode Ray Tube (CRT) technology Based on scan lines Horizontal flyback Vertical flyback Blank Active video Blank (vertical flyback takes several line

More information

VID_OVERLAY. Digital Video Overlay Module Rev Key Design Features. Block Diagram. Applications. Pin-out Description

VID_OVERLAY. Digital Video Overlay Module Rev Key Design Features. Block Diagram. Applications. Pin-out Description Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Video overlays on 24-bit RGB or YCbCr 4:4:4 video Supports all video resolutions up to 2 16 x 2 16 pixels Supports any

More information

HD66840/HD LVIC/LVIC-II (LCD Video Interface Controller) Description. Features

HD66840/HD LVIC/LVIC-II (LCD Video Interface Controller) Description. Features HD6684/HD6684 LVIC/LVIC-II (LCD Video Interface Controller) Description The HD6684/HD6684 LCD video interface controller (LVIC/LVIC-II) converts standard RGB video signals for CRT display into LCD data.

More information

Configuring and using the DCU2 on the MPC5606S MCU

Configuring and using the DCU2 on the MPC5606S MCU Freescale Semiconductor Document Number: AN4187 Application Note Rev. 0, 11/2010 Configuring and using the DCU2 on the MPC5606S MCU by: Steve McAslan Microcontroller Solutions Group 1 Introduction The

More information

SPI Serial Communication and Nokia 5110 LCD Screen

SPI Serial Communication and Nokia 5110 LCD Screen 8 SPI Serial Communication and Nokia 5110 LCD Screen 8.1 Objectives: Many devices use Serial Communication to communicate with each other. The advantage of serial communication is that it uses relatively

More information

Oscilloscopes, logic analyzers ScopeLogicDAQ

Oscilloscopes, logic analyzers ScopeLogicDAQ Oscilloscopes, logic analyzers ScopeLogicDAQ ScopeLogicDAQ 2.0 is a comprehensive measurement system used for data acquisition. The device includes a twochannel digital oscilloscope and a logic analyser

More information

LAX_x Logic Analyzer

LAX_x Logic Analyzer Legacy documentation LAX_x Logic Analyzer Summary This core reference describes how to place and use a Logic Analyzer instrument in an FPGA design. Core Reference CR0103 (v2.0) March 17, 2008 The LAX_x

More information

7inch Resistive Touch LCD User Manual

7inch Resistive Touch LCD User Manual 7inch Resistive Touch LCD User Manual Chinese website: www.waveshare.net English website: www.wvshare.com Data download: www.waveshare.net/wiki Shenzhen Waveshare Electronics Ltd. Co. 1 Contents 1. Overview...

More information

Lancelot. VGA video controller for the Altera Nios II processor. V4.0. December 16th, 2005

Lancelot. VGA video controller for the Altera Nios II processor. V4.0. December 16th, 2005 Lancelot VGA video controller for the Altera Nios II processor. V4.0 December 16th, 2005 http://www.microtronix.com 1. Description Lancelot is a VGA video controller for the Altera Nios (II) processor.

More information

Week 5 Dr. David Ward Hybrid Embedded Systems

Week 5 Dr. David Ward Hybrid Embedded Systems Week 5 Dr. David Ward Hybrid Embedded Systems Today s Agenda Discuss Homework and Labs HW #2 due September 24 (this Friday by midnight) Don t start Lab # 5 until next week Work on HW #2 in today s lab

More information

Part 1: Introduction to Computer Graphics

Part 1: Introduction to Computer Graphics Part 1: Introduction to Computer Graphics 1. Define computer graphics? The branch of science and technology concerned with methods and techniques for converting data to or from visual presentation using

More information

Digilent Nexys-3 Cellular RAM Controller Reference Design Overview

Digilent Nexys-3 Cellular RAM Controller Reference Design Overview Digilent Nexys-3 Cellular RAM Controller Reference Design Overview General Overview This document describes a reference design of the Cellular RAM (or PSRAM Pseudo Static RAM) controller for the Digilent

More information

Display Technology. Images stolen from various locations on the web... Cathode Ray Tube

Display Technology. Images stolen from various locations on the web... Cathode Ray Tube Display Technology Images stolen from various locations on the web... Cathode Ray Tube 1 Cathode Ray Tube Raster Scanning 2 Electron Gun Beam Steering Coils 3 Color Shadow Mask and Aperture Grille 4 Liquid

More information

EDA385 Bomberman. Fredrik Ahlberg Adam Johansson Magnus Hultin

EDA385 Bomberman. Fredrik Ahlberg Adam Johansson Magnus Hultin EDA385 Bomberman Fredrik Ahlberg ael09fah@student.lu.se Adam Johansson rys08ajo@student.lu.se Magnus Hultin ael08mhu@student.lu.se 2013-09-23 Abstract This report describes how a Super Nintendo Entertainment

More information

TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T7779

TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T7779 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T7779 CRT / LCD CONTROLLER LS The T7779 is a controller LSI for a raster scan type CRT display and large scale dot matrix LCD. It can be used

More information

Different Display Configurations on the i.mx31 WinCE PDK

Different Display Configurations on the i.mx31 WinCE PDK Freescale Semiconductor Application Note Document Number: AN4041 Rev. 0, 03/2010 Different Display Configurations on the i.mx31 WinCE PDK by Multimedia Application Division Freescale Semiconductor, Inc.

More information

Group 1. C.J. Silver Geoff Jean Will Petty Cody Baxley

Group 1. C.J. Silver Geoff Jean Will Petty Cody Baxley Group 1 C.J. Silver Geoff Jean Will Petty Cody Baxley Vision Enhancement System 3 cameras Visible, IR, UV Image change functions Shift, Drunken Vision, Photo-negative, Spectrum Shift Function control via

More information

A Fast Constant Coefficient Multiplier for the XC6200

A Fast Constant Coefficient Multiplier for the XC6200 A Fast Constant Coefficient Multiplier for the XC6200 Tom Kean, Bernie New and Bob Slous Xilinx Inc. Abstract. We discuss the design of a high performance constant coefficient multiplier on the Xilinx

More information

LOCAL DECODING OF WALSH CODES TO REDUCE CDMA DESPREADING COMPUTATION. Matt Doherty Introductory Digital Systems Laboratory.

LOCAL DECODING OF WALSH CODES TO REDUCE CDMA DESPREADING COMPUTATION. Matt Doherty Introductory Digital Systems Laboratory. LOCAL DECODING OF WALSH CODES TO REDUCE CDMA DESPREADING COMPUTATION Matt Doherty 6.111 Introductory Digital Systems Laboratory May 18, 2006 Abstract As field-programmable gate arrays (FPGAs) continue

More information

Design and Implementation of SOC VGA Controller Using Spartan-3E FPGA

Design and Implementation of SOC VGA Controller Using Spartan-3E FPGA Design and Implementation of SOC VGA Controller Using Spartan-3E FPGA 1 ARJUNA RAO UDATHA, 2 B.SUDHAKARA RAO, 3 SUDHAKAR.B. 1 Dept of ECE, PG Scholar, 2 Dept of ECE, Associate Professor, 3 Electronics,

More information

Unit 3: Parallel I/O and Handshaking for LCD Control

Unit 3: Parallel I/O and Handshaking for LCD Control 1300 Henley Court Pullman, WA 99163 509.334.6306 www.store.digilentinc.com Unit 3: Parallel I/O and Handshaking for LCD Control Revised March 10, 2017 This manual applies to Unit 3 1 Introduction Throughout

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Introductory Digital Systems Laboratory

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Introductory Digital Systems Laboratory Problem Set Issued: March 2, 2007 Problem Set Due: March 14, 2007 Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 Introductory Digital Systems Laboratory

More information

Video Output and Graphics Acceleration

Video Output and Graphics Acceleration Video Output and Graphics Acceleration Overview Frame Buffer and Line Drawing Engine Prof. Kris Pister TAs: Vincent Lee, Ian Juch, Albert Magyar Version 1.5 In this project, you will use SDRAM to implement

More information

C6845 CRT Controller Megafunction

C6845 CRT Controller Megafunction 查询 C6845 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 C6845 CRT ler Megafunction General Description The C6845 Cathode Ray Tube ler (CRTC) interfaces a microprocessor to a raster-scan CRT display. The C6845 is a synchronous,

More information

Testing Results for a Video Poker System on a Chip

Testing Results for a Video Poker System on a Chip Testing Results for a Video Poker System on a Chip Preston Thomson and Travis Johnson Introduction- This report examines the results of a system on a chip SoC video poker system. The report will begin

More information

4.3inch 480x272 Touch LCD (B) User Manual

4.3inch 480x272 Touch LCD (B) User Manual 4.3inch 480x272 Touch LCD (B) User Manual Chinese website: www.waveshare.net English Website: www.wvshare.com Data download: www.waveshare.net/wiki Shenzhen Waveshare Electronics Ltd. Co. 1 目录 1. Overview...

More information

An FPGA Based Solution for Testing Legacy Video Displays

An FPGA Based Solution for Testing Legacy Video Displays An FPGA Based Solution for Testing Legacy Video Displays Dale Johnson Geotest Marvin Test Systems Abstract The need to support discrete transistor-based electronics, TTL, CMOS and other technologies developed

More information

A CONTROL MECHANISM TO THE ANYWHERE PIXEL ROUTER

A CONTROL MECHANISM TO THE ANYWHERE PIXEL ROUTER University of Kentucky UKnowledge University of Kentucky Master's Theses Graduate School 2007 A CONTROL MECHANISM TO THE ANYWHERE PIXEL ROUTER Subhasri Krishnan University of Kentucky, skris0@engr.uky.edu

More information

ECE 448 Lecture 10. VGA Display Part 1 VGA Synchronization

ECE 448 Lecture 10. VGA Display Part 1 VGA Synchronization ECE 448 Lecture 10 VGA Display Part 1 VGA Synchronization George Mason University Required Reading Old Edition of the Textbook 2008 (see Piazza) P. Chu, FPGA Prototyping by VHDL Examples Chapter 12, VGA

More information

Lab Assignment 2 Simulation and Image Processing

Lab Assignment 2 Simulation and Image Processing INF5410 Spring 2011 Lab Assignment 2 Simulation and Image Processing Lab goals Implementation of bus functional model to test bus peripherals. Implementation of a simple video overlay module Implementation

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters

More information

ELEX 7660: Digital System Design Composite Video Encoder with SPI Interface. Matthew Knight, Cole Harkness

ELEX 7660: Digital System Design Composite Video Encoder with SPI Interface. Matthew Knight, Cole Harkness ELEX 7660: Digital System Design Composite Video Encoder with SPI Interface Matthew Knight, Cole Harkness 2017 04 17 Contents Introduction 3 Letter from Matt Knight...............................................

More information

EECS150 - Digital Design Lecture 12 - Video Interfacing. Recap and Outline

EECS150 - Digital Design Lecture 12 - Video Interfacing. Recap and Outline EECS150 - Digital Design Lecture 12 - Video Interfacing Oct. 8, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John

More information

Modeling Digital Systems with Verilog

Modeling Digital Systems with Verilog Modeling Digital Systems with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 6-1 Composition of Digital Systems Most digital systems can be partitioned into two types

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Introductory Digital Systems Laboratory

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Introductory Digital Systems Laboratory Problem Set Issued: March 3, 2006 Problem Set Due: March 15, 2006 Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 Introductory Digital Systems Laboratory

More information

Read-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus

Read-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable

More information

ECE532 Digital System Design Title: Stereoscopic Depth Detection Using Two Cameras. Final Design Report

ECE532 Digital System Design Title: Stereoscopic Depth Detection Using Two Cameras. Final Design Report ECE532 Digital System Design Title: Stereoscopic Depth Detection Using Two Cameras Group #4 Prof: Chow, Paul Student 1: Robert An Student 2: Kai Chun Chou Student 3: Mark Sikora April 10 th, 2015 Final

More information

LED Array Tutorial. This guide explains how to set up and operate the LED arrays that can be used for your. Internal Structure of LED Array

LED Array Tutorial. This guide explains how to set up and operate the LED arrays that can be used for your. Internal Structure of LED Array LED Array Tutorial This guide explains how to set up and operate the LED arrays that can be used for your final EE 271 project. This tutorial is directed towards the FYM12882AEG 8x8 LED array, but these

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error

More information

Laboratory Exercise 4

Laboratory Exercise 4 Laboratory Exercise 4 Polling and Interrupts The purpose of this exercise is to learn how to send and receive data to/from I/O devices. There are two methods used to indicate whether or not data can be

More information

2.13inch e-paper HAT (D) User Manual

2.13inch e-paper HAT (D) User Manual 2.13inch e-paper HAT (D) User Manual OVERVIRE This is a flexible E-Ink display HAT for Raspberry Pi, 2.13inch, 212x104 resolution, with embedded controller, communicating via SPI interface, supports partial

More information

Using the Siemens S65 Display

Using the Siemens S65 Display Using the Siemens S65 Display by Christian Kranz, October 2005 ( http://www.superkranz.de/christian/s65_display/displayindex.html ) ( PDF by Benjamin Metz, September 09 th, 2006 ) About the Display: Siemens

More information

Chapter 7 Counters and Registers

Chapter 7 Counters and Registers Chapter 7 Counters and Registers Chapter 7 Objectives Selected areas covered in this chapter: Operation & characteristics of synchronous and asynchronous counters. Analyzing and evaluating various types

More information

Checkpoint 2 Video Interface

Checkpoint 2 Video Interface University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 Fall 1998 R. Fearing and Kevin Cho 1. Objective Checkpoint 2 Video Interface

More information

6.111 Project Proposal IMPLEMENTATION. Lyne Petse Szu-Po Wang Wenting Zheng

6.111 Project Proposal IMPLEMENTATION. Lyne Petse Szu-Po Wang Wenting Zheng 6.111 Project Proposal Lyne Petse Szu-Po Wang Wenting Zheng Overview: Technology in the biomedical field has been advancing rapidly in the recent years, giving rise to a great deal of efficient, personalized

More information

VGA Configuration Algorithm using VHDL

VGA Configuration Algorithm using VHDL VGA Configuration Algorithm using VHDL 1 Christian Plaza, 2 Olga Ramos, 3 Dario Amaya Virtual Applications Group-GAV, Nueva Granada Military University UMNG Bogotá, Colombia. Abstract Nowadays it is important

More information

Block Diagram. dw*3 pixin (RGB) pixin_vsync pixin_hsync pixin_val pixin_rdy. clk_a. clk_b. h_s, h_bp, h_fp, h_disp, h_line

Block Diagram. dw*3 pixin (RGB) pixin_vsync pixin_hsync pixin_val pixin_rdy. clk_a. clk_b. h_s, h_bp, h_fp, h_disp, h_line Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC reset underflow Supplied as human readable VHDL (or Verilog) source code Simple FIFO input interface

More information

DATASHEET HMP8154, HMP8156A. Features. Ordering Information. Applications. NTSC/PAL Encoders. FN4343 Rev.5.00 Page 1 of 34.

DATASHEET HMP8154, HMP8156A. Features. Ordering Information. Applications. NTSC/PAL Encoders. FN4343 Rev.5.00 Page 1 of 34. NTSC/PAL Encoders NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DATASHEET FN4343 Rev.5.00 The HMP8154 and HMP8156A

More information

Risk Risk Title Severity (1-10) Probability (0-100%) I FPGA Area II Timing III Input Distortion IV Synchronization 9 60

Risk Risk Title Severity (1-10) Probability (0-100%) I FPGA Area II Timing III Input Distortion IV Synchronization 9 60 Project Planning Introduction In this section, the plans required for completing the project from start to finish are described. The risk analysis section of this project plan will describe the potential

More information

Sapera LT 8.0 Acquisition Parameters Reference Manual

Sapera LT 8.0 Acquisition Parameters Reference Manual Sapera LT 8.0 Acquisition Parameters Reference Manual sensors cameras frame grabbers processors software vision solutions P/N: OC-SAPM-APR00 www.teledynedalsa.com NOTICE 2015 Teledyne DALSA, Inc. All rights

More information

Part 1: Introduction to computer graphics 1. Describe Each of the following: a. Computer Graphics. b. Computer Graphics API. c. CG s can be used in

Part 1: Introduction to computer graphics 1. Describe Each of the following: a. Computer Graphics. b. Computer Graphics API. c. CG s can be used in Part 1: Introduction to computer graphics 1. Describe Each of the following: a. Computer Graphics. b. Computer Graphics API. c. CG s can be used in solving Problems. d. Graphics Pipeline. e. Video Memory.

More information

VARIABLE FREQUENCY CLOCKING HARDWARE

VARIABLE FREQUENCY CLOCKING HARDWARE VARIABLE FREQUENCY CLOCKING HARDWARE Variable-Frequency Clocking Hardware Many complex digital systems have components clocked at different frequencies Reason 1: to reduce power dissipation The active

More information

VectorVGA Tempest User Manual

VectorVGA Tempest User Manual VectorVGA Tempest User Manual 2 Notice Regarding This Product WARNING! To install this product you should: Be familiar with safe handling procedures for electronic components. Be able to use hand tools

More information

The BAT WAVE ANALYZER project

The BAT WAVE ANALYZER project The BAT WAVE ANALYZER project Conditions of Use The Bat Wave Analyzer program is free for personal use and can be redistributed provided it is not changed in any way, and no fee is requested. The Bat Wave

More information

Revision: August 11, E Main Suite D Pullman, WA (509) Voice and Fax. 8 LEDs. Doc: page 1 of 9

Revision: August 11, E Main Suite D Pullman, WA (509) Voice and Fax. 8 LEDs. Doc: page 1 of 9 Digilent DIO4 Peripheral Board Reference Manual www.digilentinc.com Revision: August 11, 2004 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The DIO4 circuit board provides

More information

DT3162. Ideal Applications Machine Vision Medical Imaging/Diagnostics Scientific Imaging

DT3162. Ideal Applications Machine Vision Medical Imaging/Diagnostics Scientific Imaging Compatible Windows Software GLOBAL LAB Image/2 DT Vision Foundry DT3162 Variable-Scan Monochrome Frame Grabber for the PCI Bus Key Features High-speed acquisition up to 40 MHz pixel acquire rate allows

More information

User's Manual of LED LIGHTING CONTROL SYSTEM (VC-500A/B) VISS LIGHTING (SHENZHEN) CO.,LTD.

User's Manual of LED LIGHTING CONTROL SYSTEM (VC-500A/B) VISS LIGHTING (SHENZHEN) CO.,LTD. User's Manual of LED LIGHTING CONTROL SYSTEM (VC-500A/B) VISS LIGHTING (SHENZHEN) CO.,LTD www.viss.cn CONTENTS Part One LED LIGHTING CONTROL SYSTEM 1.Safety warning... 1-1 2.System description... 1-1 3.Parameter

More information

CAPTURE CAPTURE. VERSiON 1.2. Specialists in Medical. Digital Imaging Solutions

CAPTURE CAPTURE. VERSiON 1.2. Specialists in Medical. Digital Imaging Solutions CAPTURE Add-on module for capturing images from analog video sources CAPTURE anything to DICOm VERSiON 1.2 Specialists in Medical Digital Imaging Solutions iq-capture Connect any medical device to your

More information

980 Protocol Analyzer General Presentation. Quantum Data Inc Big Timber Road Elgin, IL USA Phone: (847)

980 Protocol Analyzer General Presentation. Quantum Data Inc Big Timber Road Elgin, IL USA Phone: (847) 980 Protocol Analyzer General Presentation 980 Protocol Analyzer For HDMI 1.4a & MHL Sources Key Features and Benefits Two 980 products offered: Gen 2 provides full visibility into HDMI protocol, timing,

More information

TV Synchronism Generation with PIC Microcontroller

TV Synchronism Generation with PIC Microcontroller TV Synchronism Generation with PIC Microcontroller With the widespread conversion of the TV transmission and coding standards, from the early analog (NTSC, PAL, SECAM) systems to the modern digital formats

More information

XC-77 (EIA), XC-77CE (CCIR)

XC-77 (EIA), XC-77CE (CCIR) XC-77 (EIA), XC-77CE (CCIR) Monochrome machine vision video camera modules. 1. Outline The XC-77/77CE is a monochrome video camera module designed for the industrial market. The camera is equipped with

More information

3/5/2017. A Register Stores a Set of Bits. ECE 120: Introduction to Computing. Add an Input to Control Changing a Register s Bits

3/5/2017. A Register Stores a Set of Bits. ECE 120: Introduction to Computing. Add an Input to Control Changing a Register s Bits University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Registers A Register Stores a Set of Bits Most of our representations use sets

More information

EE251: Thursday October 11

EE251: Thursday October 11 EE251: Thursday October 11 Mid-Term Exam Comments and Statistics SSI Serial I/O: continued as needed Nokia 5110 Graphics Subsystem SSI Interface to the 5110 Key Part of Lab #5 Use of Logic Analyzer, also

More information

GUIX Synergy Port Framework Module Guide

GUIX Synergy Port Framework Module Guide Introduction Application Note R11AN0217EU0101 Rev.1.01 This module guide will enable you to effectively use a module in your own design. Upon completion of this guide, you will be able to add this module

More information

21.1. Unit 21. Hardware Acceleration

21.1. Unit 21. Hardware Acceleration 21.1 Unit 21 Hardware Acceleration 21.2 Motivation When designing hardware we have nearly unlimited control and parallelism at our disposal We can create structures that may dramatically improve performance

More information

fbas_enc: FBAS(CVBS) encoder for PAL and/or NTSC

fbas_enc: FBAS(CVBS) encoder for PAL and/or NTSC fbas_enc: FBAS(CVBS) encoder for PAL and/or NTSC V0.31 (c) 2007 Jörg Wolfram 1 License This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General

More information

Chapter 3 Unit Combinational

Chapter 3 Unit Combinational EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Chapter 3 Unit Combinational 5 Registers Logic and Design Counters Part Implementation Technology

More information

Final Project [Tic-Tac-Toe]

Final Project [Tic-Tac-Toe] Final Project [Tic-Tac-Toe] (In 2 dimension) ECE 249 Session: 3-6pm TA: Jill Cannon Joseph S Kim Ghazy Mahub Introduction As a final project for ECE 249, we will develop a multi-player tic-tac-toe game

More information

Tearing Effect with Solomon SSD1963 Display Controller

Tearing Effect with Solomon SSD1963 Display Controller Introduction Tearing Effect with Solomon SSD1963 Display Controller This document explains how the Tearing Effect Signal (TE) of Solomon SSD1963 Display Controller IC can be used to void display flicker

More information

Sandia Project Document.doc

Sandia Project Document.doc Sandia Project Document Version 3.0 Author: Date: July 13, 2010 Reviewer: Don Figer Date: July 13, 2010 Printed on Monday, June 04, 2012 Sandia Project Document.doc 1.0 INTRODUCTION...1 2.0 PROJECT STATEMENT

More information

Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA

Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA NASIR MEHMOOD 1, JENS OGNIEWSKI AND VINODH RAVINATH 1 Department of Electrical Engineering Air University PAF Complex, Sector

More information