THE RISE of emerging applications like cloud computing,

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1 1 A Survey on FEC Codes for 100G and Beyond Optical Networks G. Tzimpragos, C. Kachris, I. B. Djordjevic, M. Cvijetic, D. Soudris, and I. Tomkos Abstract Due to the rapid increase of network traffic in the last few years, many telecommunication operators have started transitions to 100 Gb/s optical networks and beyond. However, high speed optical networks need more efficient Forward Error Correction (FEC) codes to deal with the optical-impairments, such as uncompensated chromatic dispersion (CD), polarization mode dispersion (PMD) and non-linear effects, and keep the biterror-rate (BER) at long distances sufficiently low. To address these issues, new FEC codes, called 3rd generation codes, have been proposed. The majority of these codes are based on soft-decision decoders and can provide higher coding gain as compared to their predecessors. This paper presents a thorough survey of 3rd generation FEC codes, suitable for 100G and beyond optical networks. Furthermore, the paper discusses the main advantages and drawbacks of each scheme and provides a qualitative categorization and comparison of the proposed schemes based on their main features, such as net coding gain (NCG) and BER. Information about the complexity of each scheme is given, as well. Index Terms Error Control Coding (ECC), Forward error correction(fec), 3rd Generation, Optical Networks, 100G, Survey. I. INTRODUCTION THE RISE of emerging applications like cloud computing, streaming video and social networks in the last few years has increased the Internet traffic significantly. To cope with this rise, many telecom operators had to increase the data rates of their optical networks considerably. However, the fact that the optical networks are often limited by several forms of noises, boosts the development and use of advanced Forward Error Correction techniques in modern Dense Wavelength Division Multiplexing (DWDM) communication systems. In more detail, FEC codes were initially used in optical networks to mitigate amplified spontaneous emission (ASE), a form of noise native in optical amplifiers, where the bit errors occur randomly. However, as transmission rates gradually upscaled, FECs had to perform under burst error conditions G. Tzimpragos is with the Department of Electrical and Computer Engineering, National Technical University of Athens and Athens Information Technology, Greece. getzim@microlab.ntua.gr, getzim@ait.edu.gr C. Kachris and I. Tomkos are with Athens Information Technology, Greece. {kachris, itom}@ait.edu.gr I. B. Djordjevic and M. Cvijetic are with the Department of Electrical and Computer Engineering of the University of Arizona, Tucson, AZ, USA. {ivan,milorad }@ece.arizona.edu D. Soudris is with the Department of Electrical and Computer Engineering of the National Technical University of Athens, Greece. dsoudris@microlab.ntua.gr The research leading to these results is partially supported by the ASTRON project (Adaptive Software-defined Terabit Transceiver for flexible Optical Networks) with funding from the European Community s Seventh Framework Programme [FP7/ ] under grant agreement n and combat additional optical impairments, such as non-linear effects, uncompensated chromatic dispersion and polarization mode dispersion [1]. Moreover, along with the growth of optical networks, economics imposed the development of powerful electronic end-to-end processing mechanisms, which are primarily based on strong FECs, in order to enhance optical-transparency [2]. Hence, FEC systems with different transmission overhead, implementation complexity, codinggain, BER-performance, burst-error correction ability and error floor (phenomenon, where there is a point after which FEC s performance flattens suddenly) are available in today s market. Thus, the most recent 3rd generation FEC codes are developed aiming to provide a Net Coding Gain, greater than 9.6dB at post-fec BER of 10 12, in order to achieve the same quality for 100G networks as that of 40G systems using a Reed- Solomon (255,239) code [3], [4]. Our goal in this paper is to provide an overview of the characteristics of FEC codes, analyze the key parameters and advantages/drawbacks related to analyzed coding schemes, as well as the key challenges and directions in their future employment. Hence, we outline key references used in our analysis as well as ones that will help the reader to follow up this topic in references providing detailed treatment of advanced topics in optical communications, such as [5]. Additionally, this paper aims at going beyond existing bibliography, such as [1], [2] and [4], by presenting current state-of-theart advanced FEC schemes (including solutions both from industry and academia), providing a qualitative categorization and comparison between them and pointing out the challenges and possible directions with their implementation. The paper is organized as follows: Section II, provides the reader with information about all the principal aspects of Error Control Coding (ECC) and Forward Error Correction. Section III presents the evolution of FEC codes and briefly discusses the main features of each generation. Section IV describes the main state-of-the art codes that have been proposed recently both by academia and industry. Section V depicts the taxonomy of these codes and provides a qualitative comparison based on the benefits and drawbacks of each scheme. Finally, concluding remarks are given in Section VI. Overall, the main contributions of this paper are the following: A review of the key features of the 3rd Generation FEC codes for next generation optical networks, a taxonomy and categorization of the most recent proposed schemes both by academia and industry, and a qualitative comparison of the proposed schemes based on their main features.

2 2 We should mention that the advanced FEC methods can be combined with the advanced modulation formats to perform these functions simultaneously in so-called coded-modulation schemes. However, the purpose of this survey is to analyze and compare the features of the FEC schemes, while coded modulation methods will be analyzed separately. II. BACKGROUND Error control coding (ECC), is a discipline of Information Theory, introduced by Claude Elwood Shannon in 1948 [6]. In his landmark paper, Shannon showed that channel noise limits the transmission rate, not the error probability. Hence, it is possible to design an error-free communication system using error control coding, where there is a maximum rate at which data can be transmitted over a noisy communication channel of a specified bandwidth without errors. ECC aims at developing methods for coding to achieve the detection of errors and the reconstruction of the original error-free data. Figure 1 shows the block diagram of a data transmission system, where the channel encoder and decoder blocks are responsible for the encoding and decoding of the transmitted and received data sequence, respectively. Shannon s contribution was to prove the existence of such codes and therefore it was the starting point of the study of error control coding. Since then much research has been devoted to the optimization of encoding and decoding methods for error control in noisy environments. code-symbols fall into the same codeword, until a decision is made to switch to the next codeword. Therefore, the resulting codewords may have unequal lengths [7]. Another distinction of FEC codes is between Hard-Decision (HD) and Soft-Decision (SD). The difference between Hard- Decision and Soft-Decision lies in the number of input bits per symbol required for decoding. HD decoding is performed with the use of a single quantization level for the bit sampling, whereas for the SD detection 2 N 1 decision thresholds are set (N is the number of quantization bit). These intermediate levels between 0 and 1 indicate the reliability of a decision and provide a sign of how far the signal is from the threshold crossing (Figure 2). In others words, even with as few as 8 evenly distributed quantization levels, the latter approach exhibits roughly a 1-2 db coding-gain advantage over the hard-decisions (Table II). Nonetheless, soft-decision receivers are not commonplace in optical communications, because of technological complications related to the very high transmission rates of these networks, the high processing complexity of soft-decision codes and the cost of the required Analog-to- Digital (A/D) converters. '1' Threshold0 High confidence Moderate Low '0' 1 2 Low Moderate High confidence Fig. 2. Hard-Decision vs Soft-Decision decoding. A bipolar signal constellation is assumed. The number of quantization levels refers to the sampling of the received filtered signal and affects the code s correcting performance. Fig. 1. Block diagram of a data transmission system. One of the most widely used error control methods is Forward Error Correction. Just like most of the error control methods, the main idea behind FEC is to add some redundancy to the original message, which receivers can use to check the consistency of the delivered message and to recover the corrupted data. In that way though, a part of the effective transmission bit-rate is limited. Thus, a key metric for these codes is the Code Rate R, which expresses the ratio of bit rate without FEC to bit rate with FEC (R = k/n, for every k bits of information, n bits of data will be sent, of which n k are redundant). In general, FEC can be categorized into block, convolutional and a combination of these codes. To be more specific, FEC codes with finite- and constant-length codewords are called block-codes. Codewords of length n are formed by associating n k parity code-symbols with k input code-symbols. On the other hand, convolutional codes apply over input-data in a continuous manner. Therefore, the concept of codewords is not as straightforward in this case. To be more specific, input The performance of a digital lightwave system is characterized through the bit-error-rate (BER). Although the BER can be defined as the number of errors made per second, such a definition makes the BER bit-rate dependent. It is a customary to define the BER as the average probability of incorrect bit identification. Therefore, a BER of 10 6 corresponds to on an average one error per million bits [8]. Additionally, the performance of a data-transmission code used on an additive white Gaussian-noise channel is expressed in terms of the probability of channel symbol error as a function of E b /N 0 of the channel waveform. Convention requires that E b is the average energy per data bit, whereas N 0 denotes the noise power spectral density (E b /N 0 is independent of data rate and bandwidth). It is common to judge the code, not by the reduction in the bit error rate, but by the reduction in the E b /N 0 needed to ensure the specified bit error rate. The reduction in the required E b /N 0 at the same bit error rate is called the coding gain. For example, a simple binary communication system on an additive white Gaussian-noise channel using the bipolar signal constellation operates at a bit error rate of 10 5 at an E b /N 0 of 9.6 db. By adding a sufficiently strong code to the communication system, the ratio

3 Bit Error Rate (BER) Capacity limit for rate R 3 E b /N 0 could be reduced. If the code requires only 6.6 db for a bit error rate of 10 5, then we say that the code has a coding gain of 3 db at a bit error rate of 10 5 (Figure 3) [9]. The difference between coding gain and Net Coding Gain (NCG) lies in the fact that the latter also takes into account the fact that the bandwidth extension needed for the FEC scheme is associated with increased noise in the receiver. For example, if there was a 7% rate expansion due to the FEC, the data rate had to increase by 7% in order to transmit both the data and the FEC [10]. FEC codes and Optical Transport Network (OTN) standards in [7] [12]. III. FEC CODES EVOLUTION In this section the progress from first generation methods to modern FEC schemes is briefly outlined. Generally, FEC codes are classified in 3 generations and coding gains of approximately 6dB, 8dB and greater than 10dB characterize them respectively. Figure 5 [13] depicts the FEC evolution over the years and Table I [14] indicates their application fields Coded Uncoded E b / N 0 (db) Fig. 3. Illustration of the notion of coding gain. NCG = 3 db (output BER 10 5 ) TABLE I TYPICAL FECS USED IN OTN. Short-Reach Regional Long-Haul 2.5G G.709 or None G.709 or None G G G.709 or None G nd-Gen G nd-Gen 40G G.709 2nd- or 3rd-Gen 3rd-Generations 100G G.709 3rd-Generations Soft FEC(18-22%OH) As already mentioned, emphasis is given in this paper to 3rd-generation FEC codes with high correction abilities, corresponding to the needs of next-generation optical networks. In high data rate optical communication systems, the challenge is to implement codes with low redundancy that are capable of correcting random and burst errors due to noise, dispersion and inter-channel cross talk, with attention to complexity and cost. Furthermore, the Q-factor (the logarithmic value of Q) is somewhat proportional to the optical signal-to-noise ratio (OSNR) P[ε] for= ap[v(t) binary > γ optical v S = v L ] P[v communication S = v L ] + system, as Table II [15] provides further information about the diversity P[ε] = P[v(t) > γ v S = v L ] 0.5 evidenced by the following equation Q(dB) = OSN R + in overhead and achieved Net Coding Gain (NCG) for both P[v(t) < γ v S = v H ] P[v S = v H ] (13) 10log(B 0 /B c ), where B 0 is the optical bandwidth of the Hard-Decision + P[v(t) < and γ vsoft-decision S = v H ] 0.5 decoding schemes. A brief end device where andp[ε] B c is the probability electricalof bandwidth error P[x of the y] receiver description of each code generation follows as well. 1 γ filter. Therepresents form ofthe theconditional Q-factorprobability is also given of x given by the y. If equation = PROB v t σ L dt Q = (V we H Vfurther L )/(σ assume H +σ L ) an (Figure equal probability 4). Provided of sending 2 [ ( ), ] that the noise TABLE II v follows Gaussian L versus v statistics, H (50% mark density), then P[v the Q-factor relates S = v with L ] the BER via the following relationship BER = erfc(q/ = SHANNON S 1 P[v S = v H ] = 0.5. Using this assumption, equation + THEORITICAL LIMITS FOR HD AND SD DECODING PROB v t σ H dt (13) can be 2)/2 [ ( ), ALGORITHMS. ] (14) exp( Q 2 /2)/(Q 2 γ reduced to: 2π). Overhead HD SD Additonal NCG where PROB[v(t),σ x ] is defined in equation (12). This result is illustrated 7% in Figure 10dB dB 1.10dB 15% 10.95dB 12.20dB 1.25dB v(t) From Figure 3 and 25% equations 11.60dB (13) and (14) 12.90dB we can 1.30dB conclude that the probability of error is equal to the area under the tails of the density functions that P[v(t) v S = v H ] extend beyond the threshold, γ. This area, and thus the bit First-generation error ratio (BER), FEC: is determined It usesby conventional two hard-decision v(t) =Signal + Noise factors: block (1) the codes, standard suchdeviations as Hamming, of the noise BCH (σ L (Bose, Chaudhuri, and and σ H ) and (2) the voltage difference between v σ L H v Hocquenghem) and Reed-Solomon(RS) codes. RS codes [16], H and vwhich H. are the most common representatives of this era, are It is important Maximum to note Distance that for Separable the special case (MDS), when suitable to mitigating γ σ L = burst-form σ H, the threshold errors is halfway due to between their nonbinary the low structure. RS(255, and high 239) levels codes (i.e., (each γ = codeword (v H v L )/2). contains But, for the 255 code word bytes, of σ L v L more which general 239 case bytes when are σ L data σ H and, the 16optimum bytes are parity) have been threshold recommended for minimum for BER long-haul will be higher optical or lower transmission as defined than (v H v L )/2. P[v(t) v S = v L ] by ITU-T G.709 [17] and G.975 recommendations [18] on In order their to use solve for equation optical (14) submarine we need a communications. practical These codes PROB[v(t)] way to were compute successfully the result of used the integrated trans-pacific Gaussian and trans-atlantic pdf ( communication PROB[v(t),σ x ] ) that systems is defined and in provided equation data rates as high as (12). Since there is no known closed form solution Fig. 4. Probability of error for binary signaling. 5Gbit/s [13]. This code generation is generally expected to to this integral, it must be evaluated numerically. To P[v(t) > γ v S = v L ] maintain yieldcompatibility a coding-gain with near existing 6 dbnumerical at an output BER of 10 12, Interested readers can find further introductory material on solutions, as evidenced equation (12) by performance can be re-written evaluation in its under ITU-T G.709. equivalent standardized (zero mean and standard deviation of one) form. In order to convert to the γ standardized form, we use the well known z = (x µ)/σ substitution, where x = v(t) and µ = v S in

4 4 This approach is necessary for any standards-compliant OTN framer but is not suitable for high data rates and longer reach applications, due to its limited correcting performance. Second-generation FEC: Besides hard-decision based algorithms, second-generation FEC codes achieve better coding gain with the use of concatenated codes alongside interleaving, iterative and convolutional decoding techniques. The concatenation scheme is based on the idea of increasing the Hamming distance by forming inner and outer loops in the coding scheme and can be done in either a serial or parallel way. Namely, if the inner code loop has the minimum distance d, the inner encoder, the channel, and the inner decoder can be considered as elements of the inner loop, and as such subject to the outer encoder/decoder. If the outer encoder enabled the minimum distance D, the concatenated scheme results in the minimum distance of at least D d. This improvement allows technology to support 10G and even 40G transmission systems [19]. In many cases, second-generation FECs yield a net coding gain higher than 8 db at an output BER equal to Various Enhanced FEC (EFEC) techniques built for higher gain found their way to standardization as ITU- T recommendation G in 2004 [20]. G describes nine techniques (I.1 through I.9), which can be used in transponders, regenerators, muxponders and switches at OTU- 2 (10G) and OTU-3 (40G). However, equipment deployed at OTU-4 (100G) must properly utilize advanced FEC techniques [21]. Third-generation FEC: The use of coherent detection in optical communication systems and the rapid growth in integrated circuit technology make the application of Soft- Decision FECs possible. While the mathematics behind softdecision FEC algorithms have been known for many years and these codes are already popular in the wireless industry, they are not yet widely used in optical communications. The main reason for their limited use in optical networks is that until recently numerous technology and ASIC (Application-Specific Integrated Circuit) limitations prevented their widespread hardware implementation. In other words, the computational intensive nature of these codes and the technological constraints of the past did not allow the realization of such schemes for the very high transmission rates of optical networks. Another inhibiting factor was the unavailability of the required Analog-to-Digital (A/D) converters. The A/D converters appeared after the introduction of coherent detection systems and still remain costly. However, as micro-electronic technologies advance, research matures and new digital coherent receivers that integrate A/D converters as a front end for demodulating signals are developed, it is becoming more and more reasonable to consider SD-FEC codes a rising and promising solution for next generation optical networks [22]. Thus, in recent years intensive research has been conducted towards iterative soft-decision decoding of various codes, seeking the highest possible coding gain. It should be noted here that the real-time character of optical networks requires that the algorithm should be terminated after a fixed properly chosen number of iterations (a higher number of decoding iterations lead to lower throughput and larger delay). A SD-FEC scheme with 20% overhead is generally expected to provide a net coding gain of over db at a output BER. Therefore, solid support is given to ultra long-haul transmission of 40G, 100G, and even 400G data. According to the most of the existing bibliography, the 3rd generation of FEC codes includes only SD-FECs. Up to date state-of-the-art methods are mainly based on either Turbo or Low-Density Parity-Check (LDPC) coding concepts and iterative decoding. However, considering the fact that the codes are usually judged for effectiveness based on their net coding gain, it should be noted that there are some HD-FEC codes that although their correcting performance is inferior compared to this of SD-FECs, they are still suitable for 100G systems (they can be classified as 2.5th generation). NCG-Bit rate product (Gb/s) (Defined at post-fec BER 10E-15) HD FEC BCH, RS 2.5G OH < 7% Gain < 8 db FPGA (0.1 M LUTs) HD FEC Concatenated, iterative 10G OH < 7% Gain: 8-9 db FPGA & 65 nm ASIC (< 5M Gates) SD FEC Iterative decoding 100G+ OH: up to 20% Gain> db 40 nm ASIC (15M Gates) Fig. 5. FEC evolution for optical networks. IV. STATE-OF-THE-ART FEC CODES FOR NEXT GENERATION OPTICAL NETWORKS Year In current and next generation optical communications very powerful FEC codes are essential to enhance the transmission reach. A minimum post-fec BER of or preferably is generally required. Currently, the most popular schemes for FEC codes targeting 100G systems are based on Turbo, LDPC and interleaved-concatenated coding concepts. We note that the construction of FEC codes has been a highly active research area for a very long time and therefore we will describe only the most recent and efficient codes available in the open literature. Information about the status of commercialization, patented solutions and the relative academic research is provided as well. A. Two-iteration Concatenated BCH code: The described concatenated BCH code [23] consists of an outer BCH(3904,3820) and an inner BCH(2040,1952), and has approximately 6.81% redundancy. On this decoder a low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversionless Berlekamp-Massey key equation solver architecture is applied. High throughput, low complexity and high correction ability are achieved with the use of block interleaving methods and

5 5 the development of the two-parallel processing method by converting the frame format. The two-parallel architecture needs the frame converter in order to parallelize two serial frames at input and output port of the two-iteration concatenated BCH decoder. Additionally, in order to keep the hardware complexity low the number of iterations was selected to be two, since the two-iteration scheme requires a lower number of inner and outer decoders as well as interleavers/deinterleavers than the three-iteration scheme. Figure 6 depicts a block diagram of the described two-iteration concatenated BCH scheme that consists of BCH encoders, BCH decoders and interleavers/deinterleavers. use the shortened bits for further checks. As regards its hardware implementation, the algorithm used for the decoding of the individual BCH codes takes advantage of the property that the shift of a BCH codeword is also a codeword. Therefore, for a codeword of length n, n rounds are required to get the decoding result. Interested readers can find more information about this code s implementation complexity in [24]. Fig. 7. Turbo product code structure. Fig. 6. Concatenated BCH Super FEC block diagram. From post-layout simulation, the achieved NCG is 8.91dB at an output BER of and the latency is 11.8 µs. The maximum clock frequency at which this architecture can operate is 430MHz in 90-nm CMOS technology and the data processing rate is 110 Gb/s. The total number of gates and area usage for the proposed two-iteration concatenated BCH decoder are 1,928,000 and 6.3mm 2 respectively, excluding the RAM used in the interleavers/deinterleavers, frame converters and FIFOs. The required memory size for the two-iteration concatenated BCH decoder is approximately 155kbytes including all FIFOs, 2 frame converters, 1 interleaver and 2 deinterleavers. B. Turbo Product Code with shortened BCH component codes: The HD-based Turbo Product Code scheme, proposed in [24], has an overhead of 20% as recommended by OIF (Optical Internetworking Forum) and achieves 10dB NCG after 8 iterations. Its structure is shown in Figure 7. For its construction, shortened BCH(391, 357) component codes in GF (2 11 ) are used. In each BCH component code, the first 1656 bits are fixed to 0 s, the middle 357 bits are information bits and the last 34 bits are parity check bits. The product code is then shortened by removing all fixed 0 s and this returns a product code with shortened BCH component codes. For the decoding, each shortened component code aims to correct up to 3 errors. During one iteration both rows and columns are decoded once. The standard procedure for the component code decoding algorithm consists of three steps: restore the BCH code, decode BCH code, and C. LDPC-Based Codes: In coding theory, a parity-check matrix of a linear block code C is a matrix which describes the linear relations that the components of a codeword must satisfy. If the paritycheck matrix has a low density of 1 s and the number of 1 s per column (w c : column weight) and per row (w r : row weight) are both constant, the code is said to be a regular Low-Density Parity-Check (LDPC) code. If the parity-check matrix has low density, but the number of 1 s per row or column varies, the code is said to be an irregular LDPC code. The code rate R is given by the following equation: R = (n m)/n = 1 w c /w r. The graphical representation of LDPC codes, known as bipartite (Tanner) graph representation, is helpful in efficient description of LDPC decoding algorithms (Figure 8). A bipartite (Tanner) graph is a graph whose nodes may be separated into two classes (variable and check nodes), and where undirected edges may only connect two nodes not residing in the same class. The Tanner graph of a code is drawn according to the following rule: check (function) node c is connected to variable node u whenever element h cu in a parity check matrix H is an 1. In an m n parity-check matrix, there are m = n k check nodes and n variable nodes. A closed path in a bipartite graph compromising l edges that closes back on itself is called a cycle of length l. The shortest cycle in the bipartite graph is called the girth. The girth influences the minimum distance of LDPC codes, correlates the extrinsic log-likelihood ratios (LLRs) and, therefore, affects the decoding performance. Hence, the use of large girth LDPC codes is generally preferable. The iterative schemes used for their decoding engage passing the extrinsic information back and forth among the check and the variable nodes over the edges to update the distribution estimation. Conventionally, the sum-product algorithm (SPA) [25] or the modified minsum algorithm (MSA) [26] is used. However, layered LDPC

6 6 decoding schemes have recently attracted much attention in both academy and industry because they can effectively speed up the convergence of LDPC decoding and thus reduce the required maximum number of decoding iterations. At present, two kinds of layered decoding approaches have been proposed: row-layered decoding [27] [30] and column-layered decoding [30] [32]. In row-layered decoding, the rows of the parity check matrix are grouped into layers and the message updating is performed row layer by row layer, whereas in columnlayered decoding this matrix is partitioned into column layers and the update happens column layer by column layer. H = Variable nodes v o v 1 v 2 v 3 v 4 v 5 c o c 1 c 2 c 3 Check nodes Fig. 8. H-matrix and its corresponding Tanner graph. Rate R = (6 4)/6, row weight w r = 3, column weight w c = 2. LDPC codes and especially Quasi-Cyclic LDPCs (QC- LDPC) seem to be strong candidates for SD-FEC codes in next generation optical networks, due to their efficient parallelization and low complexity (required for 100G and beyond optical communication). Despite their advantages, these codes have a major drawback, which is the appearance of error floor. Thus various approaches have been proposed for the elimination of this phenomenon. Figure 9 depicts three different ways (no code concatenation, regular concatenation, triple concatenation) of using LDPC codes for the construction of FEC frames suitable for 100 Gb/s digital coherent systems, with a 20% overhead, as recommended by the OIF. Fig. 9. Types of FEC frame structure, including LDPC codes, for 100 Gb/s digital coherent systems. Figure 9a shows a single 20% LDPC implementation. In that case, while a good performance is expected, the effort to eliminate the error floor usually leads to very long codewords, resulting in large circuits with high latency. Especially for implementations according to the OTU4 framer, huge interconnection speed between the OTU4 framer LSI and the coherent ASIC is required [33]. Recently, D. Chang et al. [34] and D. A. Morero et al. [35], [36] have made significant progress in the development of efficient single/non-concatenated LDPC codes with low error floor and tolerable latency. In more detail, Huawei s D. Chang et al. proposed in 2011 a nonconcatenated girth-8 QC-LDPC(18360, 15300) code exceeding a net coding gain up to 11.3dB, Q-limit of 5.9dB and no error floor at a post-fec BER of Influenced by the compromise of performance and complexity, w c = 4 (column weight) and w r = 24 (row weight) were selected. Moreover, progressive edge growth (PEG) algorithm was used for the search of high girth QC-LDPC codes. Thanks to the use of modified offset min-sum decoding algorithm with multithresholds and modified layered decoding algorithm with 4 quantization bits the implementation complexity was kept low [34]. Additionally, D. A. Morero et al. presented a nonconcatenated QC-LDPC code with a standard 20% or better overhead providing a net effective coding gain greater than 10dB at a BER of In [35], [36] a design method of parity check matrices with reduced number of short cycles, a parallel decoder architecture and an adaptive quantization post-processing technique are described. Besides these codes, large girth block-circulant LDPCs with 20% redundancy were presented in [37], providing a net effective coding gain of 10.95dB at post-fec BER of 10 12, whereas Q. Yang et al. showed in [38] an error free beyond 1 Tb/s QC-LDPCcoded 16-QAM CO-OFDM transmission over 1040km standard single-mode fiber and proved its better performance compared to common 4-QAM transmission. However, the routing congestion problem and the increase of the global wiring overhead (due to the feedback-loop architecture of an LDPC block code (LDPC-BC) decoder) should still be considered for the implementation of such long codes (both of them limit the clock frequency and require larger space and power consumption than the initial estimation). Nevertheless, these two implementation drawbacks can be overcomed with the use of LDPC convolutional codes (LDPC-CCs). As can be seen in [39], the LDPC-CCs are suitable for pipelined implementation and additionally their coding performance is similar to this of longer LDPC-BCs. To be more specific, the LDPC-CC(10032,4,24) achieves a Q-factor of 5.7dB and a NCG of 11.5db at a post-fec BER of 10 15, as proved by FPGA (Field-Programmable Gate Array) emulation (the maximum number of iterations was set to 12). Figure 9b presents another way to supress the unwanted error floor by concatenating a SD-FEC with a HD code. In their paper [40], T. Mizuochi et al. presented the concatenation of LDPC(9216,7936) and RS(992,956) codes, achieving a NCG of 9db at with only 2-bit soft-decision and 4 iterations. In order to guarantee low circuit complexity and high error correction performance, cyclic approximated δ- minimum algorithm is proposed for the decoding procedure. The value of row and column weight is 36 and 5, respectively, whereas the girth of the LDPC code is 6. Under this concept, another high-performance low-complexity approach

7 7 based on LDPC codes are the Concatenated QC-LDPC and SPC Codes, introduced by N. Kamiya and S. Shioiri (NEC Corporation) [41]. The construction of these codes rely on the concatenation of single-parity check (SPC) codes and QC-LDPC codes of shorter lengths. According to the OTU4 framer, an implementation with 20.5% OH is proposed. The expected Q-limit and NCG of these codes, with 4 quantized bits and 15 iterations are 5.8 db and 10.4 db at a BER of ( NCG=11.3 db at a BER of ), respectively. Naturally, a small degradation in the performance is noticed with the reduction in the number of quantization levels or in the maximum number of iterations. Spatially-coupled codes is another class of LDPCs, which can be derived from QC-LDPC design [42]. Numerical simulation (Monte Carlo simulation in an additive white Gaussian noise channel with QPSK modulation) [43] indicate a NCG of 12.0 db at a BER of achieved by the code concatenation of spatiallycoupled type irregular LDPC(38400, 30832) and BCH(30832, 30592), when the number of iterations was set to 32. This scheme has a 25.5% redundancy and for its decoding the simplified δ-min algorithm with 4 soft-decision bits was used. Another promising FEC scheme for 100Gb/s Optical Transport Systems is the recently presented Concatenated Non-Binary LDPC and HD-FEC Code [44]. The proposed concatenated NB-LDPC(2304,2048) over GF (2 4 ) and RS(255,239) is compatible with OTU-4 frame structure and can provide a NCG performance over 10.3 db at a post-fec BER and over 10.8 db with enhanced HD-FEC in the outer code, with the number of maximum iteration limited to 16. As far as its architecture modeling is concerned, between NB-LDPC and RS codes 2D-interleaving/deinterleaving buffers are located and Min-Max algorithm is preferred for decoding due to its advantageous VLSI implementation compared to FFT-BP algorithms. Figure 9c illustrates the concept of the so-called tripleconcatenated FEC [45] [48]. Unlike conventional concatenated codes, the proposed one combines an inner LDPC code with a pair of concatenated hard decision based block codes having 7% redundancy. The expected net coding gain at a output BER is 10.8 db. Generally, these codes are characterized by the following: Inner Codes: Irregular QC-LDPC(4608,4080) 20.5% total redundancy compliant with OIF standards, which results in a transmission rate of Gb/s. an OTU4V frame format compliant with ITU-T G.709. Decoding algorithm: Variable Offset Belief Propagation 16 iterations straightforward circuit implementation via a well designed parallelized pipelined architecture. Recently, nonbinary approaches are also attracting more and more attention. These codes are designed over higherorder fields and achieve coding gains similar to or even better than binary LDPC codes, but for shorter codeword lengths [49], [50]. The higher performance of Nonbinary LDPC (NB- LDPC) codes in comparison to binary ones was at first demonstrated by Davey and Mackay in [51] and [52]. The main factors that led to improved performance are the reduced probability of forming short cycles when compared to their binary counterparts and the increased number of nonbinary check and variable nodes, which ultimately improves the achievable decoding performance. Their main drawback though, is that they are characterized by increased decoding complexity, due to the large number of values [53]. For the construction of NB- QC-LDPC codes firstly finite fields are used for the generation of a large girth parity-check matrix for binary QC-LDPC and then with the application of certain design criteria non zero elements from the Galois field GF(q) replace the 1 s. With the use of these codes (20% overhead) a net effective coding gain of 10.8 db at a post-fec BER of can be achieved [49]. Furthermore, in most recent publications, e.g. [54], NB-QC-LDPC based coded modulation schemes are presented. Compared to binary interleaved LDPC based coded modulation, the non-binary scheme provides higher coding gains and is advantageous due to the reduced system s complexity and latency. In more detail, nonbinary LDPCcoded modulation provides several advantages compared to binary counterparts, when decoding is based on modified FFTbased q-ary SPA (MD-FFT-QSPA), as shown in [55]. Namely, with MD-FFT-QSPA, the trade-off between the computational complexity and coding gain improvement can be adjusted to suit the needs of the system under consideration. This particular scheme is also suitable for rate adaptation. D. Staircase Codes: B. P. Smith et al. presented in their paper Staircase Codes: FEC for 100 Gb/s OTN [56] a new class of high-rate binary error correcting codes, whose construction combines ideas from recursive convolutional and block coding. These codes are characterized by the relationship between successive matrices of symbols and can be interpreted as generalized LDPC codes with a systematic encoder and an indeterminate block length, which admits decoding algorithms with a range of latencies. The low latency of their encoding process is guaranteed by the use of a frame mapper, whereas a range of strategies with varying latencies can be used for their decoding due to the fact that these codes are naturally unterminated (i.e. their block length is indeterminate). That is, their decoding can be accomplished in a sliding-window fashion, in which the decoder operates on the received bits (binary case) corresponding to L consecutively received blocks B i, B i+1...b i+l, (B i denotes an m-by-m matrix with elements either in GF(2) (binary case) or in Galois fields of higher orders (non-binary case)). A more detailed explanation of the encoding and decoding of these codes is provided in [56]. Generally, the relationship between successive blocks in a staircase code satisfies the following relation: for any i >= 1, each of the rows of the matrix [B T i 1, B i] is a valid codeword. Figure 10 represents a Staircase visualization of staircase codes, in which the concatenation of the symbols in every row and every column in the staircase is a valid codeword. The expected NCG from the proposed ITU-T G.709- compatible staircase code, with rate R = 239/255 is 9.41dB at an output error rate of as evidenced by a FPGA-based simulation.

8 1 I.B. Djordjevic is with Department of Electrical and Computer k z Engineering, University of Arizona, 1230 E. Speedway Blvd., n x RS code RS code 2 z Tucson, Arizona, , USA. ivan@ece.arizona.edu 1 2 L. Xu, and T. Wang are with NEC Laboratories America, Fig. 10. The Staircase visualization Princeton, NJ of staircase codes. Fig. 1. A multidimensional TPC codeword example This paper was supported in part by the NSF under Grant IHCS- Fig. 11. A 3-dimensional TPC, with RS component codes The different options to perform encoding/decoding can be classified as: (i) serial, (ii) parallel, and (iii) partially parallel. E. Multidimensional TPCS and GLPDC Codes with Components RS Codes: the GLDPC code. Each sub-matrix H j is derived from H 1 by U.S. Government work not protected by U.S. copyright random 402 permutations π j 1 as given by Eq.3. In Multidimensional Turbo Product and Generalized LDPC Codes with Component RS Codes Suitable for use in [H1 T,..., HW T ] T (1) Beyond 100 Gb/s Optical Transmission paper [57], two harddecision decoding FECs suitable for next generation optical networks are presented. The first scheme is based on mul- 0 H1 MT P C 0 0 H 1 = H MT P C tidimensional turbo product codes (MTPCs) with component.. (2) Reed-Solomon (RS) codes and the second one is based on HN MT P C t/n generalized low-density parity-check (GLDPC) codes with component RS or MTPC codes. H j = π j 1 (H 1 ), j = 2,..., W (3) The multidimensional turbo-product codes (MTPCs) are a generalization of the original turbo-product codes. The various methods to perform their encoding and decoding are divided in the following three categories: serial, fully parallel, and partially parallel. forward error correction (FEC) scheme suitable for beyond 100 Gb/s transmission and 100Gb/s Ethernet is of high importance [1],[2]. The soft iteratively decodable codes [1]-[7], turbo-product codes (TPCs) and LDPC codes, are excellent candidates for use in high-speed optical communications. Although those schemes provide excellent performance improvement, they require soft bit reliabilities, and as such are still not implementable at data rates above 100 Gb/s. Given the lack of A/D converters operating at data rates 100 Gb/s, we propose two FEC schemes: (i) the FEC scheme based on multidimensional TPCs (MTPCs) with component Reed- Solomon (RS) codes [8], and (ii) the generalized LDPC (GLDPC) codes with component codes being either MTPCs or RS codes. These schemes operate on hard decisions only, In serial version, only three different encoders/decoders are needed, each performing encoding/decoding in corresponding dimension. The encoding/decoding latency of this scheme is high, but the complexity is low. In fully parallel implementation, we need n y n z encoders/decoders performing the encoding/decoding in x-direction, n x n z encoders/decoders performing the encoding/decoding in y-direction; and n x n y encoders/decoders performing the encoding/decoding in z- direction. The encoding/decoding latency of this scheme is low, while the encoding/decoding complexity is high. Thus, the partially parallel scheme was finally proposed for implementation, as a middle ground solution between these two schemes. The three-dimensional (3D)-TPC of rate 0.8, based on (255,237) RS code as a component code, provides the net effective coding gain of 9.3 db at BER of and is also very efficient in dealing burst of errors due to intra-channel nonlinearities. An example of 3-dimensional TPC, with RS component codes, is shown in Figure 11. The GLDPC codes are either constructed using MTPC or RS components for less complex designs. The parity-check matrix H of a Boutros-like nonbinary GLDPC codes can be partitioned into W sub-matrices H 1,..., H W (Eq.1). H 1 is a block-diagonal matrix generated from an identity matrix by replacing the ones by the parity-check matrices Hi MT P C of the constituent MTPCs of codeword-length N and dimension K i, i=1,2,...,n t /N (Eq.2). N t denotes the code word length of 1 2 D 1 2 D n 1 xn 2 xxn D array such that ith dimension code word is obtained from an (n i,k i,d i ) code C i. With n i, k i and d i (i=1,2,,n) we denoted the codeword length, dimension and minimum distance, respectively, of i th component code. An example of 3-dimensional TPC, with RS component codes, is shown in Fig. 1. x 1 2 k x 1 y 2 k y n y Layer k 2 RS code RS code RS code RS code Layer 1 RS code Layer n z Layer k z n z The GLDPC code of rate 0.82, based on (255,239) and (255,223) RS codes as components provides the net effective coding gain of 9.6 db at BER of Interested readers can find more information about how these schemes are implemented and can be used along with multilevel modulation formats in [57]. F. Super-Product BCH: The super-product BCH (SP-BCH) code [58] is a true product code designed for OTU4 100 G applications and was originally introduced by Broadcom Corporation. It has a standard 7% overhead and is based on hard decision decoding. The code consists of 960 BCH(987,956, t=3) (1-bit extended) codes as row codes and 987 BCH(992, 960, t=3) (2-bit extended) codes as column codes. The most likely dead pattern is the 4x4 square error pattern shown in Fig. 12, where 16 bit errors are located in the cross points between 4 arbitrary row codes and 4 arbitrary columns codes. A maximum number of 7 iterations are allowed at the decoding procedure. Due to an advanced decoding method used for its decoding, called dynamic reverting, it is expected to provide a net coding gain up to 9.4 db for an output BER of The proposed code seems to have advantages, such as lower computational complexity, better burst error correction capacity and less required maximum iterations compared to other super FEC schemes [20]. However, its main drawback is that it has a long decoding latency due to large block size. G. CI-BCH: CI-BCH stands for Continuously Interleaved BCH and was introduced by Vitesse Semiconductor Corp in 2010 [59]. It is an enhanced HD based FEC (efec) code relying on 8

9 9 992 bits Row code 0: BCH(992, 960) Row code 1: BCH(992, 960) bits bits Row code 955: BCH(992, 960) 31 bits C-0 C-1 Parity bits of column codes C-990 C-991 Fig. 13. UEP-BCH FEC Frame Structure. Fig. 12. SP-BCH Structure. interleaved BCH(1020,988) codewords and originally, it has a standard 7% redundancy. Due to its structure, it is able to handle up to 1500 consecutive burst errors. Moreover, it is characterized by low complexity decoding, as no Chien search or matrix inversion techniques are used and flaring correction in most applications is not necessary. A net electrical coding gain, for bursty-error channel (not for AWGN channel model only), of 9.35 db and 10.5 db at output BER of is expected for 7% and 20% overhead respectively. The latency of the proposed codes varies from 1Mbits to 8Mbits (decoding latency in time is equal to the decode latency in bits divided by the OTN line rate), depending on the error correction capabilities of the used BCH components (3- and 4-error correcting BCH respectively) [60]. H. UEP-BCH: In 2012 Mitsubishi Electric Corporation proposed a novel HD-FEC based on an unequal error protection (UEP) BCH product code for OTU4 framers. Figure 13 [61] shows the suggested FEC frame format for the UEP-BCH product code. Their code consists of a BCH(1632,1588) x BCH(1280,1236) + BCH(1280,1225) with 7% overhead. According to simulations a Q-limit of 8.35 db and a NCG of 9.35 db for a post-fec BER of are expected, with no error floor [61]. Generally, an enhanced FEC (EFEC) scheme for 100 Gb/s OTN is a product code, constructed by two or more types of element code and uses iterative HD decoding. The encoding procedure of the proposed code succeeds in adjusting the codeword and payload length to fit OTU4 and is summarized in the following steps: use of a systematic code for wrapping by the OTUk Frame, removal of unequal parity-check bits, use of row-wise code as parity bits in order to reduce burst-error. I. Swizzle : PMC-Sierra introduced the Swizzle Spiral Interleaved Turbo Forward Error Correction code in order to provide an efficient hard-decision FEC code suitable for 40G and 100G DWDM systems. It offers 9.45dB of net efficient coding gain with a 6.7% OTN overhead, 1.35dB better than the second-generation FECs captured in G In addition to its great performance, the small overhead makes this solution appealing. It can correct up to a random BER of 4.8E-3, corresponding to 9.45dB of net effective coding gain(2048 consecutive errors at 40G and up to 6000 consecutive errors at 100G) and offers low latency. Its design is inspired by LDPC and the codewords interlace in a spiral pattern(figure 14 [14]), so that each codeword is covered by almost all the others nearby(maximum overlap of each pair of codewords is only 2 bits). This approach makes trapping sets rare and eliminates the error floor, while keeping the latency low. Moreover, it is characterized by tight interleaving, parallel decoding and the use of an intelligent scheduler to allocate decode resources. Fig. 14. Swizzle interleave. In 2011 PMC-Sierra published a white paper, called Swizzle FEC for 40G and 100G Optical Transmission [14], providing extended information about the construction and the performance of this code.

10 10 J. TPC FEC IP Cores: Viasat has developed and offers third generation FEC codes exceeding ITU-T G.709 and G.975 submarine standards for long haul (LH) and ultra long haul (ULH) link performance requirements, providing a net coding gain ranging from 9.3dB to 11.4 db at a output BER, depending on code type (HD or SD) and overhead (7%-20%). In accordance with their research [62], [63], TPCs are considered the most efficient FEC codes for 100G systems, because of the following features: high coding gain, high and deterministic minimum distance / excellent asymptotic performance / no error floors down to operational BERs, fast convergence/small number of decoding iterations leading to lower complexity and lower latency, and high tolerance to soft-input resolution, so few bits of ADC input resolution are required. As far as decoder s architecture is concerned, its top-level block diagram consists of a deinterleaver, a pre-processor, SISO iterations, and a post-processor. More specifically, the proposed decoder uses four copies of the SISO decoding engine and is built taking advantage of pipelined architecture and high parallelism. The decoding procedure terminates after four iterations, keeping latency and complexity low, while providing the required NCG. V. COMPARISON In the previous sections, not only we introduced the reader to error control coding and FEC codes, but also described their evolution and standardization through the years, and presented the state-of-the-art. In this section, we summarize the benefits and drawbacks of each scheme and provide a qualitative comparison between them. Table III forms a synopsis of the FEC codes described above and includes statistics about their Net Coding Gain, Overhead (OH), post-fec BER and the number of quantized bits in case of Soft-Decision decoding, whether they are available. Additionally, Figure 15 depicts this table for better understanding, where Hard-Decision based FECs are represented with circles and Soft-Decision based FECs with rhombuses. As already mentioned, all the included solutions target at 100G transmission and beyond. As far as post-fec BER is concerned, a minimum of or preferably is generally required. A first conclusion from this comparison is the confirmation of the greater correcting performance of SD-FEC codes. The SD-FECs take advantage of the additional confident bits provided by the A/D converters and manage to outperform the conventional HD-FECs. Such an improvement in NCG is very important since it gives us the opportunity to increase the un-regenerated optical propagation distance. In practice, the 1-2 db of coding gain translates into 20-40% rise in total achievable distances, which is a substantial improvement at 100Gps. However, this happens at the expense of resources as the SD-FECs are generally characterized by higher implementation complexity than HD-FECs. Hence, the hardwareefficient realization of such high-performance SD-FEC codes remains a hot topic for research [65], [66]. Despite their weaker performance, HD-FEC codes are still a reliable solution. As shown above, these codes meet the needs of 100G and beyond systems, typically have a smaller overhead and no costly A/D converters are required for their implementation. From this family of codes, the best NCG at a post-fec BER is provided by CI-BCH 4 with a 20% redundancy [59], [60] and Turbo Product code with shortened BCH component codes [24], whereas CI-BCH 4 (7% OH), Swizzle [14] and Staircase codes [56] achieve the greatest performance for a standard 7% overhead. From the class of SD-FEC codes, the spatially-coupled type LDPC code [43] exhibits the highest NCG at a post- FEC BER. However, its overhead is at least 5% higher than this of the other described FEC codes. LDPC-CCs [39] and Viasat s TPCs [62], [63] are the two implemented schemes with the greatest correcting performance with a 20% overhead at a post-fec BER of Some of the other proposed LDPC-based codes have also similar or even better performance (e.g. Large-Girth LDPC [37], [49] or Non-Binary QC- LDPCs [49], [64]), as evidenced by Table III, but they are not yet sufficiently implemented onto hardware. Especially for the case of Soft-Decision codes, besides coding gains, attention should be paid to both latency and complexity of the proposed schemes. These factors are implementation dependant and affect the delay and the power consumption of the system, thus they are considered critical. For this reason, LDPC and mostly QC-LDPC codes have recently started to attract more and more interest, as they come along with an efficient architecture and are characterized by parallelism in decoding and computational simplicity. Towards this direction, there is a high motivation to use single LDPCs with low error floor (e.g. [34] [36]), instead of concatenated codes. As compared to non-concatenated solutions, the latter brings on additional drawbacks, such as increased complexity and latency, since the concatenation scheme requires an outer code and an additional interleaver (deinterleaver) to de-correlate the data sequences between the component codes. However, the length of these single codes has to be selected carefully, considering both the elimination of the unwanted error floor and the routing and latency of the implemented design. Having this trade-off in mind non-binary approaches were recently proposed as they come along with an efficient hardware implementation and an effective integration with advanced modulation formats (coded-modulation) [54], [55]. Definitely, in the case of SD-based FECs another factor that should be considered is the number of quantization bits. Typically, an increase in the number of quantization levels leads to more expensive solutions, while we have noticed that their reduction causes degradation in the correcting performance. Considering this trade-off, SD-FEC codes with only 2 quantization bits, such as the one presented in [40], are in many cases a favorable solution. It should be also noticed here that the implementation of SD-FEC codes under this concept is possible even without the use of A/D converters by taking advantage of the softdecision optical front-end proposed in [67], [68], leading to low-power solutions.

11 11 TABLE III STATE-OF-THE-ART AND BEYOND FEC CODES COMPARISON Name Ref. HD SD Appr. Overhead NCG(dB) post-fec BER Implementation FPGA ASIC Swizzle [14] 6.7% NA Staircase [56] 7% NA MTPC [57] 20% NA NA GLDPC [57] 20% NA NA SP-BCH [58] 7% nm Two-iter. conc. BCH [23] 6.81% NA NA UEP-BCH [61] 7% NA 40 nm TPC with shortened BCH comp. [24] 20% > NA NA CI-BCH 3 [59], [60] 6.7%/12%/20% 9.35/9.90/ NA CI-BCH 4 [59], [60] 6.7%/12%/20% 9.55/10/ NA TPC [62], [63] 7%/15% 9.30/ nm TPC [62], [63] 7%/15%/20% 10.30/11.10/ nm Conc. QC-LDPC and SPC [41] 4 bits 20.5% 10.4/ /10 15 NA Single QC-LDPC [34] 4 bits 20% NA LDPC-CC. [39] 4 bits 20% NA Non-Conc. FEC [35], [36] 5 bits 20% 11, NA Conc. LDPC and RS [40] 2 bits 20% NA Spatially-coupled LDPC [43] 4 bits 25.5% NA NA Conc. NB-LDPC and RS [44] 5 bits 20.5% NA NA Large-Girth LDPC [37], [49] 4 bits 20% NA NA NB-QC-LDPC [49], [64] 20% NA NA Triple Conc. FEC [45] [48] 3 bits 20.5% NA VI. CONCLUSIONS AND FUTURE OUTLOOK In this paper we have provided a thorough survey of the associated open literature that is related to high-performance forward error correction codes suitable for next generation optical networks targeting 100G and above. We have commenced our discourse by outlining the fundamentals and the basic principles of error correction codes. Furthermore, we gave a historical overview of their progress, standardization and application fields. Following this preliminary foundation, we proceeded to provide a description of state-of-the-art FEC codes recommended both by academia and industry. Because different application systems have different decoding performance, latency, power and cost requirements, FEC systems with various transmission overhead, implementation complexity, coding-gain, BER-performance, burst-error correction ability and error floor are available in today s market or literature. Therefore, a qualitative comparison based on the main features of each scheme has been presented, analysing the tradeoffs in terms of coding gain, latency and implementation complexity between the described schemes and leading to useful conclusions about their suitability for use in various applications. As far as future challenges in this research area are concerned, the authors of this paper believe that emphasis should be given to the joint design of coding and advanced modulation format (so-called coded modulation) [69] [71]. The use of advanced modulation formats is a promising solution for attaining such high data rates in optical networks. However, as a signal constellation grows in size, so does the optical signalto-noise ratio it requires to achieve a certain bit error rate. Hence, the development of integrated solutions (e.g. irregular structured LDPC codes to further improve NCG) suitable to improve the spectral efficiency of these channels with less power requirements (for the same amount of redundancy and the same BER) will be greatly needed in the near future. Finally, considering the dynamic structure of next generation flexible networks [72], attention should also be paid to the hardware realization of these schemes both due to their high implementation complexity and the need to adapt effectively in different signal qualities, power requirements and expected transmission rates. REFERENCES [1] T. Mizuochi, Recent progress in forward error correction and its interplay with transmission impairments, Selected Topics in Quantum Electronics, IEEE Journal of, vol. 12, no. 4, pp , [2] B. Smith and F. Kschischang, Future Prospects for FEC in Fiber- Optic Communications, Selected Topics in Quantum Electronics, IEEE Journal of, vol. 16, no. 5, pp , [3] T. Mizuochi and Y. Miyata, LDPC-based advanced FEC for 100 Gbps transmission, in IEEE/LEOS Summer Topical Meetings, 2008 Digest of the, july 2008, pp [4] T. Mizuochi, Next Generation FEC for Optical Communication, in Optical Fiber communication/national Fiber Optic Engineers Conference, OFC/NFOEC Conference on, feb. 2008, pp [5] M. Cvijetic and I. B. Djordjevic, Advanced Optical Communication Systems and Networks. Artech House, [6] C. E. Shannon, A Mathematical Theory of Communication, The Bell System Technical Journal, vol. 27, pp , , July, October [Online]. Available: shannonday/shannon1948.pdf

12 12 Overhead (%) *post-fec BER 10E-15 *post-fec BER 10E-13 *post-fec BER 10E-12 HD-FEC SD-FEC MTPC Spatially-coupled LDPC NB-LDPC&RS Triple Conc. QC-LDPC&SPC CI-BCH4 Non-Conc. LDPC-CC LDPC&RS GLDPC TPC-SD CI-BCH3 Single QC-LDPC TPC - short BCH Large- girth LDPC NB-QC-LDPC TPC-HD TPC-SD CI-BCH3 CI-BCH4 10 UEP-BCH Two-iter. conc BCH SP-BCH TPC-HD Staircase TPC-SD CI-BCH3 Swizzle CI-BCH NCG (db) Fig. 15. State-of-the-art and beyond FEC codes comparison [7] A. Tychopoulos, O. Koufopaulou, and I. Tomkos, FEC in optical communications - A tutorial overview on the evolution of architectures and the future prospects of outband and inband FEC for optical communications, IEEE Circuits and Devices, vol. 22, pp , [8] G. P. Agrawal, Fiber-Optic Communication Systems, 3rd ed. John Wiley & Sons, [9] R. Blahut, Algebraic Codes for Data Transmission. Cambridge University Press. [Online]. Available: eqs2i-r9-oyc [10] Optical Transport Network (OTN) Tutorial. ITU. [Online]. Available: [11] Sklar, Bernard, Digital Communications: Fundamentals and Applications. Upper Saddle River, NJ, USA: Prentice-Hall, Inc., [12] Freude, W. and Schmogrow, R. and Nebendahl, B. and Winter, M. and Josten, A. and Hillerkuss, D. and Koenig, S. and Meyer, J. and Dreschmann, M. and Huebner, M. and Koos, C. and Becker, J. and Leuthold, J., Quality metrics for optical signals: Eye diagram, Q-factor, OSNR, EVM and BER, in Transparent Optical Networks (ICTON), th International Conference on, July 2012, pp [13] Soft-Decision FEC: Key to High-Performance 100G Transmission. [Online]. Available: broader-smarter/morematerial-b/hw [14] P. Northcott, Swizzle FEC for 40G and 100G Optical Transmission, White Paper - PMC-Sierra, Inc., January [15] O. I. Forum. (2010, May) 100G Forward Error Correction White Paper. [Online]. Available: [16] I. S. Reed and G. Solomon, Polynomial Codes Over Certain Finite Fields, Journal of the Society for Industrial and Applied Mathematics, vol. 8, no. 2, pp , [17] Telecommunication Standardization Sector of ITU., ITU-T Recommendation G.709: General Aspects of Digital Transmission System : Synchronous Multiplexing Structure. International Telecommunication Union, [18] Telecommunicatio Standardization Sector of ITU, ITU-T Recommendation G.975: Forward error correction for submarine systems, Oct [19] L. Song, M.-L. Yu, and M. Shaffer, 10- and 40-Gb/s forward error correction devices for optical communications, Solid-State Circuits, IEEE Journal of, vol. 37, no. 11, pp , [20] Telecommunication Standardization Sector of ITU, ITU-T Recommendation G.975.1: Forward error correction for high bit-rate DWDM submarine systems, Feb [21] K. Cackovic-Altera. Implementing Forward Error Correction in Optical Networking. [Online]. Available: English/Newsletters/2011/Articles/ Article KevinCackovic.html [22] Fujitsu. (2012, Feb.) Soft-Decision FEC Benefits for 100G. [Online]. Available: fnc/whitepapers/soft-decision-fec-benefits-or-100g-wp.pdf

13 13 [23] K. Lee, H.-G. Kang, J.-I. Park, and H. Lee, 100GB/S two-iteration concatenated BCH decoder architecture for optical communications, in Signal Processing Systems (SIPS), 2010 IEEE Workshop on, oct. 2010, pp [24] B. Li, K. J. Larsen, D. Zibar, and I. T. Monroy, Over 10 db Net Coding Gain Based on 20% Overhead Hard Decision Forward Error Correction in 100G Optical Communication Systems, in 37th European Conference and Exposition on Optical Communications. Optical Society of America, 2011, p. Tu.6.A.3. [25] R. G. Gallager, Low-Density Parity-Check Codes. MIT Press, [26] J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, Reduced-Complexity Decoding of LDPC Codes, Communications, IEEE Transactions on, vol. 53, no. 8, pp , [27] Sharon, E. and Litsyn, S. and Goldberger, J., An efficient messagepassing schedule for LDPC decoding, in Electrical and Electronics Engineers in Israel, Proceedings rd IEEE Convention of, Sept 2004, pp [28] Hocevar, D.E., A reduced complexity decoder architecture via layered decoding of LDPC codes, in Signal Processing Systems, SIPS IEEE Workshop on, Oct 2004, pp [29] C.-K. Liau, S.-Y. Lin, T.-H. Tsai, and C. L. Wey, A partially parallel low-density parity check code decoder with reduced memory for long code-length, in 18th VLSI Des./CAD Symp., [30] Radosavljevic, P. and De Baynast, A. and Cavallaro, J.R., Optimized Message Passing Schedules for LDPC Decoding, in Signals, Systems and Computers, Conference Record of the Thirty-Ninth Asilomar Conference on, Oct 2005, pp [31] Juntan Zhang and Fossorier, M.P.C., Shuffled iterative decoding, Communications, IEEE Transactions on, vol. 53, no. 2, pp , Feb [32] Z. Cui, Z. Wang, and X. Zhang, Reduced-complexity column-layered decoding and implementation for LDPC codes, Communications, IET, vol. 5, no. 15, pp , [33] T. Mizuochi, Y. Miyata, K. Kubo, T. Sugihara, K. Onohara, and H. Yoshida, Progress in Soft-Decision FEC, in National Fiber Optic Engineers Conference. Optical Society of America, 2011, p. NWC2. [34] D. Chang, F. Yu, Z. Xiao, Y. Li, N. Stojanovic, C. Xie, X. Shi, X. Xu, and Q. Xiong, FPGA Verification of a Single QC-LDPC Code for 100 Gb/s Optical Systems without Error Floor down to BER of 10-15, in Optical Fiber Communication Conference. Optical Society of America, 2011, p. OTuN2. [35] D. A. Morero, M. A. Castrillon, F. A. Ramos, T. A. Goette, O. E. Agazzi, and M. R. Hueda, Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks, in GLOBECOM. IEEE, 2011, pp [36] D. A. Morero, M. A. Castrillon, T. A. Goette, M. G. Schnidrig, F. A. A. Ramos, and M. Rafael, Non concatenated FEC codes for ultra-high speed optical transport networks, U.S. Patent US 2012/ A1, [37] I. Djordjevic, L. Xu, T. Wang, and M. Cvijetic, Large Girth Low- Density Parity-Check Codes for Long-Haul High-Speed Optical Communications, in Optical Fiber communication/national Fiber Optic Engineers Conference, OFC/NFOEC Conference on, feb. 2008, pp [38] Q. Yang, W. Shieh, and I. B. Djordjevic, 1-Tb/s Large Girth LDPC- Coded Coherent Optical OFDM Transmission over 1040-km Standard Single-Mode Fiber, in Optical Fiber Communication Conference. Optical Society of America, 2011, p. JThA035. [39] D. Chang, F. Yu, Z. Xiao, N. Stojanovic, F. Hauske, Y. Cai, C. Xie, L. Li, X. Xu, and Q. Xiong, LDPC convolutional codes using layered decoding algorithm for high speed coherent optical transmission, in Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2012 and the National Fiber Optic Engineers Conference, 2012, pp [40] T. Mizuochi, Y. Konishi, Y. Miyata, T. Inoue, K. Onohara, S. Kametani, T. Sugihara, K. Kubo, H. Yoshida, T. Kobayashi, and T. Ichikawa, Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation, Photonics Technology Letters, IEEE, vol. 21, no. 18, pp , sept.15, [41] N. Kamiya and S. Shioiri, Concatenated QC-LDPC and SPC Codes for 100 Gbps Ultra Long-Haul Optical Transmission Systems, in Optical Fiber Communication Conference. Optical Society of America, 2010, p. OThL2. [42] I. B. Djordjevic, Advances in error correction coding for high-speed optical transmission, in Proc. IEEE Photonics Conference 2013 (IPC 2013), [43] K. Sugihara, Y. Miyata, T. Sugihara, K. Kubo, H. Yoshida, W. Matsumoto, and T. Mizuochi, A spatially-coupled type LDPC Code with an NCG of 12 db for optical transmission beyond 100 Gb/s, in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013, 2013, pp [44] C.-S. Choi, H. Lee, N. Kaneda, and Y.-K. Chen, Concatenated nonbinary LDPC and HD-FEC codes for 100Gb/s optical transport systems, in ircuits and Systems (ISCAS), 2012 IEEE International Symposium on, may 2012, pp [45] K. Onohara, DSP Based Enhanced FEC for 100G Optical Transmission, in Signal Processing in Photonic Communications. Optical Society of America, 2010, p. SPThA1. [46] T. Mizuochi, T. Sugihara, Y. Miyata, K. Kubo, K. Onohara, S. Hirano, H. Yoshida, T. Yoshida, and T. Ichikawa, Evolution and status of forward error correction, in Optical Fiber Communication Conference. Optical Society of America, 2012, p. OTu2A.6. [47] K. Onohara, Y. Miyata, K. Sugihara, T. Sugihara, K. Kubo, H. Yoshida, K. Koguchi, and T. Mizuochi, Implementation of soft-decision forward error correction for 100G digital coherent system, in OptoeElectronics and Communications Conference (OECC), th, july 2011, pp [48] K. Onohara, T. Sugihara, Y. Konishi, Y. Miyata, T. Inoue, S. Kametani, K. Sugihara, K. Kubo, H. Yoshida, and T. Mizuochi, Soft-Decision- Based Forward Error Correction for 100 Gb/s Transport Systems, IEEE Journal of Selected Topics in Quantum Electronics, vol. 16, no. 5, pp , Sep [49] I. B. Djordjevic, M. Arabaci, and L. L. Minkov, Next Generation FEC for High-Capacity Communication in Optical Transport Networks, J. Lightwave Technol., vol. 27, no. 16, pp , Aug [50] M. Arabaci, Nonbinary-LDPC-coded modulation schemes for highspeed optical communication networks, Ph.D. dissertation, Department of Electrical and Computer Engineering, the University of Arizona, [51] M. Davey and D. MacKay, Low density parity check codes over GF(q), in Information Theory Workshop, 1998, jun 1998, pp [52] M. C.Davey, Error-correction using Low-Density Parity-Check Codes, Ph.D. dissertation, University of Cambridge, [53] N. Bonello, S. Chen, and L. Hanzo, Low-density Parity-Check codes and their rateless relatives, IEEE Communications Surveys and Tutorials, vol. 13, no. 1, pp. 3 26, [54] C. Lin, I. Djordjevic, D. Zou, M. Arabaci, and M. Cvijetic, Nonbinary LDPC-Coded Mode-Multiplexed Coherent Optical OFDM 1.28-Tbit/s 16-QAM Signal Transmission Over 2000 km of Few-Mode Fibers With Mode-Dependent Loss, Photonics Journal, IEEE, vol. 4, no. 5, pp , oct [55] M. Arabaci, I. Djordjevic, R. Saunders, and R. Marcoccia, Polarizationmultiplexed rate-adaptive non-binary-ldpc-coded multilevel modulation with coherent detection for optical transport networks, in Opt. Express, vol. 18, no. 3, 2010, pp [56] B. Smith, A. Farhood, A. Hunt, F. Kschischang, and J. Lodge, Staircase Codes: FEC for 100 Gb/s OTN, Lightwave Technology, Journal of, vol. 30, no. 1, pp , jan.1, [57] I. Djordjevic, L. Xu, and T. Wang, Multidimensional turbo product and generalized LDPC codes with component RS codes suitable for use in beyond 100 Gb/s optical transmission, in Telecommunication in Modern Satellite, Cable, and Broadcasting Services, TELSIKS 09. 9th International Conference on, oct. 2009, pp [58] Z. Wang, Super-FEC Codes for 40/100 Gbps Networking, CoRR, vol. abs/ , [59] M. Scholten, T. Coe, and J. Dillard, Continuously-Interleaved BCH (CI-BCH) FEC Delivers Best-in-Class NECG for 40G and 100G Metro Applications, in National Fiber Optic Engineers Conference. Optical Society of America, 2010, p. NTuB3. [60] M. Scholten, T. Coe, J. Dillard, and F. Chang, Enhanced FEC for 40G / 100G, ECOC, Sept. 2009, vitesse. [61] Y. Miyata, K. Kubo, K. Onohara, W. Matsumoto, H. Yoshida, and T. Mizuochi, UEP-BCH Product Code based Hard-Decision FEC for 100 Gb/s Optical Transport Networks, in Optical Fiber Communication Conference. Optical Society of America, 2012, p. JW2A.7. [62] S. Dave, L. Esker, F. Mo, W. Thesling, J. Keszenheimer, and R. Fuerst, Soft-decision Forward Error Correction in a 40-nm ASIC for 100-Gbps OTN Applications, in National Fiber Optic Engineers Conference. Optical Society of America, 2011, p. JWA014. [63] Viasat. FEC IP Cores. ECC66100 Series. [Online]. Available: {http: // IPCores 114.pdf} [64] M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, High-Rate Nonbinary Regular Quasi-Cyclic LDPC Codes for Optical Communications, J. Lightwave Technol., vol. 27, no. 23, pp , Dec

14 14 [65] G. Tzimpragos, C. Kachris, D. Soudris and I. Tomkos, A LowComplexity Implementation of QC-LDPC Encoder in Reconfigurable Logic, in Field Programmable Logic and Applications (FPL), rd International Conference on, Sept 2013, pp [66] G. Tzimpragos, C. Kachris, D. Soudris, and I. Tomkos, A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders, in the 28th IEEE International Symposium on Parallel Distributed Processing (IPDPS), May 2014, to appear. [67] M. N. Sakib, V. Mahalingam, W. J. Gross, and O. Liboiron-Ladouceur, Optical Front-End for Soft-Decision LDPC Codes in Optical Communication Systems, J. Opt. Commun. Netw., vol. 3, no. 6, pp , Jun [68] M. N. Sakib, M. Moayedi, W. J. Gross, and O. Liboiron-Ladouceur, 45 Gb/s low complexity optical front-end for soft-decision LDPC decoders, Opt. Express, vol. 20, no. 16, pp , Jul [69] L. Beygi, E. Agrell, J. Kahn, and M. Karlsson, Rate-Adaptive Coded Modulation for Fiber-Optic Communications, Lightwave Technology, Journal of, vol. 32, no. 2, pp , Jan [70] M. Arabaci, I. Djordjevic, L. Xu, and T. Wang, Hybrid LDPC-coded modulation schemes for optical communication systems, in Lasers and Electro-Optics (CLEO), 2012 Conference on, May 2012, pp [71] M. Arabaci, I.B. Djordjevic, L. Xu and T. Wang, Nonbinary LDPCCoded Modulation for High-Speed Optical Fiber Communication Without Bandwidth Expansion, Photonics Journal, IEEE, vol. 4, no. 3, pp , June [72] I. Tomkos, S. Azodolmolky, J. Sole-Pareta, D. Careglio, and E. Palkopoulou, A Tutorial on the Flexible Optical Networking Paradigm: State-of-the-Art, Trends, and Research Challenges, Proceedings of the IEEE, to appear. Georgios Tzimpragos earned his Diploma degree in Electrical and Computer Engineering from National Technical University of Athens (NTUA) in Since then, he has been a member of the High Speed Networks and Optical Communications group of Athens Information Technology (AIT) and NTUA s Microprocessors and Digital Systems Lab, working under EU-funded projects as a research engineer. His research interests include embedded systems, reconfigurable computing (FPGAs), network processing and computer architecture. Christoforos Kachris is a senior researcher at Athens Information Technology (AIT), Greece. He obtained his Ph.D. in Computer Engineering from Delft University of Technology, The Netherlands in 2007, and the diploma and the M.Sc. in Electronic and Computer Engineering from the Technical University of Crete, Greece in 2001 and 2003 respectively. From February 2009 till August 2010 he was a visiting assistant professor at the University of Crete, Greece and associate researcher at the Institute of Computer Science in the Foundation for Research and Technology (FORTH) working in the HiPEAC NoE and the SARC IP European research projects. In 2006 he was a research intern at Xilinx Research Labs, San Jose, CA, working at the Networks Group. His research interests are in the area of reconfigurable computing, multi-core FPGAs, network processing, computer architecture and embedded systems Ivan B. Djordjevic is a tenured Associate Professor in the ECE Department of College of Engineering of University of Arizona, with a joint appointment in the College of Optical Sciences. Prior to joining the University of Arizona, he was with University of the West of England and University of Bristol, Bristol, UK; Tyco Telecommunications, Eatontown, USA; National Technical University of Athens, Athens, Greece; and State Telecommunication Company Telecom Serbia, Nis, Serbia. During sabbatical 2013 he was also with Technische Universitt Darmstadt, Darmstadt, Germany. Dr. Djordjevic is an author/co-author of four books, over 360 international journal/conference publications, and 26 US patents. Dr. Djordjevic serves as an associate editor for 3 journals. Milorad Cvijetic is currently Professor at University of Arizona - College of Optical Sciences in Tucson, Arizona. Prior joining University of Arizona he served as Vice President and Chief Technology Strategist at NEC Corporation of America in Herndon, Virginia. In his 30+ years long career mostly in the area of optical communications and networking, Dr. Cvijetic has been one of pioneers in the area of high-speed optical systems and coherent detection technologies, as well as the industry leader responsible for advanced optical networking technologies. He published numerous technical papers, and is the author of four books and author/coauthor of twelve US patents, all related to optical communications and networking. His current interests include high-speed DWDM optical transmission systems and networking, optical access networks, optical-wireless systems, and quantum communications. Dimitrios Soudris received the Diploma and Ph.D. degrees in electrical engineering from the University of Patras, Patras, Greece, in 1987 and Since 1995 and for 13 years, he has served as a Professor with the Department of Electrical and Computer Engineering, Democritus University of Thrace, Avdira, Greece. He is currently working as an Associate Professor with the School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece. His research focuses on embedded systems design, low power VLSI design, and reconfigurable architectures. He has published more than 300 papers and is the coauthor/coeditor of six Kluwer/Springer books. He has served as a General/Program Chair for PATMOS 1999 and PATMOS 2000 and IFIP-VLSISOC Dr. Soudris is a member of the VLSI Systems and Applications Technical Committee of IEEE CAS and HiPEAC

15 Dr. Ioannis Tomkos is with the Athens Information Technology Center (AIT), since Sep He was elected as Adjunct Faculty at the College of Optical Sciences of University of Arizona ( now), at the Department of Electrical and Computer Engineering at University of Cyprus ( now) and at the Information Networking Institute of Carnegie- Mellon University, USA ( ). At AIT his Research Group was/is involved in over 25 EU funded research projects and in national and industry projects, within which Dr. Tomkos has a consortiumwide leading role (including Project Leader/Technical Manager of 8 major EU projects). Based on his innovative research ideas, he has attracted for AIT an amount of funding in excess of 7.5M Euros. He is a Fellow of the IET (2010) and OSA (2012) for outstanding contributions to the field of transparent optical networking. He was also elected Distinguished Lecturer of IEEE Communications Society (2007). He has co-authored over 550 articles (including over 330 archival through IEEE Xplore) and has received over 4000 citations to his work. He is the co-recipient of the 2014 IEEE/OSA JLT Best Paper Award. He served as the Chair of the Optical Networking Technical Committee of IEEE Communications Society and a member of the IEEE ComSocs Techical Activities Council. He was also Chairman of the IFIP Group on Photonic Networking and the Chairman of the Optical Communications Group at OSA. He is currently the Chair of the Greek chapter of IEEE Photonics Society. 15