HYBRID CONCATENATED CONVOLUTIONAL CODES FOR DEEP SPACE MISSION

Transcription

1 HYBRID CONCATENATED CONVOLUTIONAL CODES FOR DEEP SPACE MISSION Presented by Dr.DEEPAK MISHRA OSPD/ODCG/SNPA

2 Objective :To find out suitable channel codec for future deep space mission. Outline: Interleaver Design. Puncturing. Decoding Algorithms. Various Turbo code like structure like Hybrid Concatenated codes. Validation and verification using MATLAB HDL Co Simulation Hardware in loop Simulation

3 Digital Communication System Information Source & Input Transducer Source Encoder Channel Encoder Digital Modulator Transmitted Signal Synchroniz ation Channel Output Signal Outpot Transducer Source Decoder Channel Decoder Digital Demodulator Received Signal

4 Shannon theorem H( z) C T S TC Channel Coding Thorem Where L K 1 k 0 H(S) = - p k l k p i log(p i) C P Blog 2 1 bits N0B / sec Shannon Source Coding theorem Information Capacity Theorem

5 Interleaver Design

6 Classical Block diagram

7 Interleaver Design Earlier Concepts Design Interleaver Design Earlier Interleaver design is separate design and There is no relation between interleaver design and Channel coder design. Purpose To distribute the error through out the frame. It has the job of spreading out long bursts of errors

8 Interleaver Design Resent Concepts Interleaver Design Design Interleaver design is a part of Channel coder design. Purpose To provide Interleaver gain (decorrelation gain) to decoder. Different properties:- 1) S distance properties 2) mod-k properties 3) symmetric properties

9 S distance Property An interleaver with the spread or S distance property will, after interleaving, separate all neighboring elements at least S interleaver index distance a part, i.e., S min( π(i)-π (j), ( π -1 (i)-π -1 (j) ), for all i,j I, i-j =1. The performance of Channel codes improves as the S distance increases. S< [ N/2], where N is the size of the interleaver

10 Input /output Position Plot of a 192 bit poor S distance random Interleaver Input /output Position Plot of MATLAB a 192 bit good EXPO s distance 2015 random Interleaver

11 Mod-k Property Mod K Property used in applications where k-1 parity bits are punctured from each constituent code. We call this a pure mod-k interleaver where the modulus rule applies to all elements of the interleaver. Therefore a pure mod-k interleaver has i mod k = j mod k, where the interleaver maps i j.

12 Symmetric Property A disadvantage of most of the interleavers types mentioned previously is that they require both an interleave and a deinterleave sequence. Since an interleave and a deinterleave sequence are normally different, separate hardware or look up tables are usually required for each sequence. We can solve this problem by using a symmetric interleaver, where the interleaver and deinterleaver sequences are identical.

13 CCSDS PCCC Codes Standardization of turbo codes by the Consulting Committee for Space Data System (CCSDS) organization was remarkable efficient process, because there are relatively few parameters must be determined to define a turbo code CCSDS TURBO CODES STANDARD

14 CCSDS B-6 Standard Turbo Encoder

15 CCSDS Compline Turbo codes CCSDS Compline Turbo Encoder and Decoder encoded In1 Out1 Signal From Workspace1 CCSDS compline Turbo Encoder Tx Error Rate Calculation Rx AWGN pcccber -K- Model Parameters Out1 In1 Double-click to set model parameters CCSDS compline Turbo Decoder finaldatad To Workspace1

16 CCSDS Interleaver design

17 Input / Output distribution of CCSDS Interleaver OUTPUT INPUT

18 Proposed Interleaver The proposed interleaver is based on Gaussian distribution function. The selective criteria of these models are minimum distance and multiplicities for all suggested algorithmic interleavers and polynomials for turbo codes. m=mod((h-1),2); i=floor((h-1)/446); j= floor((h-1)/2)- (i*223); t=mod((19*i+1),4); q= mod(t,8)+1; c=mod((9*j+113*m),223); position1=(2*(t+(c*4)+1))-m; pot(h)=position1;

19 Input / Output Distribution of Proposed Interleaver OUTPUT INPUT

20 Frame length Proposed Interleaver Advantages The advantages of proposed interleaver with respect to CCSDS interleaver are following. There is no need to store 8 prime integers value in hardware. Since It has only fixed value. The S distance property is better compare to CCSDS interleaver. The minimum hamming distance d min and its multiplicity values, A min is better compare to CCSDS standard. Code rate Feedback Polynomial Feed forward Polynomial Interleaver Model d min A min W min / CCSDS / PROPOSED

21 Proposed Interleaver Advantages

22 SIMULATION APPROACH

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25 Proposed Interleaver Advantages BER dB Eb/No(dB)

26 Puncturing

27 CCSDS Compline Turbo codes 1 In Convolutional Encoder finaldatad4 To Workspace2 Encoder1 General Internal Block Interleaver Interleaver Convolutional Encoder 1 Matrix Concatenate 1 Out Encoder2 finaldatad3 To Workspace1 finaldatad2 To Workspace3 Turbo Encoder Turbo Encoder 1 LTE In1 Turbo Encoder Puncture Puncture to make 1/2 code rate Unipolar to Bipolar Converter 1 Out1

28 CCSDS Compline Turbo codes Turbo Decoder 1 Out1 Out f or {... } Lc2 Lc1 Lc3 Multiport Selector Select Rows Insert Zero Insert Zero 1 In1 Turbo Decoder For Iterator For Iterator z Delay General Block Deinterleaver Internal Deinterleaver Lin 0/1 Hard Decision 1 Out 3 Lc3 2 Lc1 L(u) L(u) APP Decoder L(c) L(c) Decoder1 NotUsed General Block Interleaver Internal Interleaver 1 Lc2 L(u) L(u) APP Decoder L(c) L(c) Decoder2 NotUsed2

29 CCSDS Compline Turbo codes Turbo Decoder without Transmission of Systematic Bits For Iterator For Iterator [1788x1] z Delay [1788x1] Pad Pad Tail2 [1784x1] [1784x1] General Block Deinterleaver Internal Deinterleaver [1788x1] Y U [1784x1] Remove Tail2 [1784x1] [1784x1] [1784x1] [1784x1] Lin 0/1 Hard Decision 1 Out 1 [1788x1] [1788x1] L(u) L(c) APP Decoder L(u) L(c) [1788x1] [1784x1] U Y Remove Tail [1788x1] [1784x1] General Block Interleaver Internal Interleaver [1784x1] 2 [1788x1] Pad Pad Tail [1788x1] L(u) L(u) APP Decoder L(c) L(c) [1788x1] [1788x1] Lc1 Decoder1 NotUsed Lc2 Decoder2 NotUsed2

30 Comparative Performance Analysis of Different Turbo Codec Result shows that deletion of parity bit will be preferred over systematic bits.

31 Decoder in case of Turbo code

32 : 1. Decoding algorithm MAP Algorithm (max of posteriori probability). Log-MAP Algorithm Near Log-MAP Algorithm SOVA Algorithm (Soft output Viterbi algorithm ) Performance of MAP Algorithm is better compare to other algorithm,however Log-MAP and SOVA algorithm is easier to implement in Hardware (i.e. In log domain multiplication become addition and division become subtraction.) May 13, 2015

33 Decoding Algorithm fhscc Decoding Algorithm for Hybrid Concatenated Codes Decoding algorithm Log-MAP Algorithm (max of posteriori probability). SOVA Algorithm (Soft output Viterbi algorithm ) These two algorithm are practically use for implementation of Concatenated decoders. However decoding complexity of HCCC is still higher.further modification on Log-MAP algorithm know as Linear Log-MAP Algorithm.

34 Decoding using Log-MAP Algorithm

35 Decoding using SOVA Algorithm

36 Turbo codes Log-MAP vs SOVA G=[7 5], Unpunctured(1/3), frame size=1024, Iteration=8. Iteration increment.. SOVA Iteration increment.. Log_MAP

37 Decoding Algorithm for HSCC where Linear Log-MAP Algorithm + + is a real number. This operation with multiple arguments can be decomposed into a recursive form using a max* operator with only two arguments, such as Applying the Jacobian logarithm, a two-input max* operator can be expressed in the form

38 Decoding Algorithm for HSCC Linear Log-MAP Algorithm A further enhancement is the more complex linear-log-map algorithm, which offers one of the best trade-offs in terms of complexity and performance among the different max* variants.it achieves an approximation very close to that of the log-map max* implementation by using a linear correction function We found that, parameters a = -0:24904 and T = 2:5068 minimize the total squared error between the exact correction function and its linear approximation, when using floating-point operations to implement the decoder

39 Simulation Parameter Parameter Eb/No Value 0-7 db Block Length 1784 Interleaver Random Interleaver Iteration 6

40 Simulation of turbo decoder using Linear Log MAP using a = -0:24904 and T = For Iterator For Iterator z Delay General Block Deinterleaver Internal Deinterleaver Lin 0/1 Hard Decision 1 Out 3 Lc3 2 Lc1 msg llr out Linearlogmap Embedded MATLAB Function1 General Block Interleaver Internal Interleaver 1 Lc2 msg llr out linearlogmap Embedded MATLAB Function2 May 13, 2015 SAC TDP/R&D 2009

41 Performance Comparison 10 0 PERFORMANCE COMPARISION BETWEEN LOG MAP AND LINEAR LOG MAP Log-MAP Linear Log-MAP 10-5 BER May 13, 2015 SAC TDP/R&D 2009 Eb/No(dB)

42 Serial concatenated codes Serial concatenated Encoder and Decoder 1 In1 Convolutional Encoder Outer Encoder Random Interleaver Convolutional Encoder Inner Encoder Unipolar to Bipolar Converter 1 Out1 1 In1 O Deinterlacer E Deinterlacer L(u) L(u) APP Decoder L(c) L(c) Outer Decoder Random Interleaver L(u) L(u) APP Decoder L(c) L(c) -K- Inner Decoder Out1 1 Add Random Deinterleaver z -? -K- 0/1 Lin

43 Hybrid concatenated codes Hybrid concatenated Encoder and Decoder 1 In1 Random Interleaver Convolutional Encoder Convolutional Encoder Outer Encoder1 Random Interleaver Convolutional Encoder Unipolar to Bipolar Converter Unipolar to Bipolar Converter O Interlacer E Interlacer 1 Out1 Outer Encoder Inner Encoder 1 In1 O Deinterlacer E Deinterlacer Out1 1 L(u) L(u) zeros(sccc_len,1) APP Decoder L(c) L(c) Outer Decoder Random Deinterleaver L(u) L(u) APP Decoder L(c) L(c) -K- Inner Decoder Random Interleaver z -? 0/1 Lin Add Random Interleaver Random Deinterleaver L(u) APP Decoder L(u) L(c) L(c) -K- Outer Decoder1

44 10-1 COMPARITIVE PERFORMANCE OF SCCC,PCCC AND HCCC BER Turbo codes CROSS OVER POINT SCCC PCCC HCCC Eb/No

45 Hybrid Concatenated codes with respect to different interleaver

46 RESULTS Packet size : 1784 Bits, BER=10-6 S.No Interleaver Type 1 st iteration (Eb/No) 2 nd iteration (Eb/No) 3 rd iteration (Eb/No) 1 Pseudo random Matrix Helical CircularA Algebraic

47 Turbo Coded Digital QPSK Modulator for Human Space Program

48 Modulator Block Diagram

49 Validation and Verification

50 Turbo Decoder

51 Simulation vs Hardware Matlab Simulation Hardware

52 Simulation vs Hardware Matlab Simulation Hardware

53 DVM Model

54 Hardware Setup

55 Hardware Spectrum

56 Demodulation

57 Verification of coding gain

58 APSK Modulator Block Diagram

59 DESIGN PARAMETER

60 CCSDS Standard APSK Modulator in Simulink

61 Noise Characterization at 13db Eb/No

62 Noise Characterization at 9 db Eb/No

63 Simulation Result at 1784 bits frame length 10 0 Uncoded 16-APSK performance Turbo coded 16-APSK performance BER db coding gain Eb/No(dB)

64 Characterization of Turbo Encoder and Decoder

65 CURRENT STATUS

66 Hardware Constellation of 16 APSK

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68 HDL Cosimulation

69 FPGA IN LOOP VERFICATION

70 Verification of Turbo decoder

71 Cosimulation and FPGA IN LOOP VERFICATION

72 Result achieved New interleaver design : Performance is better than 1.31 db compare to CCSDS compliant interleaver. Puncturing : Suitable puncturing scheme for Turbo like codes. Decoding scheme: Optimize decoding scheme for hardware implementation. Encoder and Decoder selection: Suitable structure for future deep space mission.

73 Use of MATLAB to achieve the results Co simulation of proposed interleaver with CCSDS Interleaver Performance comparison of various puncturing channel codec. Comparison of various decoding algorithms. Simulation of various Turbo code like structure. Verification and Validation of codec without actual hardware.

74 Questions?

75 Dr. Deepak Mishra Scientist/Engineer -SF Onboard Signal Processing Division (OSPD) Optical & Digital Communication Group (ODCG) Space Applications Centre Indian Space Research Organisation Ahmedabad