description S0 OE1 OE2 V CC S1 SL Q H H/Q H F/Q F D/Q D B/Q B CLK SR G/Q G E/Q E C/Q C A/Q A Q A CLR GND CLK B/Q S1 GND CLR

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1 Multiplexed I/O Ports Provide Improved Bit Deity Four Modes of Operation: old (Store) Shift Right Shift eft oad Data Operate With Outputs Enabled or at igh Impedance 3-State Outputs Drive Bus ines Directly Can Be Cascaded for n-bit Word engths Synchronous Clear Applicatio: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These 8-bit universal shift/storage registers feature multiplexed input/output (I/O) ports to achieve full 8-bit data handling in a 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 SN54AS323...J PACKAGE SN74AS DW OR N PACKAGE (TOP VIEW) G/Q G E/Q E C/Q C A/Q A Q A S0 OE1 OE2 G/Q G E/Q E C/Q C A/Q A Q A CR GND Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs synchronously when the clear (CR) input is low. Taking either OE1 or OE2 high disables the outputs but has no effect on clearing, shifting, or storing data. The SN54AS323 is characterized for operation over the full military temperature range of 55 C to 125 C. The SN74AS323 is characterized for operation from 0 C to 70 C V CC S1 S Q /Q F/Q F D/Q D B/Q B CK SR SN54AS FK PACKAGE (TOP VIEW) OE2 OE1 S0 CR GND SR V CC CK B/Q S1 B S Q /Q F/Q F D/Q D Copyright 1994, Texas Itruments Incorporated POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

2 SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 FUNCTION TABE INPUTS I/O PORTS OUTPUTS MODE CR S1 S0 OE1 OE2 CK S SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG /Q QA Q Clear old Shift Right Shift eft QA0 QA0 QBn QBn oad a b c d e f g h a h NOTE: a...h = the level of the steady-state input at inputs A through, respectively. This data is loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. logic symbol QB0 QB0 QAn QAn QCn QCn QC0 QC0 QBn QBn QDn QDn QD0 QD0 QCn QCn QEn QEn QE0 QE0 QDn QDn QFn QFn QF0 QF0 QEn QEn QGn QGn QG0 QG0 QFn QFn Qn Qn Q0 Q0 QGn QGn QA0 QA0 QBn QBn Q0 Q0 QGn QGn CR OE1 OE2 S0 S1 CK SRG8 4R & 3EN M 0 3 C4/1 /2 SR A/QA ,4D 3,4D 8 QA B/QB C/QC D/QD E/QE F/QF G/QG /Q S , 13 3, 4D 6, 13 3, 4D 12, 13 2, 4D Z5 Z6 Z12 17 Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

3 SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 logic diagram (positive logic) CR 9 S0 1 S1 SR (shift right serial input) Six Identical Channels Not Shown 18 S (shift left serial input) CK 12 QA 8 1D C1 1D C1 17 Q OE1 OE A/QA /Q I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I : All inputs V I/O ports V Operating free-air temperature range, T A : SN54AS C to 125 C SN74AS C to 70 C Storage temperature range C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

4 SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 recommended operating conditio SN54AS323 SN74AS323 MIN NOM MA MIN NOM MA VCC Supply voltage V VI igh-level input voltage 2 2 V VI ow-level input voltage V IO IO igh-level output current ow-level output current QA or Q QA thru Q QA or Q 4 8 QA thru Q TA Operating free-air temperature C UNIT ma ma electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS323 SN74AS323 MIN TYP MA MIN TYP MA VIK VCC = 4.5 V, II = 18 ma V VO VO II Any output VCC = 4.5 V to 5.5 V, IO = 0.4 ma VCC 2 VCC 2 QA thru Q VCC = 4.5 V QA or Q VCC = 4.5 V QA thru Q VCC = 4.5 V A thru Any others VCC = 5.5 V UNIT IO = 1 ma V IO = 2.6 ma IO = 4 ma IO = 8 ma IO = 12 ma IO = 24 ma VI = 5.5 V VI = 7 V II VCC = 5.5 V, VI = 2.7 V µa II IOS S0, S1, SR, S Any others QA or Q QA thru Q VCC = 5.5 V, VI = 0.4 V VCC = 5.5 V, VO = 2.25 V Outputs high ICC VCC = 5.5 V Outputs low ma Outputs disabled All typical values are at VCC = 5 V, TA = 25 C. For I/O ports (QA thru Q), the parameters II and II include the off-state output current. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. V ma ma ma 4 POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

5 SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54AS323 SN74AS323 MIN MA MIN MA fclock Clock frequency (at 50% duty cycle) Mz tw Pulse duration CK high or low tsu th Setup time before CK S0 or S Serial or parallel data igh UNIT ow 15 6 CR active Inactive-state setup time before CK CR old time after CK Inactive-state setup time is also referred to as recovery time. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) S0 or S1 0 0 Serial or parallel data 0 0 TO (OUTPUT) VCC = 4.5 V to 5.5 V, C = 50 pf, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MA SN54AS323 SN74AS323 MIN MA MIN MA fmax Mz tp CK QA thru Q tp tp CK QA or Q tp tpz OE1, OE2 QA thru Q tpz tpz S0, S1 QA thru Q tpz tpz OE1, OE2 QA thru Q tpz tpz S0, S1 QA thru Q tpz For conditio shown as MIN or MA, use the appropriate value specified under recommended operating conditio. UNIT POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

6 SDAS267A DECEMBER 1982 REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54AS/74AS AND 54AS/74AS DEVICES VCC 7 V R = R1 = R2 S1 R From Output Under Test C (see Note A) R Test Point From Output Under Test C (see Note A) Test Point From Output Under Test C (see Note A) R1 R2 Test Point OAD CIRCUIT FOR BI-STATE TOTEM-POE OUTPUTS OAD CIRCUIT FOR OPEN-COECTOR OUTPUTS OAD CIRCUIT FOR 3-STATE OUTPUTS Timing Input 3.5 V igh-evel Pulse 3.5 V Data Input tsu th 3.5 V ow-evel Pulse tw 3.5 V VOTAGE WAVEFORMS SETUP AND OD TIMES VOTAGE WAVEFORMS PUSE DURATIONS Output Control (low-level enabling) Waveform 1 S1 Closed (see Note B) Waveform 2 S1 Open (see Note B) tpz tpz tpz tpz 3.5 V 3.5 V VO VO 0 V VOTAGE WAVEFORMS ENABE AND DISABE TIMES, 3-STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) tp tp tp 3.5 V VO VO tp VO VO VOTAGE WAVEFORMS PROPAGATION DEAY TIMES NOTES: A. C includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 Mz, tr = tf = 2, duty cycle = 50%. E. The outputs are measured one at a time with one traition per measurement. Figure 1. oad Circuits and Voltage Waveforms 6 POST OFFICE BO DAAS, TEAS POST OFFICE BO 1443 OUSTON, TEAS

7 PACKAGE OPTION ADDENDUM 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pi Package Qty Eco Plan (2) ead/ball Finish (6) MS Peak Temp (3) Op Temp ( C) Device Marking RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to RA SNJ54AS323J SA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to SA SNJ54AS323W SN74AS323N ACTIVE PDIP N Pb-Free (RoS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS323N SNJ54AS323J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to RA SNJ54AS323J SNJ54AS323W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to SA SNJ54AS323W (4/5) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new desig. IFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new desig. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoS), Pb-Free (RoS Exempt), or Green (RoS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoS): TI's terms "ead-free" or "Pb-Free" mean semiconductor products that are compatible with the current RoS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoS Exempt): This component has a RoS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise coidered Pb-Free (RoS compatible) as defined above. Green (RoS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MS, Peak Temp. - The Moisture Seitivity evel rating according to the JEDEC industry standard classificatio, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be iide parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

8 PACKAGE OPTION ADDENDUM 17-Mar-2017 (6) ead/ball Finish - Orderable Devices may have multiple material finish optio. Finish optio are separated by a vertical ruled line. ead/ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers coider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTER QUAIFIED VERSIONS OF SN54AS323, SN74AS323 : Catalog: SN74AS323 Military: SN54AS323 NOTE: Qualified Version Definitio: Catalog - TI's standard catalog product Military - QM certified for Military and Defee Applicatio Addendum-Page 2

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