ULTRACHIP The Coolest LCD Driver. Ever!! HIGH-VOLTAGE MIXED-SIGNAL IC

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1 HIGH-VOLTAGE MIXED-SIGNAL IC 8 x 4RGB C-STN LCD Controller-Driver w/ 32-shade per dot, 2-bit per RGB (Dither 22K) ES Specifications August, 23 Revision 6 ULTRACHIP The Coolest LCD Driver Ever!!

2 UC682 8x4RGB CSTN Controller-Driver TABLE OF CONTENT INTRODUCTION MAIN APPLICATIONS FEATURE HIGHLIGHTS ORDERING INFORMATION 2 BLOCK DIAGRAM 4 PIN DESCRIPTION 5 REFERENCE COG LAYOUT 9 COMMAND TABLE 3 COMMAND DESCRIPTION 5 LCD VOLTAGE SETTING 29 V LCD QUICK REFERENCE 3 LCD DISPLAY CONTROLS 32 HOST INTERFACE 35 DISPLAY DATA RAM 42 RESET & POWER MANAGEMENT 45 ABSOLUTE MAXIMUM RATINGS 49 SPECIFICATIONS 5 AC CHARACTERISTICS 5 PHYSICAL DIMENSIONS 58 ALIGNMENT MARK INFORMATION 59 PI INFORMATION 6 PAD COORDINATES 6 TRAY INFORMATION 65 COF INFORMATION 66 REVISION HISTORY 68 Revision 6

3 UC682 8x4RGB CSTN Controller-Driver UC682 Single-Chip, Ultra-Low Power 8COM x 32SEG Matrix Passive Color LCD Controller-Driver INTRODUCTION UC682 is an advanced high-voltage mixedsignal CMOS IC, especially designed for the display needs of ultra-low power hand-held devices This chip employs UltraChip s unique DCC (Direct Capacitor Coupling) driver architecture to achieve near crosstalk free images, with well balanced gray shades and vivid colors In addition to low power COM and SEG drivers, UC682 contains all necessary circuits for high-v LCD power supply, bias voltage generation, timing generation and graphics data memory Advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption MAIN APPLICATIONS Cellular Phones and other battery operated palm top devices or portable Instruments FEATURE HIGHLIGHTS Single chip controller-driver for 8x4 matrix C-STN LCD with comprehensive support for input format and color depth: 8-bit RGB: 256 color 2-bit RGB: 4K color 6-bit RGB: 56K color (dithering) 24-bit RGB: 22K color (dithering) One software readable ID pin to support configurable vender identification Partial scroll function and programmable data update window to support flexible manipulation of screen data Support both row ordered and column ordered display buffer RAM access Support industry standard 3-wire, 4-wire serial bus (S9, S8, S8uc) and 8-bit/4-bit parallel bus (88 or 68) Special driver structure and gray shade modulation scheme Ultra-low power consumption under all display patterns Fully programmable Mux Rate, partial display window, Bias Ratio and Line Rate allow many flexible power management options Software programmable frame rates up to 25Hz Support the use of fast Liquid Crystal material for speedy LCD response Software programmable four temperature compensation coefficients On-chip Power-ON Reset and Software Reset command, make RST pin optional Self-configuring x charge pump with onchip pumping capacitors Only 2/3 external capacitors are required to operate Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements Very low pin count (9~ pins with S9) allows exceptional image quality in COG format on conventional ITO glass Many on-chip and I/O pad layout features to support optimized COG applications V DD (digital) range: 8V ~ 33V V DD (analog) range: 24V ~ 33V LCD V OP range: 5V ~ 5V Available OTP V LCD trimming option to support precise LCD contrast matching Available in COF and gold bump dies Bump pitch: 45µM Bump gap: 7µM Bump surface: 3,µM 2 Revision 6

4 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 ORDERING INFORMATION Part Number Versions Description UC682xHCZ Gold Bumped Die with PI Without OTP option UC682tHCZ Gold Bumped Die with PI With OTP option UC682xFBZ COF Without OTP option UC682tFBZ COF with OTP option Convention note: Grayed-out contents are functions not available yet 2 ES Specifications

5 UC682 8x4RGB CSTN Controller-Driver General Notes APPLICATION INFORMATION For improved readability, the specification contains many application data points When application information is given, it is advisory and does not form part of the specification for the device BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (9) days from the date of UltraChip s delivery There is no post waffle saw/pack testing performed on individual die Although the latest processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die Accordingly, it is the responsibility of the customer to test and qualify their applications in which the die is to be used UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die OTP CELL LIGHT SENSITIVITY The OTP memory cell is sensitive to photon excitation Under extended exposure to strong ambient light, the OTP cells can lose its content before the specified memory retention time span The system designer is advised to provide proper light shields to realize full OTP content retention performance LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries Customer using or selling these products for use in such applications do so at their own risk Revision 6 3

6 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 BLOCK DIAGRAM POWER-ON & RESET CONTROL CLOCK & TIMING GEN CONTROL & STATUS REGISTER PAGE ADDRESS GENERATOR DATA RAM I/O BUFFER COLUMN ADDRESS GENERATOR DISPLAY DATA RAM ROW ADDRESS GENERATOR LEVEL SHIFTER COM DRIVERS DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS SEG DRIVERS V LCD & BIAS GENERATOR C L C B C B 4 ES Specifications

7 UC682 8x4RGB CSTN Controller-Driver PIN DESCRIPTION Name Type Pins Description V DD V DD2 V DD3 V SS V SS2 PWR GND MAIN POWER SUPPLY V DD2 /V DD3 is the analog power supply and it should be connected to the same power source V DD is the digital power supply and it should be connected to a voltage source that is no higher than V DD2 /V DD3 Please maintain the following relationship: V DD +V V DD2/3 V DD "Minimize the trace resistance for V DD and V DD2 /V DD3 Ground Connect V SS and V SS2 to the shared GND pin Minimize the trace resistance for this node LCD POWER SUPPLY & VOLTAGE CONTROL This is the reference voltage to generate the actual SEG driving voltage V BIAS can be used to fine tune V LCD by external variable resistors Internal resistor network has been provided to simplify external trimming circuit The following network is sufficient for most applications V BIAS I V BIAS 33K M/VR V DD2 / V DD3 V B+ V B V B+ V B S B+ S B S B+ S B V LCD-IN V LCD-OUT PWR I PWR An internal RC filter is provided to filter noise on the V BIAS pin When not used, it is OK to leave V BIAS open circuit If noise starts to cause problem, connect a small bypass capacitor between V BIAS and V SS In the OTP version, this pin is disconnected from internal circuit So, there is no need to add bypass capacitor for this pin for OTP version LCD Bias Voltages These are the voltage sources to provide SEG driving currents These voltages are generated internally Connect capacitors of C BX value between V BX+ and V BX The resistance of these traces directly affects the driving strength of SEG electrodes and impacts the image of the LCD module Minimize the trace resistance is critical in achieving high quality image Wire to corresponding V B/2x pin Merge ITO traces between corresponding S Bx and V Bx in COG High voltage LCD Power Supply Connect these pins together By-pass capacitor C L is optional It can be connected between V LCD and V SS When C L is used, keep the trace resistance under 3 Ω NOTE Recommended capacitor values: C B : 5~25x LCD load capacitance or 22µF (2V), whichever is higher C L : (Optional) 5nF~5nF (6V) is appropriate for most applications Revision 6 5

8 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 Name Type Pins Description BM BM CS CS RST CD ID WR WR D~D7 I I 2 I I I I I/O HOST INTERFACE Bus mode: The interface bus mode is determined by BM[:] and D[7:6] by the following relationship: BM[:] D[7:6] Mode Data 68/8-bit Data 88/8-bit X 68/4-bit X 88/4-bit 3-wire SPI w/ 9-bit token (S9: conventional) 4-wire SPI w/ 8-bit token (S8: conventional) 3/4-wire SPI w/ 8-bit token (S8uc: Ultra-Compact) Chip Select Chip is selected when CS= H and CS = L When the chip is not selected, D[7:] will be high impedance When RST= L, all control registers are re-initialized by their default states Since UC682 has built-in Power-ON Reset and Software Reset command, RST pin is not required for proper chip operation An RC Filter has been included on-chip There is no need for external RC noise filter When RST is not used, connect the pin to V DD Select Control data or Display data for read/write operation In S9 modes, CD pin is not used Connect CD to V SS when not used L : Control data H : Display data ID pin is for production control The connection will affect the content of D[7] when using Get Status command Connect to V DD for H or V SS for L WR[:] controls the read/write operation of the host interface See Host Interface section for more detail In parallel mode, WR[:] meaning depends on whether the interface is in the 68 mode or the 88 mode In serial interface modes, these two pins are not used, connect them to V SS Bi-directional bus for both serial and parallel host interfaces In serial modes, connect D[] to SCK, D[3] to SDA, BM=x BM=x BM= BM= (Parallel) (Parallel) (S9) (S8/S8uc) D D D/D4 SCK SCK D D D/D5 D2 D2 D2/D6 D3 D3 D3/D7 SDA SDA D4 D4 D5 D5 D6 D6 S8/S8uc D7 D7 Connect unused pins to V SS 6 ES Specifications

9 UC682 8x4RGB CSTN Controller-Driver Name Type Pins Description SEG ~ SEG32 COM ~ COM8 HV HV HIGH VOLTAGE LCD DRIVER OUTPUT SEG (column) driver outputs Support up to 4 x RGB pixels Leave unused drivers open-circuit COM (row) driver outputs Support up to 8 rows Leave unused COM drivers open-circuit When designing LCM, always start from COM If the LCM has N pixel rows and N is less than 8, set CEN to be N-, and leave COM drivers [N+ ~ 8] open-circuit V DDX TST4 O I/HV MISC PINS Auxiliary V DD These pins are connected to the main V DD bus on chip They are provided to facilitate chip configurations in COG and COF applications These pins should not be used to provide V DD power to the chip It is not necessary to connect V DDX to main V DD externally Test control This pin has on-chip pull-up/down resistor Leave it open during normal operation TST4 is also used as one of the high voltage programming power supply for OTP operation For COG design with OTP options, please wire out TST4 with an ITO trace resistance of 2 Ω or less TST2 I/O Test I/O pins Leave these pins open during normal use TP[5:] I Test control Leave these pins open during normal use Note: Several control registers will specify based index for COM and SEG electrodes In those situations, COMX or SEGX will correspond to index X-, and the value ranges for those index registers will be ~79 for COM and ~3 for SEG Revision 6 7

10 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 RECOMMENDED COG LAYOUT Users can use either OTP control (through TST4 pin) or external circuit (through V BIAS pin) to fine tune V LCD Please refer to the following figures: FIGURE : Example for TST4 COG layout when using OTP control to fine tune V LCD FIGURE 2: Example for V BIAS COG layout when using external circuit to fine tune V LCD 8 ES Specifications

11 UC682 8x4RGB CSTN Controller-Driver REFERENCE COG LAYOUT dummy COM_pad<2> COM_pad<4> COM_pad<24> COM_pad<26> COM_pad<28> COM_pad<46> COM_pad<48> dummy2 FPC BONDING AREA NC D7 D6 D5 D4 D3 D2 D D RST CS CD WR WR TST4 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 VSS ~ VSS2 ~ 3 ~ 3 ~ 3 ~ 3 ~ 3 VB+ ~ SB+ VB+ ~ SB+ VB+ ~ SB+ VB+ ~ SB+ VB+ ~ SB+ VB+ ~ SB+ VB- ~ SB- VB- ~ SB- VB- ~ SB- VB- ~ SB- VB- ~ SB- VB- ~ SB- VB- ~ SB- VB- ~ SB- VLCD VLCD NC COM_pad<5> COM_pad<52> COM_pad<78> COM_pad<8> D7 X D6 D5 D4 D3 D2 D D VREF RST_ CS X CS CD WR X WR BM X BM TST4 TST4 TST3 TST2 TST PRG3 PRG2 PRG ID VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS VBP VBP VBP VBP VBP VBP VBP VBP VBP VBP_S VBP VBP VBP VBP VBP VBP VBP VBP VBP VBP_S VBN VBN VBN VBN VBN VBN VBN VBN VBN VBN_S VBN VBN VBN VBN VBN VBN VBN VBN VBN VBN_S VLCDIN VLCDIN VLCDOUT VLCDOUT COM_pad<79> COM_pad<77> SEG_pad<32> SEG_pad<3> SEG_pad<96> SEG_pad<95> SEG_pad<94> SEG_pad<62> SEG_pad<6> SEG_pad<6> SEG_pad<59> COM_pad<5> COM_pad<49> SEG_pad<2> SEG_pad<> Notes for V DD with COG: The V DD =8V-typ operation condition of UC682 should be met under all LCM formats Unless V DD, V DD2/3 ITO trances can each be controlled to be 5 Ω or lower, otherwise V DD -V DD2/3 separation can cause the actual on-chip V DD to drop below V DD =7V during high speed data write condition Therefore, for COG, V DD -V DD2/3 separation is not suitable for pure ITO based COG designs Revision 6 9

12 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 CONTROL REGISTERS UC682 contains registers which control the chip operation These registers can be modified by commands The following table is a summary of the control registers, their meanings and their default values Commands supported by UC682 will be described in the next two sections First, a summary table, followed by a detailed instruction-by-instruction description Name: Default: The Symbolic reference of the register Note that, some symbol name refers to bits (flags) within another register Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset Name Bits Default Description SL 7 H Scroll Line Scroll the displayed image up by SL rows The valid SL value is between (for no scrolling) and (79 2xFL) Setting SL outside of this range causes undefined effect on the displayed image FL 4 H Fixed Lines The first FLx2 lines of each frame are fixed and are not affected by scrolling (SL) When FL is non-zero, the screen is effectively separated into two regions: one scrollable, one non-scrollable When partial display mode is activated, the display of these 2xFL lines is also controlled by LC[] CR 7 H Return Column Address Useful for cursor implementation CA 7 H Display Data RAM Column Address (counted in RGB triplet) (Used in Host to Display Data RAM access) RA 7 H Display Data RAM Row Address (Used in Host to Display Data RAM access) BR 2 3H Bias Ratio The ratio between V LCD and V BIAS b: 5 b: 7 b: 8 b: 9 TC 2 H Temperature Compensation (per o C) b: -5% b: -% b: -5% b: -2% PM 8 55H Electronic Potentiometer to fine tune V BIAS and V LCD PMO 6 2H PM offset The effective PM value PMV = PM+PMO-32 Make sure PMV formula does not overflow or underflow (Available only on OTP version) OM 2 Operating Modes (Read only) b: Sleep b: Normal b: (Not used) b: Reset ID PIN Access the connected status of ID pin MSK 3 H R/G/B Write Data mask bits MSK[2:] = {MR, MG, MB} (Default: b) : Write : Block RS Reset in progress Host Interface not ready PC 4 DH Power Control PC[:]: b: LCD: 9nF b: LCD: 9~2nF b: LCD: 2~6nF b: LCD: 6~22nF PC[3:2]: b: External V LCD b: Internal V LCD (Standard) ES Specifications

13 UC682 8x4RGB CSTN Controller-Driver Name Bits Default Description DC 5 8H Display Control: DC[]: PXV: Pixels Inverse Bit-wise data inversion (Default : OFF) DC[]: APO: All Pixels ON (Default : OFF) DC[2]: Display ON/OFF (Default : OFF) DC[3]: Gray-shade Modulation mode : 8-shade mode : 32-shade Mode DC[4]: Dither Function Control : Disable Dither Function : Enable Dither Function AC 5 H Address Control: AC[]: WA: Automatic column/row Wrap Around (Default : ON) AC[]: Auto-Increment order : Column (CA) first : Row (RA) first AC[2]: RID: RA (row address) auto increment direction (L:+ H:-) AC[3]: CUM: Cursor update mode, (Default : OFF) when CUM=, CA increment on write only, wrap around suspended AC[4] : Window Program Enable : Disable : Enable WPC 8 H Window program starting column address Value range: ~3 WPP 8 H Window program starting row address Value range: ~79 WPC 8 67H Window program ending column address Value range: ~3 WPP 8 4FH Window program ending row address Value range: ~79 CEN DST DEN OTP operation FH H 4FH For OTP version IC, register WPC[:] and WPP[:] are also used to control the OTP operation (when OTPC[3]=) COM scanning end (last COM with full line cycle, based index) Display start (first COM with active scan pulse, based index) Display end (last COM with active scan pulse, based index) Please maintain the following relationship: CEN = the actual number of pixel rows on the LCD - CEN DEN DST+ 9 Revision 6

14 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 Name Bits Default Description LC 9H LCD Control: LC[]: Enable the first FLx2 lines in partial display mode (Default OFF) LC[]: MX, Mirror X SEG/Column sequence inversion (Default: OFF) LC[2]: MY, Mirror Y COM/Row sequence inversion (Default: OFF) LC[4:3]: Line Rate (Klps: Kilo-Line-per-second) b: Klps b: 28 Klps b: 6 Klps b: 2 Klps (Frame-Rate = Line-Rate / Mux-Rate) LC[5] : RGB filter order (as mapped to SEG, SEG2, SEG3) : BGR-BGR : RGB-RGB LC[7:6] : Color and input mode for Dither-Enabled: b : 256 color mode 3R-3G-2B (8-bit/RGB) b : 4K color mode 4R-4G-4B (2-bit/RGB) b : 56K color mode 5R-6G-5B (6-bit/RGB) b : 22K color mode 6R-7G-5B (24-bit/RGB) for Dither-Disabled: b : 256 color mode 3R-3G-2B (8-bit/RGB) b : 4K color mode 4R-5G-3B (2-bit/RGB) b : 4K color mode 5R-6G-5B (6-bit/RGB) b : 4K color mode 6R-7G-5B (24-bit/RGB) For data over 4R-5G-3B, each redundant LSB of each color will be truncated (Example: For R4R3R2RR - G5G4G3G2GG - B4B3B2BB, R, G, B, and B will be truncated) LC[9:8] : Partial Display Control xb: Disable Mux-Rate = CEN+ (DST, DEN not used) b: Enabled Mux-Rate = CEN+ b: Enabled Mux-Rate = DEN-DST++LC[]x2xFL APC APC 5 8 DH 36H Advanced Program Control For UltraChip only Please do not use OD OTP option flag : No OTP : With OTP OS OTP programming in-progress WS OTP Command Succeeded OTPC 6 H OTP Programming Control: OTP[2:] : OTP command : Sleep : Read : Erase : Program XX : For UltraChip use only OTP[3] : OTP Enable ( auto clear after OTP command action done ) OTP[4] : Use/Ignore OTP value : Ignore : Normal OTP[5] : OTP Command enable OTPM 8 H OTP Write Mask 2 ES Specifications

15 UC682 8x4RGB CSTN Controller-Driver COMMAND TABLE The following is a list of host commands supported by UC682 C/D: : Control, : Data W/R: : Write Cycle, : Read Cycle Useful Data bits Don t Care Command C/D W/R D7 D6 D5 D4 D3 D2 D D Action Default Write Data Byte Write byte N/A 2 Read Data Byte Read byte N/A 3 Get Status ID MX MY WA DE WS OD OS Get Status N/A 4 Set Column Address LSB Set CA[3:] Set Column Address MSB - Set CA[6:4] 5 Set Temp Compensation Set TC[:] 6 Set Panel Loading Set PC[:] 7 Set Pump Control Set PC[3:2] b 8 Set Adv Program Control R Set APC[R][7:], (double byte command) R =, or N/A 9 Set Scroll Line LSB Set SL[3:] Set Scroll Line MSB - Set SL[6:4] Set Row Address LSB Set RA[3:] Set Row Address MSB - Set RA[6:4] Set V BIAS Potentiometer (double-byte command) Set PM[7:] 55H 2 Set Partial Display Control Set LC[9:8] : Disable 3 Set RAM Address Control Set AC[2:] b 4 Set Fixed Lines Set FL[3:] 5 Set Line Rate Set LC[4:3] b 6 Set All-Pixel-ON Set DC[] 7 Set Inverse Display Set DC[] 8 Set Display Enable Set DC[4:2] b 9 Set Color Mask Set MSK[2:] 2 Set LCD Mapping Control Set LC[2:] 2 Set Color Pattern Set LC[5] (BGR) 22 Set Color Mode Set LC[7:6] b (56K) 23 System Reset System Reset N/A 24 NOP No operation N/A Set Test Control TT For testing only 25 (double byte command) Do not use N/A 26 Set LCD Bias Ratio Set BR[:] b: 9 27 Reset Cursor Update Mode AC[3]=, CA=CR AC[3]= 28 Set Cursor Update Mode AC[3]=, CR=CA AC[3]= 29 Set COM End - Set CEN[6:] 79 3 Set Partial Display Start - Set DST[6:] 3 Set Partial Display End - Set DEN[6:] 79 Set Window Program 32 Starting Column Address Set WPC[7:] Set Window Programming 33 Starting Row Address Set WPP[7:] Set Window Programming 34 Ending Column Address Set WPC[7:] 3 Set Window Programming 35 Ending Row Address Set WPP[7:] Enable window program Set AC[4] : Disable * Other than commands listed above, all other bit patterns may result in undefined behavior Revision 6 3

16 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 4 ES Specifications OTP Command C/D W/R D7 D6 D5 D4 D3 D2 D D Action Default 37 Set OTP Operation control - - Set OTP[5:] 38 Set OTP Write Mask Set OTP[7:] 39 Set V OTP Potentiometer 4 Set V OTP2 Potentiometer 4 Set OTP Write Timer 42 Set OTP Read Timer Shared with Window Programming commands N/A Other than commands listed above, all other bit patterns may result in undefined behavior The OTP commands listed above should only be used with OTP version of UC682 Command 39~42 are shared with command 32~35, and they have exactly the same code The interpretation of these four commands depends on register OTPC[3] When OTPC[3]=, they are interpreted as Window Programming commands When OTPC[3]=, they are OTP Control commands OTPM and PM are actually the same register The usage of this register is determined by OTPC[3] in similar ways as Command 39~42 After OTP-ERASE or OTP-PROGRAM operation (Set OTPC[3]=), always a) remove TST4 power source; b) Do a full Vdd ON-OFF cycle; before resuming normal operation

17 UC682 8x4RGB CSTN Controller-Driver COMMAND DESCRIPTION () WRITE DATA TO DISPLAY MEMORY Action C/D W/R D7 D6 D5 D4 D3 D2 D D Write data 8bits data write to SRAM UC682 will convert input RAM data to 2-bits of RGB data Please refer to command (22) Set Color Mode for detail data write sequence The format of 2 bits RGB data is as following: D D D9 D8 D7 D6 D5 D4 D3 D2 D D R G B (2) READ DATA FROM DISPLAY MEMORY Action C/D W/R D7 D6 D5 D4 D3 D2 D D Read data 8bits data from SRAM Each RGB triplet is stored as 2-bit in the display RAM Each 2 bits RGB data takes 2 RAM read cycles The data read will start with the high byte D[:4] and then low byte {D[3:],4 b} The read out RGB data is after-dither for 56K color and 22K color mode and after-extension for 256 color mode R3 R2 R R G4 G3 G2 G G B2 B B st Read 2nd Read Write/Read Data Byte (command /2) operation uses internal Row Address register (RA) and Column Address register (CA) RA and CA can be programmed by issuing Set Row Address and Set Column Address commands If wrap-around (WA, AC[]) is OFF (), CA will stop incrementing after reaching the CA boundary, and system programmers need to set the values of RA and CA explicitly If WA is ON (), when CA reaches end of column address, CA will be reset to and RA will be increased or decreased, depending on the setting of Row Increment Direction (RID, AC[2]) When RA reaches the boundary of RAM (ie RA = or 79), RA will be wrapped around to the other end of RAM and continue (3) GET STATUS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Get Status ID MX MY WA DE WS OD OS Status flag definitions: ID: Provide access to ID pin connection status MX: Status of register LC[], mirror X MY: Status of register LC[2], mirror Y WA: Status of register AC[] Automatic column/row wrap around DE: Display enable flag DE= when display is enabled WS : OTP Command Succeeded OD: OTP Option (Yes/No) OS : OTP action status (4) SET COLUMN ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Column Address LSB CA[3:] CA3 CA2 CA CA Set Column Address MSB CA[6:4] - CA6 CA5 CA4 Set SRAM column address for read/write access CA is counted in RGB triplets, not individual SEG electrode CA value range: ~3 Revision 6 5

18 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (5) SET TEMPERATURE COMPENSATION Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Temperature Comp TC[:] TC TC Set VBIAS temperature compensation coefficient (%-per-degree-c) Temperature compensation curve definition: b= -5%/ o C b= -%/ o C b= -5%/ o C b= -2%/ o C (6) SET PANEL LOADING Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Panel Loading PC[:] PC PC Set PC[:] according to the capacitance loading of LCD panel Panel loading definition: b 9nF b= 9~2nF b= 2~6nF b= 6~22nF (7) SET PUMP CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Pump Control PC[3:2] PC3 PC2 Set PC[3:2] to program the build-in charge pump stages Pump control definition: b=external VLCD b= Internal VLCD (standard) (8) SET ADVANCED PROGRAM CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set APC[:] R (Double byte command) APC register parameter For UltraChip only Please do NOT use (9) SET SCROLL LINE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Scroll Line LSB SL[3:] SL3 SL2 SL SL Set Scroll Line MSB SL[6:4] - SL6 SL5 SL4 Set the scroll line number Scroll line setting will scroll the displayed image up by SL rows The valid value for SL is between (no scrolling) and (79-2xFL) FL is the register value programmed by Set Fixed Lines command Image row Image row N Image row N Image row 79 SL= Image row 79 Image row Image row N- SL=N 6 ES Specifications

19 UC682 8x4RGB CSTN Controller-Driver () SET ROW ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Row Address LSB RA [3:] RA3 RA2 RA RA Set Row Address MSB RA [6:4] - RA6 RA5 RA4 Set SRAM row address for read/write access Possible value = ~79 () SET VBIAS POTENTIOMETER Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set V BIAS Potentiometer PM [7:] (Double byte command) PM7 PM6 PM5 PM4 PM3 PM2 PM PM Program V BIAS Potentiometer (PM[7:]) See section LCD VOLTAGE SETTING for more detail Effective range: ~ 255 (2) SET PARTIAL DISPLAY CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Partial Display Enable LC [9:8] LC9 LC8 This command is used to enable partial display function LC[9:8] : Xb: Disable Partial Display, Mux-Rate = CEN+ (DST, DEN not used) b: Enable Partial Display, Mux-Rate = CEN+ b: Enable Partial Display, Mux-Rate = DEN-DST++LC[]x2xFL (3) SET RAM ADDRESS CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set AC [2:] AC2 AC AC Program registers AC[2:] for RAM address control AC[]: WA, Automatic column/row wrap around : CA or RA (depends on AC[]= or ) will stop incrementing after reaching boundary : CA or RA (depends on AC[]= or ) will restart, and RA or CA will increment by one step AC[]: Auto-Increment order : column (CA) increment (+) first until CA reaches CA boundary, then RA will increment by (+/-) : row (RA) increment (+/-) first until RA reach RA boundary, then CA will increment by (+) AC[2]: RID, row address (RA) auto increment direction ( / = +/- ) When WA= and CA reaches CA boundary, RID controls whether row address will be adjusted by + or - AC[2:] controls the auto-increment behavior of CA and RA When Window Program is enabled (AC[4]=ON), see command description (32) ~ (36) for more details If WPC[:] and WPP[:] values are the default values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[4] is Revision 6 7

20 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (4) SET FIXED LINES Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Fixed Lines FL [3:] FL3 FL2 FL FL The fixed line function is used to implement the partial scroll function by dividing the screen into scroll and fixed area Set Fixed Lines command will define the fixed area, which will not be affected by the SL scroll function The fixed area covers the top 2xFL rows for mirror Y (MY) is and bottom 2xFL rows for MY= One example of the visual effect on LCD is illustrated in the figure below Fixed Area (2xFL) Scroll Area Scroll Area 8 Fixed Area (2xFL) 8 MY = MY = When partial display mode is activated, the display of these 2xFL lines is also controlled by LC[] ] Before turning on LC[], please make sure MY= DST >= FLx2 MY= DST >= DEN <= CEN DEN <= CEN-FLx2 (5) SET LINE RATE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Line Rate LC [4:3] LC4 LC3 Program LC [4:3] for line rate setting (Frame-Rate = Line-Rate / Mux-Rate) The line rate is automatically scaled down by /2 and /3 at Mux-Rate = 38 and 24 The following are line rates at Mux Rate = 39 ~ 8 b: Klps b: 28 klps b: 6 Klps b: 2 Klps (Klps: Kilo-Line-per-second) (6) SET ALL PIXEL ON Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set All Pixel ON DC [] DC Set DC[] to force all SEG drivers to output ON signals This function has no effect on the existing data stored in display RAM (7) SET INVERSE DISPLAY Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Inverse Display DC [] DC Set DC[] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM This function has no effect on the existing data stored in display RAM 8 ES Specifications

21 UC682 8x4RGB CSTN Controller-Driver (8) SET DISPLAY ENABLE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Display Enable DC [4:2] DC4 DC3 DC2 This command is for programming register DC[4:2] When DC[2] is set to, the IC will put itself into Sleep mode All drivers, voltage generation circuit and timing circuit will be halted to conserve power When DC[2] is set to, UC682 will first exit from Sleep mode, restore the power and then turn on COM drivers and SEG drivers There is no other explicit user action or timing sequence required to enter or exit the Sleep mode DC[3] controls the gray shade modulation modes UC682 has two gray shade modulation modes: an 8- sahde mode and a 32-shade mode The modulation curves are shown below Horizontal axes are the gray shade data The vertical axes are the ON-OFF ratio 9/9 is % ON for 8-shade mode, 5/5 is % ON for 32-shade mode DC[4] enables dither function Refer to (22) Set Color Mode for more information b: Disable b: Enable Revision 6 9

22 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (9) SET COLOR MASK Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Color Mask MSK [2:] MSK[2:] This command is used for program MSK[2:] which will control whether the input RGB data will be blocked from updating RGB data in the RAM (: Block, : Normal MSK[2:] = {MSK_R, MSK_G, MSK_B}) Example: Let color mode = 256 color, MSK[2:] = b (MSK_R =, MSK_G =, MSK_B = ) There is one pixel to be updated, and the original data for the pixel is b (RRR-GGG-BB) Suppose the new input RGB data is b, since R is masked, the data for the pixel would be updated as b (2) SET LCD MAPPING CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set LCD Mapping Control LC [2:] MY MX LC This command is used for program LC[2:] for COM (row) mirror (MY), SEG (column) mirror (MX) LC[2] controls Mirror Y (MY): MY is implemented by reversing the mapping order between RAM and COM electrodes The data stored in RAM is not affected by MY command MY will have immediate effect on the display image LC[] controls Mirror X (MX): MX is implemented by selecting the CA or 3-CA as write/read (from host interface) display RAM column address so this function will only take effect after rewriting the RAM data LC[] controls whether the soft icon section (~ 2xFL) is display or not during partial display mode (2) SET COLOR PATTERN Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Color Pattern LC [5] LC5 UC682 supports on-chip swapping of R B data mapping to the SEG drivers LC[5] SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG34 SEG3 SEG32 B G R B G R B G R R G B R G B R G B The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Mode below 2 ES Specifications

23 UC682 8x4RGB CSTN Controller-Driver (22) SET COLOR MODE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Color Mode LC [7:6] LC7 LC6 Program color mode and RGB input pattern Color mode (LC[7:6]) definition: Dither Options: DC[4]=b enables dither function Refer to (8) Set Display Enable for more information LC[7:6] = b ( RRR-GGG-BB, 256 color ) One byte of input data is extended and stored to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R2 R R G2 G G B B LC[7:6] = b ( RRRR-GGGG-BBBB, 4K color ) -bit extension for G, -bit dither for B 2 bits of input data is stored to 2 RAM bits 3 bytes of input data will be merged into 2 sets of RGB data Data Write Sequence D[7:] st Byte Write Data R3 R2 R R G3 G2 G G 2 nd Byte Write Data B3 B2 B B R3 R2 R R 3 rd Byte Write Data G3 G2 G G B3 B2 B B LC[7:6] = b ( RRRRR-GGGGGG-BBBBB, 56K color ) -bit dither for R/G, 2-bit dither for B 6 bits input data dithered to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R4 R3 R2 R R G5 G4 G3 2 nd Byte Write Data G2 G G B4 B3 B2 B B LC[7:6] = b ( RRRRRR-GGGGGGG-BBBBB, 22K color ) 2-bit dither per color 8 out of 24 bits input data is dithered to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R5 R4 R3 R2 R R nd Byte Write Data G6 G5 G4 G3 G2 G G -- 3 rd Byte Write Data B4 B3 B2 B B Data Read Sequence for LC[7:6] = Data Read Sequence D[7:] st Byte Read Data R2 R R R M G2 G G G M2 2 nd Byte Read Data G M B2 B B R/G/B: the input Red/Green/Blue data R/G MN : the Red/Green bits mapped from RGB input data for LC[7:6] =, 2, 3 Data Read Sequence D[7:] st Byte Read Data R D3 R D2 R D R D G D4 G D3 G D2 G D 2 nd Byte Read Data G D B D2 B D B D R/G/B DN : the N-th bit of after-dither Red/Green/Blue input data Note: For system designers who want to use their own dithering algorithm, please set LC[7:6] = b (56k color mode) and use the following input pattern to bypass on-chip dithering algorithm: R3-R2-R-R--G4-G3-G2-G-G--B2-B-B-- Revision 6 2

24 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 No-Dither Options: DC[4]=b disables dither function Refer to (8) Set Display Enable for more information LC[7:6] = b ( RRR-GGG-BB, 256 color ) One byte of input data is extended and stored to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R2 R R G2 G G B B LC[7:6] = b ( RRRR-GGGGG-BBB, 4K color ) 2 bits of input data is stored to 2 RAM bits 3 bytes of input data will be merged into 2 sets of RGB data Data Write Sequence D[7:] st Byte Write Data R3 R2 R R G4 G3 G2 G 2 nd Byte Write Data G B2 B B R3 R2 R R 3 rd Byte Write Data G4 G3 G2 G G B2 B B LC[7:6] = b ( RRRRR-GGGGGG-BBBBB, 56K color ) -bit truncation for R/G, 2-bit for B 6 bits input data truncated to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R4 R3 R2 R R G5 G4 G3 2 nd Byte Write Data G2 G G B4 B3 B2 B B LC[7:6] = b ( RRRRRR-GGGGGGG-BBBBB, 22K color ) 2-bit truncation for per color 8 out of 24 bits input data is truncated to 2 RAM bits Data Write Sequence D[7:] st Byte Write Data R5 R4 R3 R2 R R nd Byte Write Data G6 G5 G4 G3 G2 G G -- 3 rd Byte Write Data R4 R3 R2 R R Data Read Sequence for LC[7:6] = Data Read Sequence D[7:] st Byte Read Data R2 R R R M G2 G G G M2 2 nd Byte Read Data G M B2 B B R/G/B: the input Red/Green/Blue data R/G MN : the Red/Green bits mapped from RGB input data for LC[7:6] =, 2, 3 Data Read Sequence D[7:] st Byte Read Data R T3 R T2 R T R T G T4 G T3 G T2 G T 2 nd Byte Read Data G T B T2 B T B T R/G/B TN : the N-th bit of after-truncated Red/Green/Blue input data (23) SYSTEM RESET Action C/D W/R D7 D6 D5 D4 D3 D2 D D System Reset This command will activate the system reset Control register values will be reset to their default values Data stored in RAM will not be affected 22 ES Specifications

25 UC682 8x4RGB CSTN Controller-Driver (24) NOP Action C/D W/R D7 D6 D5 D4 D3 D2 D D No Operation This command is used for no operation (25) SET TEST CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set TT TT (Double byte command) Testing parameter This command is used for UltraChip production testing Please do not use (26) SET LCD BIAS RATIO Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Bias Ratio BR [:] BR BR Bias ratio definition: b= 5 b=7 b=8 b=9 (27) RESET CURSOR UPDATE MODE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Reset Cursor Update Mode AC[3]= CA=CR This command is used to reset cursor update mode function (28) SET CURSOR UPDATE MODE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set AC[3]= CR=CA This command is used for set cursor update mode function When cursor update mode is set, UC682 will update register CR with the value of register CA The column address CA will increment with write RAM data operation but the address wraps around will be suspended no matter what WA setting is However, the column address will not increment in read RAM data operation The set cursor update mode can be used to implement write after read RAM function The column address (CA) will be restored to the value, which is before the set cursor update mode command, when resetting cursor update mode The purpose of this pair of commands and their features is to support write after read function for cursor implementation (29) SET COM END Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set CEN (Double byte command) CEN register parameter This command programs the ending COM electrode CEN defines the number of used COM electrodes, and it should correspond to the number of pixel-rows in the LCD Revision 6 23

26 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (3) SET PARTIAL DISPLAY START Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set DST (Double byte command) DST register parameter This command programs the starting COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse (3) SET PARTIAL DISPLAY END Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set DEN (Double byte command) DEN register parameter This command programs the ending COM electrode, which has been assigned a full scanning period and will output an active COM scanning pulse CEN, DST, and DEN are -based index of COM electrodes They control only the COM electrode activity, and do not affect the mapping of display RAM to each COM electrodes The image displayed by each pixel row is therefore not affected by the setting of these three registers When LC[9]=, two partial display modes are possible with UC682: LC[8]=: ON-OFF only, ultra-low-power mode (if Mux-Rate 32, set BR=5) LC[8]=: Full gray shade low power mode (BR and PM stays the same) When LC[9:8]=b, the Mux-Rate is narrowed down to just the range between DST and DEN When Mux- Rate is under 32, set BR=5, PC[3:2]=b, and adjust PM to reduce VLCD and achieve the lowest power consumption When LC[9:8]=b, the Mux-Rate is still CEN+ This is achieved by suppressing only the scanning pulses, but not the scanning time slots, for COM electrodes that is outside of DST~DEN Under this mode, the gray-scale quality of the display is preserved, while the power can be reduced significantly In either case, DST/DEN defines a small subsection of the display which will remain active while shutting down all the rest of the display to conserve energy DST DEN CEN 79 Pulse Disable: Pulse Enable: Not Scanned: (32) SET WINDOW PROGRAM STARTING COLUMN ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set WPC (Double byte command) WPC[7:] register parameter This command is to program the starting column address of RAM program window 24 ES Specifications

27 UC682 8x4RGB CSTN Controller-Driver (33) SET WINDOW PROGRAM STARTING ROW ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set WPP (Double byte command) WPP register parameter This command is to program the starting row address of RAM program window (34) SET WINDOW PROGRAM ENDING COLUMN ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set WPC (Double byte command) WPC[7:] register parameter This command is to program the ending column address of RAM program window (35) SET WINDOW PROGRAM ENDING ROW ADDRESS Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set WPP (Double byte command) WPP register parameter This command is to program the ending row address of RAM program window (36) SET WINDOW PROGRAM ENABLE Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set Window Program Enable AC[4] AC4 This command is to enable the Window Program Function Window Program Enable should always be reset when changing the window program boundary and then set right before starting the new boundary program Window Program Function can be used to refresh the RAM data in a specified window of SRAM address When window programming is enabled, the CA and RA increment and wrap around will be automatically adjusted, and therefore allow effective data update within the window The direction of Window Program will depend on the WA (AC[]), RID (AC[2]), auto-increment order (AC[]) and MX (LC[]) register setting WA decides whether the program RAM address advances to next row/column after reaching the specified window column / row boundary RID controls the RAM address incrementing from WPP toward WPP (RID=) or reverse the direction (RID=) Auto-increment order directs the RAM address increment vertically (AC[]=) or horizontally (AC[]=) MX results the RAM column address incrementing from 3-WPC to 3-WPC (MX=) or WPC to WPC (MX=) Revision 6 25

28 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (WPP,WPC) Auto-increment order = MX= RID = (WPP,WPC) (WPP,WPC) Auto-increment order = MX= RID = (WPP,WPC) (WPP,WPC) Auto-increment order = MX= RID = (WPP,WPC) Auto-increment order = MX= RID = (WPP,3-WPC) (WPP,3-WPC) 26 ES Specifications

29 UC682 8x4RGB CSTN Controller-Driver Auto-increment order = MX= RID = (WPP,WPC) (WPP,WPC) Auto-increment order = MX= RID = (WPP,3-WPC) (WPP,3-WPC) Auto-increment order = MX= RID = (WPP,3-WPC) (WPP,3-WPC) Auto-increment order = MX= RID = (WPP,3-WPC) (WPP,3-WPC) Revision 6 27

30 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 (37) SET OTP CONTROL Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTPC (Double byte command) This command is for OTP operation control: OTP register parameter OTPC[2:] : OTP command : Sleep : OTP Read : OTP Erase : OTP Program XX : For UltraChip use only OTPC[3] : OTP Enable (automatically cleared each time after OTP command is done) OTPC[4] : OTP value valid ( ignore OTP value when L ) OTPC[5] : OTP operation mode Set [5] before OTP external V connection (38) SET OTP WRITE MASK Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTPM (Double byte command) OTP register parameter This command is enable write to each of the 8 individual OTP bits (39) SET V OTP POTENTIOMETER Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTP2 (Double byte command) OTP2 register parameter This command is for fine tuning V OPT setting (use with BR=) (4) SET V OTP2 POTENTIOMETER Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTP3 (Double byte command) OTP3 register parameter This command is for fine tuning V OTP2 PM setting (use with BR=) (4) SET OTP WRITE TIMER Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTP4 (Double byte command) OTP4 register parameter (42) SET OTP READ TIMER Action C/D W/R D7 D6 D5 D4 D3 D2 D D Set OTP5 (Double byte command) OTP5 register parameter 28 ES Specifications

31 UC682 8x4RGB CSTN Controller-Driver LCD VOLTAGE SETTING MULTIPLEX RATES Multiplex Rate is completely software programmable in UC682 via registers CEN, DST, DEN, and partial display control LC[9:8] Combined with low power partial display mode and a low bias ratio of 5, UC682 can support wide variety of display control options For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power BIAS RATIO SELECTION Bias Ratio (BR) is defined as the ratio between V LCD and V BIAS, ie BR = V LCD /V BIAS, where V BIAS = V B+ V B = V B+ V B The theoretical optimum Bias Ratio can be estimated by Mux + BR of value 5~2% lower/higher than the optimum value calculated above will not cause significant visible change in image quality Due to the nature of STN operation, an LCD designed for good gray-shade performance at high Mux Rate (eg MR=8), can generally perform very well as a black and white display, at lower Mux Rate However, it is also true that such technique generally can not maintain LCD s quality of gray shade performance, since the contrast of the LCD will increase as Mux Rate decreases, and the shades near the two ends of the spectrum will start to lose visibility UC682 supports four BR as listed below BR can be selected by software program BR 2 3 Bias Ratio Table : Bias Ratios TEMPERATURE COMPENSATION Four (4) different temperature compensation coefficients can be selected via software The four coefficients are given below: TC 2 3 % per o C Table 2: Temperature Compensation V LCD GENERATION V LCD may be supplied either by internal charge pump or by external power supply The source of V LCD is controlled by PC[3:2] For good product reliability, it is recommended to keep V LCD under 2V over the entire operating range When V LCD is generated internally, the voltage level of V LCD is determined by three control registers: BR (Bias Ratio), PM (Potentiometer), and TC (Temperature Compensation), with the following relationship: V LCD = ( CV + C PM PM ) ( + ( T 25) CT %) where C V and C PM are two constants, whose value depends on the setting of BR register, as illustrated in the table on the next page, PM is the numerical value of PM register, T is the ambient temperature in O C, and C T is the temperature compensation coefficient as selected by TC register V LCD FINE TUNING Gray shade and color STN LCD is sensitive to even a % mismatch between IC driving voltage and the V OP of LCD However, it is difficult for LCD makers to guarantee such high precision matching of parts from different venders It is therefore necessary to adjust V LCD to match the actual V OP of the LCD For the best results, software or OTP based V LCD adjustment is the recommended method for V LCD fine tuning For applications where mechanical manual fine tuning of V LCD becomes necessary, then V BIAS pin may be used with an external trim pot to fine tune the V LCD LOAD DRIVING STRENGTH The power supply circuit of UC682 is designed to handle LCD panels with load capacitance up to ~2nF when V DD2 = 25V For larger LCD panels use higher V DD and COF packaging 2nF is also the recommended limit for LCD panel size for COG applications Revision 6 29

32 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 V LCD QUICK REFERENCE VLCD PM VLCD-PM relationship for different BR setting at 25 o C BR CV (V) CPM (mv) PM VLCD (V) Note: For good product reliability, keep VLCD under 3V at room temperature, and keep VLCD under 5V under all temperature and operating conditions 2 The integer values of BR above are for reference only and probably have slight shift 3 ES Specifications

33 UC682 8x4RGB CSTN Controller-Driver HI-V GENERATOR AND BIAS REFERENCE CIRCUIT 2/3 VB+ SB+ 2 3 UC682 VB- SB- VB+ SB+ VB- SB- CB CB CB+ (OPTIONAL) 3pf for applications with VLCD over v VLCDOUT VSS VSS2 VLCDIN CL RL (OPTIONAL) FIGURE 3: Reference circuit using internal Hi-V generator circuit 2/3 R VR 2 3 VBIAS UC682 VB+ SB+ VB+ SB+ VB- SB- VB- SB- CB CB CB+ (OPTIONAL) ~3pf for applications with VLCD over v CBIAS VLCDOUT VLCDIN VSS VSS2 CL RL (OPTIONAL) FIGURE 4: Reference circuit using external Bias source Note Sample component values: (The illustrated circuit and component values are for reference only Please optimize for specific requirements of each application) C B : 5 ~ 25x LCD load capacitance or 22µF (2V), whichever is higher C L : 5nF ~ 5nF (6V) is appropriate for most applications R L : 3 ~ M Ω, RC time constant of CL x RL should be roughly 2~sec V R : M Ω R : 33K Ω C BIAS : nf ~ uf is the recommended default value (not required for OTP version) Revision 6 3

34 ULTRACHIP High-Voltage Mixed-Signal IC 999 ~ 23 LCD DISPLAY CONTROLS CLOCK & TIMING GENERATOR UC682 contains a built-in system clock All required components for the clock oscillator are built-in No external parts are required Four different line rates are provided for system design flexibility The line rate is controlled by register LC[4:3] When Mux-Rate is above 38, frame rate is calculated as: Frame Rate = Line-Rate / Mux-Rate When Mux-Rate is lowered to 38 (and 24), line rate will be scaled down by 2 (and 3) times automatically reduce power consumption Flicker-free frame rate is dependent on LC material and gray-shade modulation scheme Frame rate 75Hz is recommended for 32-shade mode Choose lower frame rate for lower power, and choose higher frame rate to improve LCD contrast and minimize flicker When switching from 32-shade modulation to 8- shade modulation, line rate will be scaled down automatically by ~3% Under most situations, flicker behavior is similar between these two different modulation schemes When switching from 32-shade modulation to 8- shade modulation, line rate will be scaled down automatically by ~35% Under most situations, flicker behavior is similar between these two different modulation schemes However, it is always recommended to test each mode to make sure flicker behavior is acceptable DRIVER MODES COM and SEG drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]) When SEG drivers are in Idle mode, they will be connected together to ensure zero DC condition on the LCD DRIVER ARRANGEMENTS The naming conventions are: COM(x), where x=~8, refers to the COM driver for the x-th row of pixels on the LCD panel The mapping of COM(x) to LCD pixel rows is fixed and it is not affected by SL, CST, CEN, DST, DEN, MX or MY settings DISPLAY CONTROLS There are three groups of display control flags in the control register DC: Driver Enable (DE), All- Pixel-ON (APO) and Inverse (PXV) DE has the overriding effect over PXV and APO DRIVER ENABLE (DE) Driver Enable is controlled by the value of DC[2] via Set Display Enable command When DC[2] is set to OFF (logic ), both COM and SEG drivers will become idle and UC682 will put itself into Sleep mode to conserve power When DC[2] is set to ON, the DE flag will become, and UC682 will first exit from Sleep mode, restore the power (V LCD, V D etc) and then turn on COM and SEG drivers ALL PIXELS ON (APO) When set, this flag will force all SEG drivers to output ON signals, disregarding the data stored in the display buffer This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM INVERSE (PXV) When this flag is set to ON, SEG drivers will output the inverse of the value it received from the display buffer RAM (bit-wise inversion) This flag has no impact on data stored in RAM PARTIAL SCROLL Control register FL specifies a region of rows which are not affected by the SL register Since SL register can be used to implement scroll function The FL register can be used to implement fixed region when the other part of the display is scrolled by SL PARTIAL DISPLAY UC682 provides flexible control of Mux Rate and active display area Please refer to command Set COM End, Set Partial Display Start, and Set Partial Display End for more detail GRAY-SHADE MODULATION MODE UC682 has two gray-shade modulation modes: 32-shade and 8-shade The 8-shade mode will consume ~3% less power than the 32-shade mode, and can be used for situations where power consumption is more critical than color fidelity Changing gray-shade modulation mode does not affect the content of SRAM display buffer, and the image data will remain the same after switching back and forth between 8-shade mode and 32-shade mode 32 ES Specifications