Enhanced Launch-Off-Capture Transition Fault Testing

Transcription

1 Enhanced Launch-Off-apture Transition Fault Testing Nisar Ahmed, Mohammad Tehranipoor 2,.P. Ravikumar ASI Product Development enter, Texas Instruments India, 2 Dept. of SEE, Univ. of Maryland Baltimore ounty, ABSTRAT With today s design size in millions of gates and working frequency in gigahertz range, timing-related defects are high proportion of the total chip defects and at-speed test is crucial. The transition fault model is widely used for detecting delayinduced defects. There are two transition fault pattern generation methods; i.e. launch-off-shift (LOS) and launch-off-capture (). In LOS, the transition is launched during the last shift cycle from the scan path (non-functional). The scan enable () is high during the last shift and must go low to enable response capture during the capture cycle. The time period for to make this transition corresponds to the functional frequency. This is not applicable for very low cost ATE, which have a limitation of one at-speed signal port. In method, the at-speed constraint on the signal is relaxed and the transition is launched from the functional path. The controllability of launching a transition at the target gate is less as it depends on the functional response of the circuit under test to the initialization vector. A novel scan-based at-speed test is proposed in which a transition can be launched either from the scan path or the functional path. The technique improves the controllability of transition fault testing and it does not require the scan enable to change at-speed. The scan enable control information is encapsulated in the test data and transferred during the scan operation to generate the local scan enable signals during the launch and capture cycle. A new scan cell, referred to as local scan enable generator (LSEG), is inserted in the scan chains to generate the local scan enable signals. The proposed technique is robust, practice-oriented and suitable for designs targeted for very low cost ATEs. I. INTRODUTION The semiconductor industry is adopting new fabrication processes to meet the area, power and performance requirements. As a result, modern Is are growing more complex in terms of gate count and operating frequency []. The deep-submicron (DSM) effects are becoming more prominent with shrinking technology, thereby increasing the probability of timing-related defects [2] [3]. For DSM designs, the stuck-at fault test alone cannot ensure high quality level of chips. In the past, functional patterns were used for at-speed test. However, functional testing is not a viable solution because of the difficulty and time to generate these tests for complex designs with very high gate density. Moreover, the number of required patterns to achieve high fault coverage can be extremely high for modern designs. Therefore, more robust at-speed techniques are required as the number of timing-related defects is growing and effectiveness of functional and I DD testing is reducing [4] [5]. The transition fault and path delay fault testing together provide a relatively good coverage for delay-induced defects [6] [7]. Path delay model targets the cumulative delay through the entire list of gates in a pre-defined path while the transition fault model targets each gate output in the design for a slow-torise and slow-to-fall delay fault [8]. Transition fault testing is widely practiced in industry due mainly to its manageable fault count (two faults in each gate) and availability of commercial tools. To test a transition fault, a pattern first is applied to initialize the circuit and another pattern is applied to apply a transition at a target gate terminal. The response is observed at the outputs of the circuit under test (UT). Scan-based structural tests generated by an automatic test pattern generator (ATPG) are increasingly used as a cost-effective alternative to the at-speed functional pattern approach [5] [9]. To perform a scan-based transition fault test, a pattern pair V V2 is applied to the circuit-under-test. Pattern V is termed as the initialization pattern and V 2 as the launch pattern. V2 launches the signal transition ( or ) at the desired node. It also helps propagate the output transition to the output of UT (scan flip-flops or primary outputs). The response of the UT to the pattern V 2 must be captured at functional speed (rated clock period). The whole operation can be divided into 3 cycles: ) Initialization ycle (I), where the UT is initialized to a particular state (V is applied), 2) Launch ycle (L), where a transition is launched at the target gate terminal (V2 is applied) and 3) apture ycle (), where the transition is propagated and captured at an observable point. Various scan-based transition fault testing methods were proposed in literature [] [] [2]. Depending on how the transition is launched and captured, there are three transition fault pattern generation methods called launch-off-shift, launch-offcapture, and enhanced-scan. In the first method, referred to as launch-off-shift (LOS) [], the transition at the gate output is launched in the last shift cycle during the shift operation. Figure shows the path of transition launch in LOS method for a multiplexed-dff design; similar approach can be applied to an LS. The transition is launched from the scan-in pin () of any flip-flop in the scan chain. This activates the required transition at the target gate terminal which is propagated and captured through the functional path at an observable point (D) of any flip-flop in the scan chain. Figure shows the waveforms during the different cycles of LOS operation. The L is a part of the shift operation and is Paper. INTERNATIONAL TEST ONFERENE /$2. c 25 IEEE

2 D Figure. Figure 2. LK OMBO LOGI I L Scan in pattern i Scan out response i LK tf Scan in pattern i+ Scan out response i Launch-off-shift Transition Delay Fault Pattern Generation. LK OMBO LOGI I L Scan in pattern i Scan out response i D LK tf Scan in pattern i+ Scan out response i Launch-off-capture Transition Delay Fault Pattern Generation. immediately followed by a fast capture pulse. The scan enable () signal is high during the last shift and must go low to capture the response at the clock egde. The time period for to make this transition corresponds to the functional frequency. Hence, LOS requires the signal to be timing critical. Skewing the clock (LK) creates a higher launch-tocapture clock frequency than standard shift clock frequency. Saxena et al. [3] list more launch-off-shift approaches. Figure 2 shows the transition launch path of the second approach, referred to as launch-off-capture () method []. In this method, the transition is launched and captured through the functional pin (D) of any flip-flop in the scan chain. Since, the launch pattern V2 depends on the functional response of the initialization vector V, the launch path is less controllable due to which the test coverage is low. Figure 2 shows the waveforms of the method in which the launch cycle is separated from the shift operation. At the end of scan-in (shift mode), pattern V is applied and UT is set to an initialized state. A pair of at-speed clock pulses is applied to launch and capture the transition at the target gate terminal. This relaxes the at-speed constraint on the signal and dead cycles are added after the last shift to provide enough time for the signal to settle low. The third technique, known as enhanced scan [2] requires that two vectors V and V2 are shifted into the scan flip-flops simultaneously. The main advantage of this technique is that it simplifies ATPG and offers better coverage for both and LOS techniques, since it eliminates any dependency between V2 and V. Enhanced scan can also have a beneficial impact on test data volume, since more compact test patterns can be generated. The drawback on enhanced scan is that it needs hold-scan flops and is area-intensive, making it unattractive for ASI designs. Enhanced scan using hold-scan flops has been used in high-performance microprocessors where the area overhead of the technique is justified. The LOS method is preferable from ATPG complexity and pattern count view points when compared to method. In case of, a high fault coverage cannot be guaranteed due to the correlation between the two patterns, V and V2. As the design size increases, the fanout exceeds any other net in the design. The LOS constraints to be timing critical which makes it difficult to implement using low cost testers and on designs where the turn-around-time is critical [5]. That is the main reason that method has been widely practiced, especially on low cost testers [9]. Note that no at-speed signal is required for method. Techniques are required to improve the method s fault coverage. In this paper, we propose a technique to improve the fault coverage and reduce the pattern count by using an enhanced technique. It intelligently selects a subset of scan cells to be controlled by technique and the rest as scanpath. This improves the controllability of scan cells and detects some of the hard-to-detect-by- faults. Several techniques have been proposed to improve the LOS fault coverage but there has not been much work on the method to the best of our knowledge. In [4], a hybrid scan architecture is proposed which controls a small subset of selected scan cells by LOS and the rest are controlled by approach. A fast scan enable signal generator is designed which drives the LOS controlled scan flops. The ATPG method used is complex and current commercial tools do not support such a technique. Moreover, the selection criteria of the LOS-controlled scan flops determines the effectiveness of the method. In some cases, the number of patterns generated by the hybrid method exceeds the pattern count. The implementation of LOS method using low cost testers is presented in [5]. A local at-speed scan enable signal is generated using a slow enable signal generated by a low cost tester. A local scan enable generator is designed; it can be inserted anywhere in scan chain and the launch and capture information are encapsulated in test data and transferred into the scan chain. The proposed technique in [5] focuses only on LOS and its implementation on low cost testers. The technique has no impact on fault coverage and pattern count. A. ontribution and Paper organization In this paper, we propose a novel transition fault pattern generation technique called Enhanced (E). In this technique, the transition launch path is deterministically determined Paper. INTERNATIONAL TEST ONFERENE 2

3 SI A G2 D G3 S D SO SI A D G2 G3 S D SO B SI2 2 D G S2 (block) D Y G4 SO2 B SI2 2 D G S2 D Y G4 SO2 I I L L I I I L I lk 2 lk 2 Figure 3. onventional method. Figure 4. Enhanced (E) method. either through a functional path or a em scan path. This improves the controllability of scan chains, increases the fault coverage, reduces the pattern count. A new scan cell, called local scan enable generator (LSEG), generates the local scan enable signals (not at-speed), used to control the scan chain mode of operation. A subset of scan chains are used as functional paths (like conventional ) and the rest are used as scan paths. This is controlled by scan enable signal; note that depending on how the scan enable signal changes during the launch and capture cycle the scan chain will be controlled either as functional path or scan path only. In a functional path, pattern V2 is generated using the functional response of pattern V. In scan path, the pattern V2 is generated using the last shift but the responses are not captured using that scan chain. The scan enable control information for the launch and capture cycle is embedded in the test data itself. The LSEG cell has the flexibility to be inserted anywhere in the scan chain and the hardware area overhead is negligible. The rest of the paper is organized as follows. The basic idea behind enhanced is explained in Section II. Section III describes the local scan enable generation technique and operation of the LSEG cell. The scan insertion and the test pattern generation flow is discussed in Section IV. Section V explains a case study of a design with fault coverage analysis. The experimental results are presented in Section VI. Finally, concluding remarks are in Section VII. II. ENHANED LAUNH-OFF-APTURE The method utilizes the functional response of the circuit to launch the transition at a target gate terminal and propagate the fault effect to an observable point. Launching a transition through functional response is difficult due to controllability issues. We now explain the controllability of and describe how the s test coverage can be improved by increasing its controllability. Figure 3 shows a small example with two scan chains, S and S2, each consisting of two scan cells. The scan-in ports are SI and SI2 and the scan-out ports are SO and SO2, respectively. In this particular example, the two scan chains have independent scan enable signals and 2, respectively. onsider a slow-to-rise transition fault at the target node Y (see Figure 3). To launch a transition at the target fault site using, the scan cell S2 2 (suffix indicates the position from the scan-in port) must contain a logic at the end of the scan shift operation (V applied). The functional response of the circuit must be logic at the output of gate G which is required to launch a transition at Y during the launch cycle through the functional path as shown. To propagate the transition, the inputs of gate G4 other than the input Y must have a non-controlling value (). However, logic at the output of the gate G, blocks the propagation of the transition to an observable point. Therefore, the slow-to-rise transition fault at the target node Y is untestable by the conventional method. The scan enable signals are high during the shift operation and low during the launch and capture cycles (see Figure 3). In some cases, the controllability can be improved by using the scan path instead of the functional path. Figure 4 shows the same example in which the slow-to-rise transition fault at node Y, untestable using conventional method, is testable by controlling the launch path of the target transition fault using the scan enable signals. The transition at Y is launched through the scan path instead of the functional path. The remaining inputs of the gate G4 other than the target fault site Y are controllable to non-controlling value to propagate the transition. The new method is referred to as enhanced launchoff-capture (E). Figure 4 shows the scan enable signals and 2 during the shift (I), launch (L) and capture () cycles. In this method, the scan enable signal of the second scan chain 2 is kept constant at during both launch and capture cycles. In other words, the scan chain S2 is used only to shift bits, i.e, to launch transitions in the circuit. It acts like a shift register and does not capture any functional response of the circuit. The conventional method may be viewed as a special condition of the enhanced (E) method, where the scan enable signals of all the chains are during the launch and capture cycles. E provides more controllability of launching the transition either through the scan path or the functional path. Note that, the scan enable () signals do not change between the launch and capture cycles and any scan enable Paper. INTERNATIONAL TEST ONFERENE 3

4 SI SO G OMBO LOGI [] G LSEG A Figure 5. ontrollability of Enhanced. L transition is at shift frequency. Figure 5 shows a circuit with two scan chains, one acting as a shift register and the other in the functional mode. The transitions in the first scan chain are launched through the functional path while the transitions from the second scan chain are launched from the scan path III. AL SAN ENABLE SIGNAL (L) GENERATION The enhanced method provides more controllability to launch a transition but requires independent scan enable signal for each scan chain. Multiple ports can be used, but this increases the number of pins. The scan enable control information for all the scan chains differ only during the launch and capture cycles of the pattern. Hence, the scan enable signal from the external tester can be utilized for the scan shift operation and the scan enable control information for only the launch and capture cycles can be generated internally. The local scan enable generator cells are inserted within the scan chains. Therefore, the control information is to be passed as part of the test data. The scan enable control information will be part of each test pattern and is stored in the tester s memory. The normal scan architecture with a single scan enable signal from the external tester is shown in Figure 6. There are eight scan flip-flops in the scan chain and the test pattern shifted is. The external scan enable signal from the tester is referred to as the global scan enable (G). Figure 6 shows the same circuit in which a local scan enable signal is generated from the test pattern data for the enhanced method. The internally generated scan enable signal is termed as local scan enable (L). The main objective is to de-assert G after the entire shift operation and then generate the L signal during the launch and capture cycle from the test data. In this case, the pattern shifted is modified to [], where is the scan enable control bit which is stored in scan flip-flop A at the end of the scan operation. One extra scan flip-flop (A) and an OR-gate are added for the generation of L signal. The output of A is ORed with G to generate the L signal (see Figure 6). Note that G is not an at-speed signal. The G signal asynchronously controls the shift operation. The values of the scan flip-flops during the various shift cycles are shown under each flip-flop. G is de-asserted after the nth shift (I) cycle, where n=9. n is the length of scan chain after inserting new cell A. After the G signal is de-asserted at the end of the shift operation, the scan enable control during the launch and capture cycles is the control bit stored in A. At the end of the capture cycle, the L signal is aysnchronously set to by G for scanning out the response. Figure 6(c) shows the detailed pro- LK G L = (G+A) (c) I L Figure 6. Scan chain architecture, Local scan enable (L) generation and (c) L generation process. cess of shifting the test pattern into the scan chain and also the timing waveforms. In general: if G= L G A A if G= A. Local Scan Enable Generator (LSEG) As explained earlier, during the launch and capture cycles of the pattern, the control bit shifted into scan flop A is used as the scan enable control. Figure 7 shows the LSEG cell architecture. It consists of a single flop which is used to load the control information required for the launch and capture cycles. The port definition is similar to a scan cell and the output of the flop is fed back to the functional input port of the flip flop. It consists of a scan-in ( in ) pin which takes G signal as input. An additional scan-out ( out ) pin (G ) represents the L signal. Therefore, after going to a control state () at the end of the shift operation (G is de-asserted), L remains in this state as long as it is asynchronously set to by G. Table I shows the different modes of operation of LSEG cell. G represents the normal shift operation of the pattern. When G and, L and the scan chain acts in the shift mode to launch the transitions (Shift-Launch mode). The scan chain acts in the conventional method when G and (Functional-Launch mode). Note that the LSEG cell can be inserted anywhere in the scan chain and it is not connected to the UT. Hence, it has no impact on the functional timing and the UT fault coverage. The LSEG cell provides a simple mechanism to generate the local internal scan enable signals. But, it has a shift dependency for the following flop in the shift register mode. If, the LSEG flip-flop is constant at for the launch and capture cycles and the flip-flop following the LSEG cell can generate Paper. INTERNATIONAL TEST ONFERENE 4

5 Pattern: [] LSEG LK in (G) D FF : [] LK I A L in (G) (FF) out (L) out (L) Figure 7. Local scan enable generator (LSEG) cell. TABLE I E: [] Scan in pattern i Scan out response i Scan in pattern i+ Scan out response i LSEG OPERATION I L G FF L Operation X Shift Shift-Launch Functional-Launch only a transition at its output. This may result in loss of coverage for faults which are in the logic cone and require a transition on the flip-flop following the LSEG cell. In order to avoid loss of coverage without significant change in the architecture, the LSEG cell is modified such that the LSEG cell when loaded with the control bit, the cell will remain in this state and it is not in the shift path during the launch and capture cycles for. Figure 8 shows the modified LSEG cell architecture. It consists of an additional multiplexer and it does not impact the functional path timing. When G, the LSEG cell is by-passed and the pin is directly connected to. In the Shift-Launch mode, the value from the previous flip-flop of LSEG cell is shifted into its following flip-flop. B. Operation of LSEG cell Figure 9 shows the previous example with the LSEG cell inserted in the scan chain. The value loaded in the LSEG flipflop is represented as ([]) in the test pattern. Figure 9 shows the pattern and the timing waveform for the conventional method. The in (G) signal is asynchronously de-asserted at the end of the shift operation. The out (L) signal is generated by the boolean equation out FF in. The G signal is high during the entire shift operation. At the end of the shift operation, the Figure 8. in (G) D FF LK out (L) Modified Local scan enable generator (LSEG) cell. LK in (G) (FF) out (L) Scan in pattern i Scan out response i (c) Scan in pattern i+ Scan out response i Figure 9. Operation of LSEG cell, Scan chain, onventional and (c) Enhanced. G signal is asynchronously deasserted and the L signal must be logic. Hence, the LSEG cell flip-flop must be constrained to during atpg. After the capture cycle, the L signal is asynchronously asserted back by G. For enhanced, similar to conventional, the G signal is high during the entire shift operation. At the end of the shift operation, the L signal is determined by the control bit () shifted into the LSEG cell flip-flop during the pattern shift. Figure 9(c) shows the pattern and the timing waveform for enhanced. The L signal is constant at logic value during the launch and capture cycle. It can be noticed that the L transitions are not at-speed. After the capture cycle, the L is asserted to asynchronously by G. A. Test Architecture IV. DFT INSERTION AND ATPG FLOW The LSEG-enabled solution explained in Section III provides a method of generating internal local scan enable signals from the pattern data and global scan enable signal from the external ATE. The overhead of generating the local scan enable signal is the addition of an LSEG cell in the scan chain. The area overhead of an LSEG cell is a few extra gates, which is negligible in modern designs. The methodology is applicable to designs with multiple clock domains. In general, there can be multiple scan chains in a design to reduce the test application time as this is the case for today s commercial compression tools. The test application time is directly proportional to the longest scan chain length in the design. Figure shows a multiple scan chain architecture with n scan chains. Each scan chain i, where i n, consists of an LSEG cell which generates the local scan enable signal L i for the respective scan chain. The G signal connects only to the in port of LSEG cells. Paper. INTERNATIONAL TEST ONFERENE 5

6 Figure. LSEG Test Architecture. 2 3 n G : for set i $i no chains incr i 2: 3: create cell LSEG$i LSEG 4: set scan segment scan segment$i 5: -access test scan in LSEG$i/, test scan out LSEG$i/ 6: -contains LSEG$i/FF 7: connect net G find( pin, LSEG$i/ IN) 8: connect net LK find( pin, LSEG$i/LK) 9: set scan path c$i LSEG$i -dedicated scan out true : set scan signal test scan enable -port G : -hookup find( pin, LSEG$i/ OUT) -chain c$i 2: Figure. B. DFT Insertion DFTompiler Tcl Script commands. Synopsys DFTompiler [7] was used for scan chain insertion in the design. We inserted one LSEG cell per scan chain. To insert the LSEG cells, additional commands are required during the scan chain configuration. Figure shows the list of additional commands in the tcl script required during scan insertion. The synthesis tool must recognize the LSEG cell as a scan cell in order to stitch it into the scan chain. This requires it to be defined as a new library cell with the scan cell attributes. A workaround is to design the LSEG cell as a module and declare it as a scan segment of length using the set scan segment command (line 4). The G signal is connected to all the LSEG cells in input pin. To make the insert scan command insert the LSEG cells in the scan chain, set scan path command must be used to declare the scan path (line 9) including the LSEG cell. Only the LSEG cell is specified in the scan path, as the tool will stitch the rest of the cells including the LSEG cell and balance the scan chain depending on the longest scan chain length parameter defined in the set scan con f iguration command. The set scan signal command (line ) is used to hookup each LSEG cell s out port in a particular chain to all the scan enable input port of the scan flops in the respective chain.. ATPG The E method provides better controllability to launch a transition fault either through the scan path or the functional path. The ATPG tool must be able to understand the local scan enable generation methodology and deterministically decide the transition fault activation path. ommercial ATPG tools were used for test pattern generation. A test pattern generation tool supports two ATPG modes: ) Basic-Scan and 2) Sequential. Basic-Scan ATPG is a combinational-only mode with only : load unload 2: W slow WFT ; 3: V LK =; LK2 =; LK3 =; 4: LK4 =; LK5 =; LK6 =; G =; 5: Shift 6: W slow WFT ; 7: V LK =P; LK2 =P; LK3 =P; 8: LK4 =P; LK5 =P; LK6 =P; G =; 9: so =#; si =#; : : //ADDING DEAD K YLE 2: V LK =; LK2 =; LK3 =; 3: LK4 =; LK5 =; LK6 =; G =; 4: 5: capture LK 6: W LK WFT ; 7: V pi = r33 #; po = j r43 #; LK =P; 8: Figure 2. ATPG test protocol file. one capture clock between pattern scan-in and scan-out of response while the Sequential mode uses sequential time-frame ATPG algorithm. By default, when generating test patterns for transition fault method, the commercial ATPG tools use a two-clock ATPG algorithm that has some features of both the Basic-Scan and Sequential engines. The tool understands the local scan enable generation technique using LSEG cells and is able to decide the launch path for the target transition fault deterministically. Hence, there is no fundamental difference in the ATPG methodology when we use the LSEG-based solution. The scan enable signal for the flip-flops for the launch and capture cycles now comes from an internally generated signal. Notice that the OR gate in the LSEG cell generates the local scan enable signal through a logical OR of the global scan enable and the output of the flop FF (see Figure 8). The global scan enable signal is in active mode during scan shift operation. The tool determines the local scan enable for each chain and shifts the control value into the LSEG cell during pattern shift, used for launch and capture. It also deterministically decides the combination of scan chains to work in Shift-Launch mode, to activate a transition fault. Figure 2 shows an example test protocol file with load unload procedure and one named capture procedure for clock LK. Each vector statement (V) is a tester clock cycle. The waveform table statement (W) determines the clock period of the tester clock cycle defined in the timing waveform procedure of the test protocol file. The waveform table slow W FT is the slow shift clock cycle and LK WFT is the at-speed clock cycle. The entire shift operation is performed at slow shift clock period. The G signal is high until the nth shift and is made low in the dead cycle after the last shift which provides enough time for G to go low. The waveform timing is changed to LK W FT in the named capture procedure before the V statement. By using named capture procedures, only a specific clock can be made active during the launch and capture cycles. As explained in Section II, in the conventional method the scan enable signal is zero during the launch and capture cycles. The LSEG cell must be loaded with logic at the end of the shift operation for conventional method. ell constraints can be used to control the load values allowed on LSEG cells. The ATPG tool creates only patterns that satisfy the cell Paper. INTERNATIONAL TEST ONFERENE 6

7 TABLE II ATPG Post process (Mask scan chains in Shift Launch Mode) DESIGN HARATERISTIS lock Domains 6 Scan hains 6 Scan Flops 477 Non-scan Flops 3 Transition Delay Faults Figure 3. E ATPG flow. Fault Simulate Modified Pattern Set constraints. The enhanced method does not require any cell constraints. The ATPG tool generates patterns based on the controllability of the target fault site. During E pattern generation, the ATPG tool deterministically decides the value of LSEG cell which determines the L signal depending on the transition fault activation path. In the ASI market, the design sizes are extremely large and the shift frequency is proportional to functional frequency. While generating patterns, the ATPG tool is unaware of the timing of the design. During E, if a scan chain is used in a Shift-Launch mode, the ATPG tool will shift data in the scan chain during the L and I cycles at functional frequency. This may cause a problem as the scan chain may not be closed for functional frequency. Since the scan chain is used only to launch the transitions in Shift-Launch mode, it does not contribute to the fault coverage. Hence, all the scan chains that are operating in Shift-Launch mode can be masked for that particular pattern. The operation mode of the scan chain need to be found by the value of the LSEG cell in the pattern. Figure 3 shows the E ATPG flow. The generated patterns are postprocessed to mask the particular scan chain with the LSEG cell value equal to. The modified pattern set is again fault simulated for coverage analysis. In future, if the ATPG tool is enhanced to mask the scan chains that are not observable, the post processing step can be skipped. V. ASE STUDY In this case study, we experimented with a subchip of an industrial-strength design that had the following characteristics (Table II). The design has 6 scan chains and approximately K scan cells. There are 3 non-scan cells and six internal clock domains. One LSEG cell is inserted per scan chain. The test strategy is to get the highest possible test coverage for the transition faults. When generating test patterns for the transition faults, we target only the faults in the same clock domain. During pattern generation, only one clock is active during the launch and capture cycle. Hence, only faults in that particular clock domain are tested. All PIs remain unchanged and all POs are unobservable while generating the test patterns for the transition faults. This is because the very low cost ATEs are not fast enough to provide the PI values and strobe POs at speed. TABLE III ATPG RESULTS onv. Enhanced LOS Detected faults Test overage Fault overage Pattern ount PU Time [sec] A. Fault overage Analysis The results for conventional, enhanced and LOS transition-delay ATPG on this design are shown in the Table III. We see that LOS methodology gave approximately 2% higher fault coverage than the conventional methodology. The E method gave approximately.9% higher fault coverage compared to method. The number of patterns generated is also less due to better controllability in E method. The PU time of E method is greater than as the ATPG tool has to do more processing to determine the possible combinations of the scan chains to work in shift register mode or in functional mode. Figure 4 shows the fault coverage analysis for the three different transition fault methods. There is a common set of transition faults which are covered by both LOS and and there are some faults in the transition fault set which are not covered by LOS. However, E covers the entire transition fault set of and also detects some extra faults which fall in the LOS set. This is because, is a special case where all the LSEG cells are constrained to during ATPG. The new E method provides an intermediate fault coverage point between LOS and the conventional method. The test coverage curves for LOS, and E are shown in Figure 5. The improvement in E coverage can be seen due to greater controllability. Figure 6 shows the number of patterns required by, E and LOS methods for the highest coverage achieved for method in all three cases. For the design under consideration, we found that only 92 patterns of E method offered the same coverage as con- Figure 4. AU Fault overage Analysis. LOS E Paper. INTERNATIONAL TEST ONFERENE 7

8 LOS E Y LOGI 9 Test overage (%) 8 7 Figure 8. SI apture dependent untestable. SO Figure No. of patterns Transition overage for, E and LOS. SI2 SI3 SI4 SO2 SO3 SO4 G 25 Figure E LOS omparison of no. of patterns in, E and LOS. ventional method. This represents a pattern reduction of about 52% compared to conventional. B. Shift and apture-dependent Untestable Faults There are two types of untestable faults which will affect the E coverage. Figure 7 shows a circuit with four scan flipflops FF, FF 2, FF 3 and FF 4 which drive a set of AND gates. In E method, if this scan chain is used as a shift-register to launch a transition at node Y, activation and propagation of the fault is not achievable since all the three scan flip-flops are required to be for propagation. For transition fault activation, if FF (FF 2 ) is loaded with a during I, then the at FF (FF 2 ) shifts to FF 2 (FF 3 ) during the L which conflicts with the value in all flip-flops to propagate the fault effect. These type of untestable faults are referred to as shift dependency untestable. In [6], dummy flip-flops are inserted to break the shift dependency between selected pairs of adjacent flip-flops in the scan chain. However, we do not address this problem in this paper as these kind of faults are common to both E and LOS. In E, in case a scan chain is used as a shift-register to Figure 7. FF > Y FF2 Shift dependent untestable. FF3 FF4 Figure 9. Top level scan insertion flow. launch a target transition fault and if the fault is observable at a scan flip-flop in the same chain, then the fault cannot be captured and is referred to as capture dependency untestable. Figure 8 shows an example of such a type of untestable fault. Since, the scan chain is only controllable and not observable while it is acting as a shift register, the fault cannot be captured. The scan flip-flops can be rearranged to break the capture dependency but it may increase the scan path routing overhead. Moreover, the scan chain flip-flops will be re-oredered during the physical design step. Another solution to break the capture dependency is to insert multiple LSEG cells per scan chain. This will provide better controllability of different sections of the scan chain.. LSEG Insertion Flow There are two issues relating to insertion of multiple LSEG cells, ) the number of LSEG cells, 2) insertion flow of LSEG cells (module level or top-level). If there is a large difference between the fault coverage between E and LOS, then one reason might be that there is a large number of capture dependency faults in the design. The capture dependency can be broken by re-arranging the scan flip-flops between the scan chains. Since, the scan insertion tool is not aware of the LSEG methodology, the test engineer should analyze the capture dependency untestable faults and determine the number of LSEG cells to be inserted. For this particular design, we experimented by inserting three LSEG cells and the E method gave about 2.3% higher fault coverage than compared to.9% percent coverage improvement for one LSEG cell per scan chain. Moreover, the LSEG insertion method is not affected by re-ordering of the scan flip-flops during the physical design. The DFT insertion described in Section IV-B is applicable for insertion of one LSEG cell per scan chain. This is a limitation of the scan insertion tool as there is no way to direct the tool to control the different parts of the same scan chain. There are two widely used scan insertion flows, ) Top-level scan insertion flow and 2) Bottoms-Up scan insertion flow. For smaller designs, the preferred flow is top-level scan insertion and for large designs, the bottoms-up scan insertion flow is followed. Fig- Paper. INTERNATIONAL TEST ONFERENE 8

9 BK A BK B TABLE IV DESIGNS HARATERISTIS BK BK D G Design Scan ells # hains locks TF UF RF A B D E F G H Figure 2. Bottoms Up scan insertion: Flow. BK A BK B TABLE VI OMPARISON OF METHODOLOGIES G Methodology Effort F Pattern ount Low Low High LOS High High Low LOS LT G [5] Medium High Low E Low Medium Medium BK Figure 2. Bottoms Up scan insertion: Flow 2. BK D ure 9 shows the top-level scan insertion with multiple LSEG cells per scan chain. For a design with N scan chains and M LSEG cells to be inserted per scan chain, the scan insertion tool is directed to insert N M scan chains with one LSEG cell per scan chain. In the next step, the scan chains are re-stitched into N scan chains. For example, if N 4 and M 2, there are 8 scan chains inserted with one LSEG cell per scan chain and later these chains are re-stitched into 4 chains at top-level. As the designs presently are large and often reuse IPs, the scan insertion is done at submodule level and then these chains are connected at the top level. It is also referred to as bottomsup approach. Figure 2 shows the first flow where the submodules are inserted with scan chains, each with an individual scan enable control signal. The LSEG cells are inserted manually between the submodules and the scan chains are stitched at the top-level. The second approach is to insert the submodules scan chains with LSEG cells and stitch the the scan chains at the top level (Figure 2). This is a preferrable approach, as the test engineer will only be required to hookup the scan chains appropriately and need not worry about LSEG cell insertion. VI. EXPERIMENTAL RESULTS We have experimented on eight industrial designs and Table IV shows the characteristics of these designs. In all designs, each scan chain is inserted with one LSEG cell. The total transition faults are shown in column TF. During ATPG, the faults related to clocks, scan-enable and set/reset pins, referred to as untestable faults (UF), are not added to the fault list. The clock related faults can only be detected by implication and the remaining faults (scan-enable/set/reset) are untestable as the signals remain unchanged during the launch and capture cycles. These faults contribute approximately -5% of the total transition faults. The total transition faults excluding UF faults is used as the real fault (RF) set during pattern generation. Table V shows the ATPG results comparing and E methods. The DT, F, # Patt columns shows the detected faults, the fault coverage percentage and the number of patterns generated respectively for each method. Note that the PU time for E method is greater than method since the tool has to do additional processing to find the transition launch activation path. The DT are the extra faults detected by the E method. The E method provides higher fault coverage upto 87% ( F) compared to method and also for a given fault coverage, the number of patterns generated by E is less in all designs. The ( Patt) column is the percentage pattern reduction for the maximum fault coverage achieved by method. Figure 22 shows the number of patterns in both methods for the highest fault coverage achieved. In all cases the E method generates a smaller pattern set as the controllability of transition launch has increased. Patt E F max The LSEG-based solution provides better fault coverage and pattern count with a simple addition of a LSEG cell controlling the scan path. On an average, the E gives 72% higher fault coverage compared to conventional method. The fault coverage of E method can be increased further by careful scan insertion. Presently, the scan insertion tool stitches the scan cells based on the lexical naming convention of the scan flops. The best results in terms of fault coverage can be obtained, if the scan insertion tools can stitch the chains such that the inter-scan chain faults are increased. However, irrespective of scan chain order, the pattern volume reduction is achieved due to improved controllability. Table VI shows a qualitative analysis of the different transition fault methodologies. The parameters compared are the scan enable effort during physical design (PD), fault coverage and the pattern count. The conventional and the E Paper. INTERNATIONAL TEST ONFERENE 9

10 TABLE V ATPG RESULTS FOR EIGHT INDUSTRIAL DESIGNS. Design E DT F (%) # Patt PU Time [sec] DT F (%) # Patt PU Time [sec] DT F (%) Patt (%) A B D E F G H Figure 22. designs E E E E E E E E A B D E F G H omparison of no. of patterns in, E and LOS for all method require the least effort as it is not at-speed. The LOS method requires the signal to work at functional speed and takes high effort. In [5], the entire scan enable tree is divided into sub-trees and the local scan enable for each sub-tree is generated internally. This reduces the effort during the PD step. The E method provides an intermediate fault coverage and pattern count between the conventional method and LOS method. VII. ONLUSION In this paper, a new method of transition fault testing, referred as enhanced launch-off-capture, has been proposed which provides better controllability than the conventional launch-off-capture method. testing is known to provide less quality results, both in terms of pattern count and fault coverage, but design teams may not use launch-off-shift due to the challenge of routing the scan enable signal. Our solution is to generate local scan-enable signals that control the transition launch path; for this purpose, we rely on embedding some scan enable control information in the patterns. We use a special cell called the LSEG cell for the generation of the local scan enable signal. This cell is simple to design and layout, and its area overhead is comparable to that of a scan flop. The number of LSEG cells inserted in the design will be small, thereby making the area overhead due to our technique negligible. The LSEG-based solution provides greater flexibility and controllability for transition fault pattern generation. The DFT insertion and ATPG can be easily performed using the commercial ATPG tools; therefore our solution is easy to practice. AKNOWLEDGEMENTS We thank Ken Butler of Texas Instruments for useful discussions during the course of this work and feedback on the initial draft of the paper. The work of M. Tehranipoor was supported in part by SR Grant No. 25-TJ-322. REFERENES [] International Technology Roadmap for Semiconductors 2 ( [2] S. Natarajan, M.A. Breuer, S.K. Gupta, Process Variations and Their Impact on ircuit Operation, in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 73-8, 998. [3] R. Wilson, Delay-Fault Testing Mandatory, Author laims, EE Design, Dec. 22. [4] G. Aldrich and B. ory, Improving Test uality and Reducing Escapes, in Proc. Fabless Forum, Fabless Semiconductor Assoc., pp , 23. [5] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, High-Frequency, At-Speed Scan Testing, IEEE Design & Test of omputers, pp. 7-25, Sep-Oct 23. [6] K. heng, Transition Fault Testing for Sequential ircuits, IEEE Transactions on omputer-aided Design of Integrated ircuits and Systems, vol. 2, no. 2, pp , Dec [7] T. M. Mak, A. Krstic, K. heng, L. Wang, New challenges in delay testing of nanometer, multigigahertz designs, IEEE Design & Test of omputers, pp , May-Jun 24. [8] M. Bushnell, V. Agrawal, Essentials of Electronics Testing, Kluwer Publishers, 2. [9] V. Jayaram, J. Saxena and K. Butler, Scan-Based Transition-Fault Test an Do Job, EE Times, Oct. 23. [] J. Savir, Skewed-Load Transition Test: Part I, alculus, in Proc. Int. Test onf. (IT 92), pp , 992. [] J. Savir and S. Patil, On Broad-Side Delay Test, in Proc. VLSI Test Symp. (VTS 94), pp , 994. [2] B. Dervisoglu and G. Stong, Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement, in Proc. Int. Test onf. (IT 9), pp , 99. [3] J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. ampbell, J. Berech, Scan-Based Transition Fault Testing - Implementation and Low ost Test hallenges, in Proc. International Test onference (IT 2), pp. 2-29, Oct. 22. [4] S. Wang, X. Liu, S.T. hakradhar, Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault overage and ompact Test Sets, in Proc. Design, Automation and Test in Europe (DATE 3), pp , 24. [5] N. Ahmed,.P. Ravikumar, M. Tehranipoor and J. Plusquellic, At-Speed Transition Fault Testing With Low Speed Scan Enable, in Proc. VLSI Test Symp. (VTS 5), pp , 25. [6] J. Savir and S. Patil, Scan-Based Transition Test, IEEE Transactions on omputer-aided Design of Integrated ircuits and Systems, vol. 2, no. 8, pp , Aug [7] Synopsys DFT ompiler, User Manual for SYNOPSYS Toolset Version 24.6, Synopsys, Inc., 24. Paper. INTERNATIONAL TEST ONFERENE