PO2030N 1/4.5 Inch VGA Single Chip CMOS IMAGE SENSOR. Last update : 28. Feb. 2005

Transcription

1 2030N Data sheet (Brief) ixelplus Co.,Ltd 2030N 1/4.5 Inch VGA Single Chip CMS IMAGE SENSR Last update : 28. Feb IXELLUS C,. LTD Kyunggi Verture B/D 502,#1017 Ingae Dong aldal-ku Suwon city Kyunggi-do, Korea Tel : , FAX : Copyright 2005, ixelplus Co.,Ltd ALL RIGHTS RESERVED age 1 of 9

2 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor Features 1/4.5 inch 640 X 4 80 acti ve pixel array with color filters and micro-lens. owe r supply 2.5V for core and 2.5 ~ 2.8V (Max. 3.1V) fo r I/. utput formats : 8bit YCbCr / 9Bit Bayer data / 5:6:5 RGB, 12bit 8:8:8 RGB / 8bit Y 30 frames/sec prog ressive MHz master clock. Image processing on chip : lens shading, gam ma correction, de fect correction, low pass filter, color interpolation, edge enhancement, color corr ection, contrast stretch, color saturation, white balance, exposure control and back light compensation. Still image capture with electrical or mechanical shutter. Frame size, window size and position controllable through a serial inte rface bus. VGA / QVGA / QQVGA Scaling. Horizontal / Vertical mirro ring. 50Hz, 60Hz flicker cancellation. ackage : 40 pin CLCC, 32 pin CS AGND D6 D7 D8 D9 D10 D11 RSTB AVDD AVDD IXELLUS C,. LTD AGND REF HVDD D5 D4 REFN STDBY SDA D3 D2 D N SYNC SCL HVDD VDD GND D0 V SYNC HSYNC CLK X1 N.C Table 1. Typical aram eters ixel Arra y 648 X 488 ixel Size Im age Area Clock Rate Frame rate Dark Current Sensitivity Saturation Level Conversion Gain 5.2um X 5.2um 3.37mm X 2.54mm 27 MHz (Max.) Variable up to 30fps 0.3 na/ cut filter 770 mv Fill Factor 40 % Supply voltage 15~50 /electrons 2.5~2.8V I/,2.5V Core ower consumption active HVDD=2.8V,Core=2.5V 30 tandby peration Temp. -30 ~ 40 < Figure. 1> in Diagram Dynamic Range 68 db ackage 40 pin CLCC, 32 pin CS 2/9 age 2 of 9

3 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor IN Descriptions in No. Name I/ Type Functions / Descripti ons IXELLUS C,. LTD D10 D11 RSTB AVDD AGND CREF_ CREF_N STDBY SDA SYNC SCL HVDD N.C X1 I I I/ I - I Bit 10 of data output. Luminance data Y<7:0> are mapped to output p ins D<11:4>. Chrominance data UV<7:0> are also mapped to outp ut pins D<11:4>. Bayer RGB data are mapped to output pinsd<11:2>. Bit 11 of data output. System reset must remain low for at least 8 master clocks after power is stabilized. When the sensor is reset, all registers are set to their default values. Digital ground. Core and I/ c ircuits share the ground pads. Analog vdd : 2.5V DC. 100nF capacit or to AGND. Analog ground. ADC reference voltage. 100nF capacitor to AGND. ADC assumes V(REF) V(REFN) is the minimum input voltage that will be conv erted to 1FFh. ADC reference voltage. 100nF capacitor to AGND. ower standby mode. When STDBY= 1 there s no current flow in any analo g circuit branch, neither any beat of digital clock. D<11:0> and CLK, HSYNC, VSYNC pins can be programmed to tri-state or all 1 or all 0. MCLK must be fixed t o 1 or 0 after STDBY is set to 1 to avoid t he leaka ge current. All registers retain t heir current valu es. I2C serial data bus. Mechanical Shutter Close command utput. I2C serial clock input. Digital vdd for I/ : DC 2.5~3.1V. Voltage range for all outp ut signals is 0V ~ HVDD. Digital vdd for core lo gic : 2.5 V DC. 100nF capacitor to. Digital ground for core and I/ circuits. No Connection Master clock : Crys tal input pad. Digital ground. Table 2-1. IN Des criptions age 3 of 9 3/9

4 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor in No CLK HSYNC VSYNC D0 ixel clock. Data can be latched by external devices at the rising or falling ed ge of CLK. The p olarity can be controlled anyway. Horizontal synchroniz ation pulse. HSYNC is high ( or low ) for the horizontal window of interest. It can be programmed to app ear or not outside the vertical window of interest. Vertical sync : Indicat es the start of a new frame. Bit 0 of data output. IXELLUS C,. LTD Name GND VDD D1 D2 D3 D4 D5 HVDD AVDD AGND D6 D7 D8 I/ Type Functions / Descripti ons Digital vdd : 2.5VDC. 100nF to Ground for pixel array. ixel array current is supplied from VDD : 2.5VDC. 100nF to AGND Digital ground. Digital vdd : 2.5VDC. 100nF to Bit 1 of data output. Bit 2 of data output. Bit 3 of data output. Bit 4 of data output. Bit 5 of data output. Vdd for I/ : 2.5~3.1V Digital vdd : 2.5VDC. 100nF to Analog vdd : 2.5V DC, 100nF to AGND Analog ground. Bit 6 of data output. Bit 7 of data output. Bit 8 of data output. 40 D9 Bit 9 of data output. Table 2-2. IN Description 4/9 age 4 of 9

5 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor Block Diagram Analog Control signal Row decod er Bias / AD C cont rol Digital Control signal ixel array 648 X 488 CDS<0:647> ADC<0:647> Column decoder Digital Control signal <Figure. 2> Block Diagram 2030N has 648 x 488 effective pixe l array and column/row driver circuits to read out the pixel data progressively. CDS c ircuit reduces noise signals generated from various sources ma inly res ulting from process variations. ixel output is compared with the reset level of its own and only the difference signal is sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain factors to balance the color of images in various light conditions. The analog signals are converted to digital for ms one line at a time and 1 line data are streamed out column by column. The Bayer RGB data are passed through a sequence of image signal proces sing blocks to finally produce YCbCr 4:2:2 output data. Image s ignal processing includes such operations as gamma correction, defect IXELLUS C,. LTD correction, low pass filter, co lor interpolation, edge enhancement, color correction, contrast stretch, color s aturation, white balance, exposure control and back light compens ation. Internal functions and output signal timing can be progra mmed simply by modifying the register files through I 2 C serial interface. Bayer RGB 9 p clk ST DBY RST B X1 Timing control H sync Image Signal rocessing Vsync D ata 9 Control register I 2C Reg isters 8bits Y/UVor 9bits Bayer CLK HSYNC VSYNC SDA SCL age 5 of 9 5/9

6 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor Electrical Characteristics Absolute Maximum Ratings * VDD Supply Voltage V to 3.5V DC Voltag e at any input pin V to VDD+0.3V DC current at any input pin mA to +10mA Storage Te mperature ?C to +125?C Table 3. DC Chara cteristics IXELLUS C,. LTD Iot utput leakage current ua ua (1)Core power is recommended to 2.5V for image quality. If lower than 2.5V, dynamic range can be decreas ed and if higher than 2.5V, the image quality can be degraded due to the color noise. * Excessive stresses may cause permanent damage to the device. age 6 of 9 6/9

7 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor Table 4. AC Chara cteristics ( All outputs : 15pF load conditions ) MCLK HSYNC D<9:0> t4 CLK 50% IXELLUS C,. LTD MCLK t3 T t5 T = 1/f MCLK T Fig. 13 Clock, Data, and Sync Timing. t5 t1 10% 90% t2 RESET t6 age 7 of 9 7/9

8 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor Table 5. Electro- ptical Chara cteristics Symbol arame ter Note s Min Typ Ma x Unit Sens Vsat Vdrk SNU DR Sensitivity Saturation Level Dark Signal IXEL Signal NN- Uniform ity Dynamic range 1) 2) 3) 4) 5) IXELLUS C,. LTD V/Lu x.sec Notes : 1) Measured sensitivity of Green pixel at 1.5lux illumination fo r 66ms integration time Test area is the 128x9 6 of center area 2) For =550 wavelength 3) Measured at the zero illumination for 66ms at the 40 degree (1) read the dark signal average of all pixels (640x480) fo r 66ms ( 2) read the dark signal average of all pixels (640x480) for 0.132ms ( 3) Dark (2) ( 4) convert to mv unit 4) For 16X12 pixel region unde r illumination with o utput signal equal to 50% of saturation of center area. Max value o f Block Min value of Block Average value of all blocks 5) For fram e rate = 15 fps 20*Log (Saturation Signal / Dark signal) [db] X 100 V m V % db age 8 of 9 8/9

9 ixelplus 2030N CMS Image Sensor with 640 X 480 ixel Array and Integrated n-chip Image Signal rocessor CLCC40in ackage Specification INDEX MARK (Ø 0.25) (R0.20) (4X) 1.78 ± ±0.13 (39X) 3.80 (C0.15) (N.1 INDEX) (R0.20) (8X) 10.16SQ. N.1 N ±0.10 N.40 C0.30 (N.1 INDEX) N (40X) 0.42 (40X) 0.68 (36X) C0.30 (8X) 0.40 ± A 0.05 IXELLUS C,. LTD 0.85 ±0.05 (R-0.15) (40X) 7.65 ±0.13 (=0.85X9) A ± ±0.08 (40X2) 0.40 ± NTE: 1. NI 2.0um + Au 0.5um MIN 2. N METALLIZATIN N SEAL R ING AND DIE ATTACH AD. 3. UNIT : mm 9/9 age 9 of 9