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1 Project GRANT AGREEMENT NO. ACRONYM TITLE CALL FUNDING SCHEME TITLE WIDE_SENSE WIDE SPECTRAL BAND & WIDE DYNAMICS MULTIFUNCTIONAL IMAGING SENSOR ENABLING SAFER CAR TRANSPORTATION FP7-ICT STREP Document identification D2.4 - ROIC FOR WIDE DYNAMICS FULL SPECTRUM FPA DISSEMINATION STATUS PUBLIC DUE DATE 31/07/2011 DELIVERABLE D2.4 ISSUE 1 PAGES 17 WP/TASK WP2 / T2.3 WP TITLE FPA DEVELOPMENT PARTNER IN CHARGE NIT EXECUTIVE SUMMARY - The Read Out circuit fulfils all the initial requirements, in terms of resolution, frame rate, noise and overall dimensions (package compatibility). The Tape Out to the Fab was done at mid July 2011, and the wafer Out was at mid September After the assembly phase, the chip was tested in NIT Lab early October. - Visual performance in visible spectra (with on chip parasitic photodiodes) is remarkable. This first test opens the way to the hybridisation step in order to extend the sensitivity from visible to SWIR domain. - This work is the main step for the 2WS project, as long as it provides the bulk of the sensor used to capture road videos. After hybridisation, the FPA will hopefully become a benchmark in Visible- SWIR WDR sensing. Specific features included in the ROIC (FPN onchip compensation, temperature sensing, dead pixel removal, low power architecture, differential low-noise output, etc) have an important contribution to the overall system cost cut. - This ROIC chip required about 12 months of design (12*2 MM), 2 test chips (MaxChip & XFab), a final tape Out, mask fabrication and silicon processing (MaxChip), assembly (Systrel), and lab test tools development (NIT). Status: Public 1/17

2 AUTHORS BOGDAN ARION / TASK LEADER NIT APPROVAL JEAN-LUC REVERCHON / WP LEADER ATL (III-V LAB) AUTHORIZATION A. FERNANDEZ-RANADA SHAW / PROJECT OFFICER EUROPEAN COMMISSION ISSUES DATE MODIFICATIONS AUTHOR 1 MAIN CONTENT DISTRIBUTION LIST OPT, CRF, UNIPR, ADA, NIT;RPL PUBLIC DISSEMINATION WORK PACKAGE LEADERS Status: Public 2/17

3 CONTENT 1. GENERAL INFORMATION FEATURES APPLICATIONS CIRCUIT BLOCK DIAGRAM PIXEL ARRAY STRUCTURE AND FLOORPLAN PIXEL ARRAY STRUCTURE FLOOR PLAN, PAD LIST & COORDINATES PACKAGE, PIN LIST AND DESCRIPTION OPERATION & TIMING DIAGRAM POWER SUPPLY AND BIAS CONDITIONS PACKAGE DIMENSIONS LIST OF ACRONYMS Status: Public 3/17

4 1. GENERAL INFORMATION ROIC_2WS is a VGA (640x513-pixel) resolution multipurpose wide dynamic range CMOS readout circuit with logarithmic response by using NIT s patented MAGIC technology. It permits a fully contrast conserving image sensing over a large dynamic range without saturation and contrast loss and without any control. ROIC_2WS incorporates an easy-to-use digital control interface and differential analog outputs. 2. FEATURES VGA format with 640x513 effective 15 m square pixel Rolling progressive scan FPN free logarithmic response with automatic level compensation Adapted to any photodiode polarity (P-on-N or N-on-P) > 120dB intrinsic dynamic range with no exposure control Low power consumption with 50mA at 3.3V single voltage Flexible and easy-to-use 8-bit digital control Differential analog outputs 3. APPLICATIONS IR detectors (SWIR, MWIR, LWIR) Automotive vision Industrial monitoring THz, X-ray, etc. Status: Public 4/17

5 4. CIRCUIT BLOCK DIAGRAM The functional block diagram is shown in Fig. 1. It is composed of 4 major blocks: a sensing array with 640x513-pixel, a vertical/horizontal scanning circuit, a column based analog readout circuit and a fully differential image signal processing chain. Fig. 1 Block diagram of ROIC_2WS. Status: Public 5/17

6 5. PIXEL ARRAY STRUCTURE AND FLOORPLAN 5.1 PIXEL ARRAY STRUCTURE The active array contains 640x513 effective pixels. Each pixel is 15x15µm and provides a 2x2µm open pad over top metal for external Photo Diode interconnection. The picture below shows the upper left corner of the array. 4 rows Dummy_outer ring (Vdetcom) Pixel pitch: 15µm 1 row (Vdrain) 1 row (Vdetcom) Pad window: 2 m Active Matrix (513x640 effective pixels) 7µm Top Metal interconnection Pad Fig. 2 Active array corner and pixel interconnection pad detail The active matrix is surrounded by two dummy pixel rings. One of them is (4+1) rows large (Vdetcom) and the other one is 1 row (Vdrain) and the two can be independently biased through two independents pad/pins Vdetcom and Vdrain. Usually Vdetcom ring is used to bias external photodiode array Common substrate layer (either P or N type). Typical Vdetcom (Common bias) voltage is 0V. Status: Public 6/17

7 PD array side Hybridization plane ROIC side Active pixel hybridization bump ROIC pixel RST Array GND * Either PN or NP junctions can be used REFRST GND Substrate hybridization bump Vdetcom_pad Vdrain_pad Active matrix Fig. 3 Hybrid PD array biasing principle Status: Public 7/17

8 5.1 FLOOR PLAN, PAD LIST & COORDINATES The overall die dimensions are 10400*10100µm, including the seal-ring. By adding the saw-lane, it gives a sawing pitch of 10480*10180µm. For chip-on-board assemblage purposes, the chip floor plan can be found below: Fig. 4 Chip floor plan Pads are positioned on top and bottom edges, with a regular pitch of 560µm on top, and 525µm on bottom side*. Pads openings are 75x75µm. Post-processing align marks are crosses (positive & negative) and are situated in the lower part between pads GOpad and DGNDpad. The following table gives the position and the name of each pad of the die. The reference (0,0) for pad coordinates is located in the bottom-left corner. * Excepted Temperature Sensing pads TS1 and TS2, intercalated between regular pads on the top (TS1) and respectively bottom side (TS2) see the Pad List below to get the precise (X,Y) position. Status: Public 8/17

9 N Pad Name (X,Y) Pad Type 1 RST (226.67, ) inpad 2 NEG (786.67, ) Videpad 3 VREG3.0 ( , ) vddpad 4 VREG3.0 ( , ) vddpad 5 STI ( , ) anapad 6 BG ( , ) anapad 7 AVDD3.3 ( , ) vddpad 8 AGND ( , ) vsspad 9 AGND ( , ) vsspad 10 AVDD3.3 ( , ) vddpad 11 AGND ( , ) vsspad 12 AGND ( , ) vsspad 13 AVDD3.3 ( , ) vddpad 14 VREG3.0 ( , ) vddpad 15 PIXBIAS ( , ) Videpad 16 COLBIAS ( , ) Videpad 17 VDETCOM ( , ) Videpad 18 VDRAIN ( , ) Videpad 19 TS1 ( , ) Videpad 20 RESREF ( , ) Videpad 21 BUFBIAS ( , ) Videpad 22 DPR ( , ) inpad 23 AGND ( , ) vsspad 24 OUTN ( , ) anapad 25 OUTP ( , ) anapad 26 AGND ( , ) vsspad 27 OFFSET ( , ) anapad Status: Public 9/17

10 28 G1 ( , ) inpad 29 G0 ( , ) inpad 30 DVDD3.3 ( , ) vddpad 31 DVDD3.3 ( , ) vddpad 32 DGND ( , ) vsspad 33 DGND ( , ) vsspad 34 DGND ( , ) vsspad 35 HCLK ( , ) inpad 36 HSYNC ( , ) inpad 37 RD2 ( , ) anapad 38 RD1 ( , ) anapad 39 VSYNC (854.58, ) inpad 40 TS2 (539.07, ) Videpad 41 VCLK (329.58, ) inpad Status: Public 10/17

11 RD1 RD2 HSYNC HCLK DGND DVDD33 G0 G1 OFFSET AGND OUTP OUTN VREG STI BG AVDD33 AGND AVDD33 AGND AVDD33 VREG PIXBIAS COLBIAS VDETCOM 6. PACKAGE, PIN LIST AND DESCRIPTION ROIC_2WS can be packaged in a CLCC-48 high quality ceramic package for evaluation purpose. The parasite photodiode in each pixel gives a reduced but useful sensitivity to visible light. The functionality and control timing can be elaborated on this support with ease NEG 7 42 VDRAIN RST 8 41 TS RESREF VCLK BUFBIAS TS2 VSYNC DPR AGND Fig. 5 Package diagram of ROIC_2WS. Status: Public 11/17

12 Pin list & description Status: Public 12/17

13 7. OPERATION & TIMING DIAGRAM The complete operation can be summarized as 3 distinct sub-operations: vertical line scanning, line reading with FPN compensation and horizontal pixel scanning. The control signals are generated offchip deliberately. A complete analog camera can be built by using a simple 8-bit micro controller or low power FPGA and some passive RC components. A smart vision sensor can be built by using any free port on the DSP and this will keep the sensor operation always synchronized with the DSP. Vertical scan: The vertical scan is controlled by the vertical scan shift register with VSYNC and VCLK as input and clock. The vertical scan is started by pulling VD to 1. This will inject a single 1 into the vertical shift register and then each VCLK will shift one line. VSYNC has to be pulled to 0 at least one VCLK cycle for its initialization. A second line RST pulse comes with the falling edge of VSYNC. This double RST pulse can be practical whenever a raw exposure control is needed. The exposure time is simply set by the length of VSYNC pulse: for a short VSYNC pulse, the second RST2 comes right after the first one, so the exposure is set to the maximum value, whereas a long VSYNC pulse will generate a late RST2 Image line loading and FPN compensation The selected line in the sensing array will be loaded into the first analog memory buffer by RD1. Then the RST signal will force the pixels in this line to dark state. This dark state will be loaded into the second analog memory buffer by RD2. A differential amplifier will remove the FPN by subtracting the two analog memory buffers. It should be mentioned that RD1 and RD2 are active low (RD1 and RD2 should go to 0 to enable analog buffer loading). By default, those 2 pins are internally pulled-up by 15k resistors. Horizontal pixel scanning The horizontal pixel scanning permits ROIC_2WS to output the video signal. This scanning is controlled by a horizontal shift register which works in the same way as the vertical shift register (HSYNC, HCLK). Pulling the signal HSYNC to 1 will inject a single 1 into the horizontal shift register and also activate the pixel output. Knowing that hybridization process lead to some dead pixel on the FPA, a new functionality allowing removing them directly during readout is provided via the DPR (Dead Pixel Removal) pin. By default, DPR pin is internally set to 0 by a pull-down resistor and all the pixels are read-out. When the DPR goes to 1, the current pixel is passed over, while the previous pixel is read once again. This function should be used together with an external memory and a calibration phase. Status: Public 13/17

14 Fig. 6 Line buffers loading and FPN compensation before line scanning. Detailed typical Timing Values Symbol Max Min Comments TRD1 5 s Analog line buffer loading time (signal + FPN) TRD2 5 s Analog line buffer loading time (FPN) TVCLK 50ns Vertical clock duration THCLK 50ns Horizontal clock period T0 50ns Timing clearance TD 10ns 2ns Delay of vertical/horizontal shift register output 8. POWER SUPPLY AND BIAS CONDITIONS There are two power supply domains, one for the pixel array analog part (AVDD33) and another one for the digital part (DVDD33). AVDD33 supply is the input for the LDO internal regulator and is usually decoupled with a 1 F external capacitor. The Low Dropout (LDO) linear regulator provides the VREG=3.0V supply for the pixel array and analog processing part. Two external capacitors, one for loop compensation (Creg1=47 F, ESR =50m ) and one for filtering (typically Creg2=0.5nF) should be connected on the PCB as close as possible to the VREG pin to the ground plane. Status: Public 14/17

15 There are also two main ground planes, one for analog part (AGND) and the other for digital part (DGND), locally interconnected to create return paths whenever control signals cross from digital part to analog domain. All the bias pins should be kept electrically clean and as far as from any noise sources. The pixel array needs a negative voltage for internal dark image generation. It is recommended to use a simple charge pump circuit driven by HCLK in order to avoid the ripple noise on the output image. Two temperature sensors are also present on chip, in the upper-right and bottom-left opposite corners. They are P+/Nwell diodes with N side connected to ground. The two P side contacts are accessible trough TS1 and TS2 pins. The on chip diodes should be used with external temperature compensated current sources. For a 100 A injected current, the typical voltage on TS1 and TS2 is 760mV at room temperature. AVDD33 Pixel array and analog processing power supply (3.3V) AGND Pixel array and analog processing ground DGND Connected to GND DVDD33 Connected to VDD NEG Negative voltage, -1V is recommended PixelBias NC (on-chip generated) ColBias NC (on-chip generated) BUFbias NC (on-chip generated) Status: Public 15/17

16 9. PACKAGE DIMENSIONS Fig CLCC package dimensions (mm) NIT, New Imaging Technologies and Native WDR, are trademarks of New Imaging Technology. Status: Public 16/17

17 LIST OF ACRONYMS CLCC DoW FPGA FPA FPN LWIR MWIR NIT RST ROIC SWIR VGA WDR Ceramic Leadless Chip Carrier Description of Work Field Programmable gate Array Focal Plane Array Fixed Patern Noise Long Wave Infra-Red Mid Wave Infra-Red New Imaging Technologies Reset ReadOut Integrated Circuit Short Wave Infra-Red Video Graphics Array Wide Dynamic Range Status: Public 17/17