1/4 inch VGA Single Chip CMOS High performance Image Sensor with 640 X 480 Pixel Array POA030R. Rev 1.4. Last update : 1st APRIL 2010.

Transcription

1 Brief Datasheet 1/4 inch VGA Single Chip CMOS High performance Image Sensor with Last update : 1st APRIL th Floor, Gyeonggi R&DB Center, Iui-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do, , Korea Tel : , FAX : Copyright c 2010, Pixelplus Co.,Ltd ALL RIGHTS RESERVED

2 Revision History 1/4 inch VGA Single Chip CMOS Image Sensor with Version Date [D/M/Y] Notes Writer /02/2009 (Preliminary) Seungpyo Hong /02/2009 Added device information Chang hui Ye /04/2009 Modify HVDD voltage : 1.5~3.3V 1.8~3.3V Comment HVDD must be higher than or equal to DVDD Change X1, X2, HVDD, NTSC PIN description John Shin /04/2009 Include Typical & Optical parameter Heung Seok Park /04/ page, slave address (E0h, E1h => DCh, DDh) Seungpyo Hong /07/2009 8page edited Seungpyo Hong /09/ page, Added min.max voltage H.B Kim /11/ /12/2009 Page6, 15, 16, 17 edited Change VSYNC,STDBY PIN description(i/o Type) VSYNC(P O), STDBY(O I) Add Fig.14 and Change Fig number Page 4, Page 6 edited. ATEST change to TEST JiKyung Moon HangKyoo Kim /01/2010 Modified I/O type of Pin description(p.6) JunHyuck Lee /02/2010 Include max current of DC Characteristics Heung Seok Park /04/2010 Changed Product Code DS MIN /04/2011 Edited for brief type Chang hui Ye Caution : This datasheet can be changed without prior notice!! If you want to get up-to-date version, please send a mail to 2/25

3 Table of Contents 1/4 inch VGA Single Chip CMOS Image Sensor with Features - [ Fig. 1 ] PIN Description - [ Table 1 ] Typical Parameters Pin Descriptions - [ Table 2 ] Pin Descriptions Signal Environment Chip Architecture - [ Fig. 2 ] Block Diagram Frame Structure and Windowing - [ Fig. 3 ] Default data structure of frame and window - Window X, Y start/stop register value for default window and max. window Data Formats - [ Fig. 4 ] Bayer Color Filter Pattern - [ Fig. 5 ] 4:2:2 YUV data sequence. Data and Synchronization Timing - [ Fig. 6 ] Timing diagram for Hsync, MCLK, PCLK and Data ( Default : YUV ) - [ Fig. 7 ] Timing diagram for Hsync, MCLK, PCLK and Data ( Bayer ) - [ Fig. 8 ] Timing diagram for Vsync and Hsync. Scaling - [ Fig. 9 ] Free Scaling - [ Fig. 10 ] Effective Image Size - [ Fig. 11 ] Timing diagram for VSYNC and HSYNC (scaling modes) - [ Fig. 12 ] Timing diagram for PCLK and Data (scaling modes) I2C Master - [ Fig. 13 ] Connection of I2C EEPROM and NTSC / PAL Encoder - [ Fig. 14 ] Example of Configuration I2C EEPROM LED Control - [ Fig. 15 ] Connection of illumination sensor and IR LED 2-wire Serial Interface Description 2-wire Serial Interface Functional Description Register Tables Register Tables ( Detailed ) Application note Package information Reference schematic Layout guide 3/25

4 Features AVDD AGND TEST ISIN STDBY RSTB VSYNC D8 D7 D6 D5 HVDD HSYNC HGND SSDAT SSCLK LED1 DVDD DGND LED0 656x496 effective pixel array with RGB bayer color filters and micro-lens Power supply : AVDD : 2.8V, DVDD : 1.5V/1.8V, HVDD : 1.8 ~ 3.3V Output formats : CCIR656, 8bit YCbCr422, 8bit RGB565, 9bit RGB Bayer, 9bit Mono. Image processing on chip : lens shading, gamma correction, defect correction, low pass filter, color interpolation, edge enhancement, color correction, brightness, contrast, saturation, auto black level compensation, auto white balance, auto exposure control and back light compensation. Max. 30 frames/sec progressive 27 MHz master clock for VGA. Frame size, window size and position can be programmed through a 2-wire serial interface bus. VGA / CIF / QVGA / QCIF / QQVGA Scaling. Horizontal / Vertical mirroring. 50Hz, 60Hz flicker automatic cancellation. Soft reset. High Image Quality and High low light performance. I2C Master NTSC RSCLK RSDAT DGND XOUT DVDD PCLK HVDD X2 X1 HGND D4 D3 D2 D1 D0 DGND TE AGND1 AVDD1 [ Fig. 1 ] PIN Description of chip in a package [ Table 1 ] Typical Parameters Effective Pixel Array 656 x 496 Pixel Size 5.55 um x 5.55 um Effective Image Area 3.64 mm x mm Optical Format 1/4 inch Max. Clock frequency 27 Mhz Max. Frame Rate 27MHz 27MHz (bayer only) Dark Signal 25.2 [ mv/sec ] Sensitivity 2.93 [V/Lux.sec] Power Consumption Dynamic Standby Operating Temp. (Fully Functional Temp) -40 ~ 105 [ ] Dynamic Range degree SNR degree LED Control. 4/25

5 1/4 inch VGA Single Chip CMOS Image Sensor with PIN Descriptions Pin No. Name I/O Type Functions / Descriptions 1 AVDD1 P Analog power supply1 : 2.8V DC. 0.1uF to AGND 2 AGND1 P Analog power ground1. 3 TE I Chip Test Mode enable. User have to connect this terminal to DGND 4 DGND P Digital power ground for core circuits. 5 D0 O Bit 0 of data output. 6 D1 O Bit 1 of data output. 7 D2 O Bit 2 of data output. 8 D3 O Bit 3 of data output. 9 D4 O Bit 4 of data output. 10 HGND P I/O power ground. 11 X1 I Crystal input pad. To use Crystal, HVDD must be 2.8~3.3V Do not leave this PIN floating. If user want to use external master clock or oscillator instead of using crystal, please connect this PIN to HVDD or HGND. 12 X2 I/O Crystal output pad or master clock input pad. To use Crystal, HVDD must be 2.8~3.3V 13 HVDD P I/O Power supply: 1.8~3.3V DC with 100nF capacitor to HGND. Voltage range for all output signals is 0V ~ HVDD. HVDD must be higher than or equal to DVDD To use Crystal, HVDD must be 2.8~3.3V 14 PCLK O Pixel clock. Data can be latched by external devices at the rising or falling edge of PCLK. The polarity can be controlled anyway. 15 DVDD P Digital power supply : DC 1.5/1.8V. 16 XOUT O Master clock output for encoder chip. 17 DGND P Digital ground for core circuits. 18 RSDAT I/O 2-wire serial interface master data bus. 19 RSCLK O 2-wire serial interface master clock. 20 NTSC I NTSC/PAL mode selection pin for I2C master. This PIN must be connected to HVDD or HGND 21 LED0 O LED control bit 0. LED[1:0] provide 2bit combination of enable signal which can turn-on LED device when low light condition. 22 DGND P Digital ground for core circuits. 23 DVDD P Digital power supply : DC 1.5/1.8V. 24 LED1 O LED control bit 1. LED[1:0] provide 2bit combination of enable signal which can turn-on LED device when low light condition. 25 SSCLK I 2-wire serial interface slave clock 26 SSDAT I/O 2-wire serial interface slave data bus. 27 HGND P I/O power ground. 28 HSYNC O Horizontal synchronization pulse. HSYNC is high ( or low ) for the horizontal window of interest. It can be programmed to appear or not outside the vertical window of interest. [ Table 2 ] Pin Descriptions 5/25

6 1/4 inch VGA Single Chip CMOS Image Sensor with PIN Descriptions Pin No. Name I/O Type Functions / Descriptions 29 HVDD P I/O Power supply: 1.8~3.3V DC with 100nF capacitor to HGND. Voltage range for all output signals is 0V ~ HVDD. HVDD must be higher than or equal to DVDD To use Crystal, HVDD must be 2.8~3.3V 30 D5 O Bit 5 of data output. 31 D6 O Bit 6 of data output. 32 D7 O Bit 7 of data output. 33 D8 O Bit 8 of data output. 34 VSYNC O Vertical sync : Indicates the start of a new frame. 35 RSTB I System reset must remain low for at least 8 master clocks after power is stabilized. When the sensor is reset, all registers are set to their default values. 36 STDBY I Power standby mode. When Standby= 1 there s no current flow in any analog circuit branch, neither any beat of digital clock. D<8:0> and PCLK, HSYNC, VSYNC pins can be programmed to tri-state or all 1 or all 0. But it is possible to control internal registers through 2-wire serial interface bus in Standby mode. All registers retain their current values. 37 ISIN I Illumination sensor input pin for LED control function. 38 TEST O Analog test pin. 39 AGND P Analog power ground. 40 AVDD P Analog power supply : 2.8V DC. 0.1uF to AGND [ Table 2 ] Pin Descriptions (continued) 6/25

7 Bias / ADC control 2-wire serial interface Registers Image Signal Processing Bayer RGB pclk Hsync Vsync Data Row decoder Control register STDBY RSTB X1 Signal Environment 1/4 inch VGA Single Chip CMOS Image Sensor with has 3.3V tolerant Input pads. Input signals must be higher than or equal to HVDD but cannot be higher than 3.3V. input pad has built in reverse current protection circuit, which makes it possible to apply input voltage even if the HVDD is disconnected or floating. Voltage range for all output signals is 0V ~ HVDD. Chip Architecture has 656 x 496 effective pixel array and column/row driver circuits to read out the pixel data progressively. CDS circuit reduces noise signals generated from various sources mainly resulting from process variations. Pixel output is compared with the reset level of its own and only the difference signal is sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain factors to balance the color of images in various light conditions. The analog signals are converted to digital forms one line at a time and 1 line data are streamed out column by column. The Bayer RGB data are passed through a sequence of image signal processing blocks to finally produce YCbCr 4:2:2 output data. Image signal processing includes such operations as gamma correction, defect correction, low pass filter, color interpolation, edge enhancement, color correction, contrast stretch, color saturation, white balance, exposure control and back light compensation. Internal functions and output signal timing can be programmed simply by modifying the register files through 2-wire serial interface. Analog Control signal Digital Control signal Effective Pixel array Timing control 9 CDS<0:803> ADC<0:803> 9 8bits Y/UV or 9bits Bayer PCLK HSYNC VSYNC SSDAT Column decoder SSCLK Digital Control signal [ Fig. 2 ] Block Diagram 7/25

8 Frame Structure and Windowing Origin ( 0, 0 ) of the frame is at the upper right corner. Size of the frame is determined by two registers : framewidth( Reg.A-04h, A-05h ) and frameheight( Reg.A-06h, A-07h ). One frame consists of framewidth + 1 columns and frameheight + 1 rows. framewidth and frameheight can be programmed to be larger than total array size. Default window array of 640 x 480 pixels is positioned at ( 110, 16 ). It is possible to define a specific region of the frame as a window. Pixel scanning begins from ( 0, 0 ) and proceeds row by row downward, and for each line scan direction is from right to the left. Hsync signal indicates if the output is from a pixel that belongs to the window or not. There are two counters to indicate the present coordinate of frame scanning : Frame row counter and frame column counter. Counter values repeat the cycle of 0 to frameheight, and 0 to framewidth respectively. The counter values increase at the pace of pixel clock (PCLK), which does not change as the frame size is altered. The pixel data rate is fixed and is independent of frame size(frame rate). [ Table 3 ] shows windowx, y start/stop( Reg.A-08h ~ A-0Fh ) registers value for default window and maximum window. Column OBP VGA Frame Structure (102,0) 8 8 (102,8) 640 (110,16) 8 8 (0,0) Row OBP (757,503) (757,511) 8 8 (749,495) (857,524) 13 Effective window (640 x 480) Effective Pixel (656 x 496) * Total Pixel : 656 x 512 [ Fig. 3 ] Default data structure of frame and window. ( Top view ) 8/25

9 Data Formats 1/4 inch VGA Single Chip CMOS Image Sensor with R G R G R G G B G B G B R G R G R G G B G B G B R G R G R G G B G B G B [ Fig. 4 ] Bayer Color filter pattern Pixel array is covered by Bayer color filters as can be seen in the [ Fig. 4 ]. Since each pixel can have only one type of filter on it, only one color component can be produced by a pixel. provides this Bayer pattern RGB data through an 8bit channel. It takes one PCLK to pass one pixel RGB data to output bus. But since it is necessary to know all 3 color components R, G, B to produce a color for a pixel, the other two components must be inferred from other pixel data. For example, G component for a B pixel is calculated as an average of its four nearest G neighbors, and its R component as an average of its four nearest R neighbors. This operation of inferring missing data from existing ones is called the color interpolation. Color interpolation produces an undesirable artifact in image. Sampling nature of color filter can leave an interference pattern around an area with repetitive fine lines. adopts a low pass filter to prevent the interference patterns ( called Moire pattern) from degrading the image quality too much. After color interpolation, every pixel has all three color components. These three color components R, G, B can be routed to 8 bits output pins in such a way RGB565. It takes two PCLK s to pass one pixel RGB data to output bus. It is possible to extract monochrome luminance data from RGB color components and the conversion equation is : Y = 0.299R G B where R,G and B are gamma corrected color components. And the color information is separated from luminance information according to following equations. U = ( B Y ), V = ( R Y ) Since human eyes are less sensitive to color variation than to luminance, color components can be sub-sampled to reduce the amount of data to be transmitted, but preserving almost the same image quality. supports 4:2:2 YUV data format where U and V components are horizontally subsampled such that U and V for every other pixel are omitted. also supports ITU-R U1 Y1 V1 Y2 U3 Y3 V3 Y4 BT.601 YC B C R format which is a scaled, offset version of YUV. Y is the same in both formats but [ Fig. 5 ] 4:2:2 YUV data sequence. the C B C R is formed as follows. C B = ( B Y ) C R = ( R Y ) /25

10 Data and Synchronization Timing [ Fig. 6 ] shows the default data sequence of. In [ Fig. 6 ] Hsync / PCLK polarity can have any combinations possible. Data can be latched at the rising or falling edge of PCLK. Hsync can be set to be active high or active low. The sequence default YUV data is [ U,Y, V, Y, ] for common even / odd rows. The width of Hsync can be programmed by windowx1 / x2( Reg.A-08h, 09h, 0Ch, 0Dh ) and given by Hsync Width = windowx2 - windowx1 + 1 Data value can be selected in Invalid or blanking region. ( Reg.B-AEh ~ B6h ) Hsync Width = window x2 window x1 + 1 (pclk) Hsync MCLK PCLK DATA AB U Y V Y U Y U Y V Y FF [ Fig. 6 ] Timing diagram for Hsync, MCLK, PCLK and Data ( YUV mode : default ) The default sequence Bayer data is [RGRG ] for even rows and [GBGB ] for odd rows. Hsync Width = window x2 window x1 + 1 (pclk) Hsync MCLK PCLK DATA(E) AB R G R G DATA(O) AB G B G B FF FF [ Fig. 7 ] Timing diagram for Hsync, MCLK, PCLK and Data ( Bayer mode ) 10/25

11 In [ Fig. 8 ], Vsync polarity also can have any combinations possible and can be set to be active high or active low. The width of Vsync can be programmed by vsyncstart / vsyncstop( Reg.A-10h ~ 13h ) and given by Vsync Width = ( vsyncstop vsyncstart ). The width of Vreference can be programmed by register windowy1 / y2( Reg.A-0Ah, 0Bh, 0Eh, 0Fh ) and given by Vreference width = ( windowy2 - windowy1 ). Vreference Vreference width = ( window y2 window y1 ) Vsync(def.) Vsync width = ( vsyncstop vsyncstart ) Hsync 1 line time = ( framewidth + 1 ) x pclk Hsync Width = window x2 window x1 [ Fig. 8 ] Timing diagram for Vsync and Hsync 11/25

12 Scaling Full image pixel locations X points = 32 * M Y points = 32 * N Whrere, M & N is integer ( 0, 1, 2,...) [ Fig. 9 ] Free Scaling Scaled image sampling points X Sampling points = reg_scale_x * P Y Sampling points = reg_scale_y * Q Where, P, Q is integer (0, 1, 2,...) Example Reg_scale_x = 40 Reg_scale_y = 48 ( reg_window_x1, reg_window_y1 ) minimum = (1, 1) # of columns # of rows [ Fig. 10 ] Effective Image Size ( reg_window_x2, reg_window_y2 ) maximum = (648, 488) Effective Image. # of columns = reg_window_x2 - reg_window_x1 +1 Effective Image. # of rows = reg_window_y2 - reg_window_y /25

13 VSYNC HSYNC [ VGA / CIF scaling case : default ] VSYNC HSYNC [ QVGA / QCIF scaling case ] VSYNC HSYNC [ QQVGA scaling case ] [ Fig. 11 ] Timing diagram for VSYNC and HSYNC ( scaling modes ) 13/25

14 MCLK PCLK DATA AB U Y V Y U Y U Y V Y U Y U Y V Y FF [ VGA / CIF scaling case : default ] MCLK PCLK DATA AB U Y V Y U V Y FF [ QVGA / QCIF scaling case ] MCLK PCLK DATA AB U Y V Y FF [ QQVGA scaling case ] [ Fig. 12 ] Timing diagram for PCLK and Data ( scaling modes ) 14/25

15 I2C Master 1/4 inch VGA Single Chip CMOS Image Sensor with supports I2C mater function. User tuning registers of and NTSC/PAL encoder can be set by I2C EEPROM initially. After reset time tries to access I2C EEPROM whether it has connected. If the connection has accomplished reads data from I2C EEPROM and sets its registers. [Fig. 13] shows how to connect and I2C EEPROM. VCC VCC VCC NTSC SSDAT SSCLK SCL SDA I2C EEPROM (24XX16) RSDAT RSCLK SCL SDA NTSC/PAL Encoder [Fig. 13] Connection of I2C EEPROM and NTSC / PAL Encoder For example,[fig. 14] shows Pin description of I2C EEPROM(24XX16). Generally The A0, A1 and A2 pins of I2C EEPROM(24XX16) are not used. doesn t support I2C EEPROM(24XX64). A0 A1 A2 VSS I2C EEPROM (24XX16) VCC WP SCL SDA [Fig. 14] Pin description of I2C EEPROM(24XX16) User can select NTSC or PAL mode using NTSC pin. If NTSC pin is connected to VCC, I2C master operate NTSC mode. If NTSC pin is connected to ground, I2C master operate PAL mode. [Fig. 15] shows that example of configuration I2C EEPROM. 15/25

16 LED Control 1/4 inch VGA Single Chip CMOS Image Sensor with provides LED control function with ambient light sensor (analog current output type) and IR LED. [Fig 16] shows that connection of illumination sensor and IR LED. Ambient Light Sensor (Analog Current Output Type) ISIN ADC LED Control Block LED1 LED0 IR LED [Fig. 16] Connection of illumination sensor and IR LED There is several tuning registers for LED control block. For more information of tuning registers, please refer to register descriptions (Reg. B-54h~59h). 16/25

17 2-wire Serial Interface Description The registers of are written and read through the 2-wire Serial Interface. The has 2-wire Serial Interface slave. The is controlled by the Register Access Clock (SSCLK), which is driven by the 2-wire Serial Interface master. Data is transferred into and out of the through the Register Access Data (SSDAT) line. The SSCLK and SSDAT lines are pulled up to VDD by a 2kΩ off-chip resistor. Either the slave or master device can pull the lines down. The 2-wire Serial Interface protocol determines which device is allowed to pull the two lines down at any given time. Start bit The start bit is defined as a HIGH to LOW transition of the data line while the clock line is HIGH. Stop bit The stop bit is defined as a LOW to HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a 2-wire Serial Interface device consists of 7-bit of address and 1-bit of direction. A 0 in the LSB of the address indicates write mode, and a 1 indicates read-mode. Data bit transfer One data bit is transferred during each clock pulse. The SSCLK pulse is provided by the master. The data must be sgroup During the HIGH period of the SSCLK : it can only change when the SSCLK is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. Acknowledge bit The receiver generates the acknowledge clock pulse. The transmitter ( which is the master when writing, or the slave when reading ) releases the data line, and receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. No-acknowledge bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. Sequence A typical read or write sequence begins by the master sending a start bit. After start bit, the master sends the slave device s 8-bit address. The last bit of the address determines if the request will be a read or a write, where a 0 indicates a write and a 1 indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The uses 8 bit data for its internal registers, thus requiring one 8-bit transfer to write to one register. After 8 bits are transferred, the register address is automatically incremented, so that the next 8 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the writemode slave address and 8-bit register address just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after each 8 bit is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. 17/25

18 2-wire Serial Interface Functional Description Single Write Mode operation S SLAVE ADDRESS W A REGISTER ADR. A DATA A P Multiple Write Mode (Register address is increased automatically) 1 operation S SLAVE ADDRESS W A REGISTER ADR. A DATA A DATA A DATA A P Single Read Mode operation S SLAVE ADDRESS W A REGISTER ADR. A Sr SLAVE ADDRESS R A DATA NA P Multiple Read Mode (Register address is increased automatically) 1 operation S SLAVE ADDRESS W A REGISTER ADR. A Sr SLAVE ADDRESS R A DATA A DATA A DATA A DATA NA P From master to slave From slave to master S: Start condition. Sr : Repeated Start ( Start without preceding stop. ) SLAVE ADDRESS: write address = DCh = b read address = DDh = b R/W: Read/Write selection. High = read / LOW = write. A: Acknowledge bit. NA : No Acknowledge. DATA: 8-bit data P: Stop condition Note 1: Continuous writing or reading without any interrupt increases the register address automatically. If the address is increased above valid register address range, further writing does not affect the chip operation in write mode. Data from invalid registers are undefined in read mode. 18/25

19 Electrical Characteristics 1/4 inch VGA Single Chip CMOS Image Sensor with Absolute Maximum Ratings * HVDD,AVDD Supply Voltage V to 4.5V DVDD Supply Voltage V to 2.5V DC Voltage at any input pin V to HVDD+0.3V DC Voltage at any output pin V to HVDD+0.3V Storage Temperature C to C Table 3. DC Characteristics Symbol Descriptions Min Typ Max Unit V DDD Digital VDD voltage relative to GND( DGND) level V V DDA Analog voltage relative to GND(AGND) level V HV DD High VDD(HVDD) voltage relative to GND(DGND) level. HVDD must be higher than or equal to DVDD V Supply current at 30 fps. Currents are programmable through 2- wire serial interface. TBD ma I DDD DVDD=1.8V(1.5V) - 7.8(6.4) 11.4 ma AVDD=2.8V ma HVDD=2.8V ma I DDS Standby supply current@ DVDD=1.8V(1.5V)/AVDD=2.8V/HVDD=2.8V 8(4.3) 20 ua V IL1 Input voltage LOW level 0.2*HV DD V V IH1 Input voltage HIGH level 0.8*HVDD V V IL2 Input voltage LOW level for rclk, rdata. 0.2*HV DD V V IH2 Input voltage HIGH level for rclk, rdata 0.8*HVDD V C IN Input pin capacitance 10 pf V OL1 Output Voltage LOW 0.1*HV DD V V OH1 Output Voltage HIGH 0.9*HVDD V V OL2 Output Voltage LOW level for rclk, rdata. 0.2 V V OH2 Output Voltage HIGH level for rdata. HVDD-0.2 V I IN Input leakage current ua I OT Output leakage current ua * Excessive stresses may cause permanent damage to the device. 19/25

20 Table 5. Electro-Optical Characteristics 60degree ) Symbol Parameter Notes Min Typ Max Unit Sens Sensitivity 1) 2.93 V/Lux.sec Vsat Saturation Level 2) 1195 mv Vdrk Dark Signal 3) 25.2 mv/sec DR Dynamic range 4) 44.2 db Notes : 1) This value comes from the wafer test. The calculation sequence is as follows. (1) read the saturation level from evaluation pad (2) calculate One LSB. (3) Read output signal of Green pixels under illumination with output signal equal to 50% of saturation signal. (4) Read the Luminance and Integration Time when 50% of saturation signal. (5) Calculate the sensitivity using (1)~(4) = (the signal of Green pixels * one LSB ) / (luminance * integration time) 2) Read the value of evaluation pad when all pixels are saturated in condition 3) Measured at the zero illumination. (1) read the dark signal average of all pixels for minimum integration time (2) read the dark signal average of all pixels for maximum integration time (3) [Dark maximum integration time] [Dark minimum integration time] (4) convert to mv/sec unit 4) For frame rate=7.5 fps 20*Log [Saturation Signal /Dark signal] [db] 20/25

21 Power-On Sequence DVDD HVDD AVDD t1 t2 MCLK RSTB SSCLK, SSDAT t7 t9 Sensor initialization (1) Output Hi-Z release (Reg.B-1Ah[3] = 0 ) DATA<8:0>, HSYNC, VSYNC, PCLK unknown Output=Hi-Z Normal operation (2) Output=Hi-Z STDBY Standby Mode (1) Output state is Hi-Z in default. To release output Hi-Z state, set Reg.A-59h[6] to 0 (2) To make output Hi-Z state in power-down mode, set Reg.A-59h[7] to 1 before starting power-down mode Power-Off Sequence DVDD HVDD AVDD RSTB t8 t5 t6 Table6. Recommended Power-On/Off sequence Symbol Descriptions Min Typ Max Unit t1 From DVDD rising to HVDD rising 0 ns t2 From HVDD rising to AVDD rising 0 ns t5 From AVDD falling to HVDD falling 0 ns t6 From HVDD falling to DVDD falling 0 ns t7 From HVDD rising to initial mclk rising 0 ns t8 From RSTB falling to AVDD falling 0 ns t9 Minimum reset time 8 x MCLK period 21/25

22 PLCC Package information < TOP VIEW > < Placing PLCC package on PCB > On standpoint of TOP view on PCB, place pin#1 as right handed then image output is correct angle. PLCC Package is designed to equalize image array center with package s. 22/25

23 PLCC Package reference schematic has 9bits data bus to interface with Multimedia processor, If need to omit as 8bit, D0 should be omitted. LEDCNTL0:1 can be an input of driving TR to LED, If no use, leave them as floating. 23/25

24 PLCC Package Layout consideration < BOTTOM VIEW > < Foot print > Above diagram is PLCC package foot print which contains marginal information on pads. To design PCB foot print, it should be concerned with SMT conditions additionally. < Power plane lay out > In case of designing GND and POWER plane, It is recommended to assign wide AGND plane. If there s not much area dedicated to AGND, horizontal random power noise can happen on image output. In case of supplying power to AVDD, LDO ( Voltage regulator ) is preferred to DC to DC converter which has oscillation frequency. < Debugging information > Coupling capacitor between AVDD and Main GND is helpful to stabilize AVDD if AGND has not enough size. Isolation beads between AVDD and LDO can sometimes enlarge dropping voltage depending on power network. Reverse current protective or voltage dropping diode between AVDD and LDO can also make power noise. 24/25

25 Pixel plus members help you to make your world much safer. Regarding further information, please contact our localized representative distributors. Copyright c 2010, Pixelplus Co.,Ltd ALL RIGHTS RESERVED 25/25