4-PIN TO HEADER V CC_RX OUTPOL OUT+ OUT- RSSI TH GND DISABLE LOS. R TH = 14kΩ

Transcription

1 ; Rev ; 6/7 Low-Power, 6Mbps to 3.Gbps General Description The multirate limiting amplifier functions as a data quantizer for SONET, Fibre-Channel, and Gigabit Ethernet optical receivers. The amplifier accepts a wide range of input voltages and provides selectable-level, current-mode logic (CML) output voltages with controlled edge speeds. A received-signal-strength indicator (RSSI) is available when the is DC-coupled to the MAX37/MAX37 SFP transimpedance amplifier (TIA). A receiver consisting of the MAX37/MAX37 and the can provide up to 19dB RSSI dynamic range. Additional features include a programmable loss-of-signal (LOS) detect, an optional disable function (DISABLE), and an output-signal polarity reversal (OUTPOL). Output disable can be used to implement squelch. The combination of the and the MAX37/ MAX37 allows for the implementation of all the smallform-factor SFF-87 digital diagnostic specifications using a standard -pin TO-6 header. The is pin-for-pin compatible with the MAX378A limiting amplifier and consumes 3% less power. The is packaged in a 3mm x 3mm, 16-pin QFN package. Applications Gigabit Ethernet SFF/SFP Transceiver Modules Fibre-Channel SFF/SFP Transceiver Modules Multirate OC-1 to OC8-FEC SFF/SFP Transceiver Modules Features SFP Reference Design Available Low 115mW Power Consumption 16-Pin QFN Package with 3mm x 3mm Footprint 7ps Rise and Fall Time Loss-of-Signal with Programmable Threshold RSSI Interface (with MAX37/MAX37 TIA) Output Disable Polarity Select 8.ps P-P Deterministic Jitter (3.Gbps) Improved EMI Performance Selectable CML Output levels Pin Compatible with MAX378A Ordering Information PART TEMP RANGE PIN- PACKAGE PKG CODE ETE - C to +85 C 16 Thin QFN T1633F-3 HETE* - C to +85 C 16 Thin QFN T1633F-3 *The HETE is a hybrid lead-free package. See the Detailed Description section for more information. Pin Configuration appears at end of data sheet. Typical Operating Circuits continued at end of data sheet. Typical Operating Circuits SFP OPTICAL RECEIVER HOST BOARD -PIN TO HEADER SUPPLY FILTER HOST FILTER _RX OUTPOL IN+ OUT+.1μF MAX37 TIA IN- OUT-.1μF SERDES DS INPUT DIAGNOSTIC MONITOR R1 3kΩ RSSI TH GND DISABLE LOS C1.1μF R TH = 1kΩ.7kΩ TO 1kΩ.97V TO 3.6V LOS Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage ( )...-.5V to +.5V Voltage at IN+, IN-...( -.V) to ( +.5V) Voltage at DISABLE, OUTPOL, RSSI, LOS, TH...-.5V to ( +.5V) Current into LOS...1mA to +9mA Differential Input Voltage (IN+ - IN-)...5V Continuous Current at CML Outputs (OUT+, OUT-)...-5mA to +5mA Continuous Power Dissipation (T A = + 7 C) 16-Pin QFN (derate 17.7mW above +7 C)...1.W Operating Junction Temperature Range (T J ) C to +15 C Storage Ambient Temperature Range (Ts) C to +15 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = +.97V to +3.63V, CML output load is to, T A = - C to +85 C, unless otherwise noted. Typical values are at = +3.3V, T A = +5 C, unless otherwise specified. The data input transition time is controlled by th-order Bessel filter with f -3dB =.75 x.667ghz for all data rates of.667gbps and below, and with f -3dB =.75 x 3.GHz for a data rate of 3.Gbps.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Single-Ended Input Resistance R IN Single ended to 5 58 Ω Input Return Loss se S 11 S i ng l e end ed, f < 3GH z, D U T i s p ow er ed on 1 diff S 11 Differential, f < 3GHz, DUT is powered on 15 Input Sensitivity V IN-MIN (Note 1) mv P-P Input Overload V IN-MAX (Note 1) 1 mv P-P Single-Ended Output Resistance R OUT Single ended to 5 58 Ω Output Return Loss diff S Differential, f < 3GHz, DUT is powered on db db CML Differential Output Voltage mv P-P < V IN < 1mV P-P, OUTPOL connected to or GND mv P-P < V IN < 1mV P-P, OUTPOL open or connected to 3kΩ mv P-P Differential Output Signal when Disabled Outputs AC-coupled, V IN-MAX applied to input (Note ) K8.5 pattern at 3.Gbps (Note ) K8.5 pattern at 3.Gbps at T A = +1 C PRBS equivalent at.7gbps (Note ) mv P-P Deterministic Jitter (Note 3) DJ 3-1 PRBS equivalent pattern at.7gbps at T A = +1 C 13.1 K8.5 pattern at.1gbps 8 K8.5 pattern at.1gbps at T A = +1 C 9.7 ps P-P 3-1 PRBS equivalent pattern at 6Mbps (Note ) 3-1 PRBS equivalent pattern at 6Mbps at T A = +1 C

3 ELECTRICAL CHARACTERISTICS (continued) ( = +.97V to +3.63V, CML output load is to, T A = - C to +85 C, unless otherwise noted. Typical values are at = 3.3V, T A = +5 C, unless otherwise specified. The data input transition time is controlled by th-order Bessel filter with f -3dB =.75 x.667ghz for all data rates of.667gbps and below, and with f -3dB =.75 x 3.GHz for a data rate of 3.Gbps.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Random Jitter Input = mv P-P (Notes, ) 3 7 ps RMS Data Output Transition Time mv P-P < V INP-P < 1mV P-P, % to 8% (Note ) 7 11 ps Input-ReferredNoise (Note ) 15 µv RMS Low-Frequency Cutoff khz Includes the CML output current; OUTPOL connected to or GND Power-Supply Current I CC Includes the CML output current; OUTPOL open or connected to 3kΩ to GND Excludes the CML output current and the CM_RSSI circuitry; OUTPOL connected to or GND (Note 5) Power-Supply Noise Rejection PSNR f < MHz db LOSS-OF-SIGNAL (Notes, 6) LOS Hysteresis 1 log (V DEASSERT / V ASSERT ) 1.5. db LOS Assert/Deassert Time (Note 7).3 5 µs Low LOS Assert Level R TH = kω.6 6. mv P-P Low LOS Deassert Level R TH = kω mv P-P Medium LOS Assert Level R TH = 1kΩ mv P-P Medium LOS Deassert Level R TH = 1kΩ 5.7 mv P-P High LOS Assert Level R TH = 5kΩ mv P-P High LOS Deassert Level R TH = 5kΩ 8 11 mv P-P CM_RSSI SPECIFICATION RSSI Current Gain A RSSI I RSSI / I CM_RSSI (Note 8).31 V CM to I RSSI 3dB Bandwidth khz Input-Referred RSSI Current Stability IRSSI ARSSI Input < 6.6mA, V V RSSI.5V (Note 9) µa RSSI Output Compliance Voltage V RSSI. V TTL/CMOS I/O LOS Output High Voltage V OH R LOS =.7kΩ to 1kΩ to Vcc_host (3V). V LOS Output Low Voltage V OL R LOS =.7kΩ to 1kΩ to Vcc_host (3.6V). V ma 3

4 ELECTRICAL CHARACTERISTICS (continued) ( = +.97V to +3.63V, CML output load is to, T A = - C to +85 C, unless otherwise noted. Typical values are at = +3.3V, T A = +5 C, unless otherwise specified. The data input transition time is controlled by th-order Bessel filter with f -3dB =.75 x.667ghz for all data rates of.667gbps and below, and with f -3dB =.75 x 3.GHz for a data rate of 3.Gbps.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DISABLE Input High V IH. V DISABLE Input Low V IL.8 V DISABLE Input Current R LOS =.7kΩ to 1kΩ to Vcc_host 1 µa Note 1: Between sensitivity and overload, all AC specifications are met. Note : Guaranteed by design and characterization. Note 3: The deterministic jitter caused by the filter is not included in the DJ generation specification. Note : Random jitter was measured without using a filter at the input. Note 5: The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate. (See Figure 1.) Note 6: Hysteresis is calculated as 1 log (V DEASSERT / V ASSERT ). Unless otherwise specified, the data rate for all LOS detect specifications varies from 6Mbps up to 3.Gbps, and the patterns are 11 or 3-1 PRBS. Note 7: The signal is switched between two amplitudes, Signal_On and Signal _Off as shown in Figure. Note 8: I CM_RSSI is the input common-mode current. I RSSI is the current at the RSSI output. Note 9: Stability is defined as the variation over temperature and power supply with respect to the typical gain of the part. ( = +3.3V, T A = +5 C, unless otherwise noted.) Typical Operating Characteristics CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE 1 OUTPOL = CML OUTPUTS INCLUDED 3 1 CML OUTPUTS NOT INCLUDED TEMPERATURE ( C) toc1 DIFFERENTIAL OUTPUT (mvp-p) TRANSFER FUNCTION OUTPOL = DIFFERENTIAL INPUT (mv P-P ) toc RANDOM JITTER (psrms) RANDOM JITTER vs. TEMPERATURE (INPUT LEVEL 1mV P-P ) TEMPERATURE ( C) toc3

5 Typical Operating Characteristics (continued) ( = +3.3V, T A = +5 C, unless otherwise noted.) RANDOM JITTER (psrms) RANDOM JITTER vs. INPUT AMPLITUDE DIFFERENTIAL INPUT (mv P-P ) toc BIT-ERROR RATIO (1-1 ) BIT-ERROR RATIO vs. INPUT VOLTAGE INPUT VOLTAGE (mv P-P ) toc5 DETERMINISTIC JITTER (psp-p) DETERMINISTIC JITTER vs. INPUT COMMON-MODE VOLTAGE (.7Gbps, K8.5) COMMON-MODE VOLTAGE ( + X) toc6 OUTPUT EYE DIAGRAM (MINIMUM INPUT) 3.Gbps, K8.5, mv P-P toc7 OUTPUT EYE DIAGRAM (MAXIMUM INPUT) 3.Gbps, K8.5, 1mV P-P toc8 OUTPUT EYE DIAGRAM (MINIMUM INPUT).7Gbps, 3-1 PRBS, mv P-P toc9 1mV/div 1mV/div 1mV/div 5ps/div 5ps/div 1ps/div 1mV/div OUTPUT EYE DIAGRAM (MAXIMUM INPUT).7Gbps, 3-1 PRBS, 1mV P-P toc1 1mV/div OUTPUT EYE DIAGRAM AT +1 C (MINIMUM INPUT).7Gbps, 3-1 PRBS, mv P-P toc11 LOS ASSERT/DEASSERT (mvp-p) ASSERT/DEASSERT LEVELS vs. R TH DEASSERT ASSERT MAX376 toc1 5ps/div 5ps/div 1 3 R TH (kω) 5

6 Typical Operating Characteristics (continued) ( = +3.3V, T A = +5 C, unless otherwise noted.) GAIN (db) M INPUT RETURN GAIN (SDD11) (INPUT SIGNAL LEVEL = -5dBm) (OUTPUT DISABLED) 1G FREQUENCY (Hz) toc13 1G GAIN (db) M OUTPUT RETURN GAIN (SDD) (INPUT SIGNAL LEVEL = -5dBm) (WITH INPUT DC OFFSET) 1G FREQUENCY (MHz) toc1 1G DETERMINISTIC JITTER (psp-p) DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE (.667Gbps, K8.5) INPUT OFFSET VOLTAGE (mv P-P ) toc15 1 log (DEASSERT/ASSERT) (db) LOS HYSTERESIS vs. TEMPERATURE (.667Gbps, 3-1 PRBS) R TH = 5kΩ R TH =.kω R TH = 1kΩ toc16 OUTPUT RSSI CURRENT (μa) RSSI CURRENT vs. INPUT TIA CURRENT (MAX37 and ) toc TEMPERATURE ( C) INPUT TIA CURRENT (μa) SINGLE-ENDED OUTPUT SIGNAL.7Gbps, 7-1, 1mV P-P toc RSSI CURRENT vs. OPTICAL POWER (MAX37 and ) toc19 5mV/div OUTPUT RSSI CURRENT (μa) ps/div OPTICAL POWER (dbm) 6

7 PIN NAME FUNCTION 1, 1 Supply Voltage IN+ Noninverted Input Signal, CML 3 IN- Inverted Input Signal, CML 5 TH 6 DISABLE Pin Description Loss-of-Signal Threshold Pin. Resistor to ground (R TH ) sets the LOS threshold. Connecting this pin to disables the LOS circuitry and reduces power consumption. Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The data outputs are enabled when this pin is asserted low. The LOS function remains active when the outputs are disabled. 7 LOS Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert threshold set by the TH input. The output is open collector. 8, 16 GND Supply Ground 9 OUTPOL Output Polarity Control. Connect to GND for an inversion of polarity through the limiting amplifier and connect to for normal operation. See Table 1 for all settings. 1 OUT- Inverted Data Output, CML 11 OUT+ Noninverted Data Output, CML 1 Output Supply 13 RSSI Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced voltage proportional to the photodiode current with the MAX37 by connecting an external resistor between this pin and GND. 1,15 N.C. No Connection. Leave open. EP EXPOSED PAD Connect the exposed pad to board ground for optimal electrical and thermal performance. Detailed Description The limiting amplifier consists of an input buffer, a multistage amplifier, offset-correction circuitry, an output buffer, power-detection circuitry, and signaldetect circuitry (see the Functional Diagram). Input Buffer The input buffer is shown in Figure 3. It provides termination for each input signal IN+ and IN-. The can be DC- or AC-coupled to a TIA (TIA output offset degrades receiver performance if DC-coupled). The CML input buffer is optimized for the MAX37/ MAX37 TIA. Gain Stage The high-bandwidth multistage amplifier provides approximately 6dB of gain. Offset Correction Loop The is susceptible to DC offsets in the signal path because it has high gain. In communication systems using NRZ data with a 5% duty cycle, pulsewidth distortion present in the signal, or generated in the transimpedance amplifier, appears as an input offset and is reduced by the offset correction loop. CML Output Buffer The limiting amplifier s CML output provides high tolerance to impedance mismatches and inductive connectors. The OUTPOL setting programs the output current. Connecting the DISABLE pin to disables the output. If the LOS pin is connected to the DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level drops below the LOS threshold. The output common mode remains constant when the part is disabled. The output buffer can be AC- or DC-coupled to the load (Figure ). 7

8 I CC (SUPPLY CURRENT) I OUT (CML OUTPUT CURRENT) V IN 1dB 6dB SIGNAL ON MAX DEASSERT LEVEL POWER-DETECT WINDOW MIN ASSERT LEVEL R TH V SIGNAL OFF TIME Figure 1. Power-Supply Current Measurement Figure. LOS Assert Threshold Set 1dB Below the Minimum by Receiver Sensitivity for Selected R TH.5pF IN+ OUT+ OUT- Q3 Q Q1 Q IN-.5pF DISABLE ESD STRUCTURES DATA ESD STRUCTURES I1 = f (OUTPOL, DISABLE) I = f (OUTPOL, DISABLE) Figure 3. CML Input Buffer Figure. CML Output Buffer Power Detect and Loss-of-Signal Indicator The is equipped with multirate LOS circuitry that indicates when the input signal is below a programmable threshold, set by resistor R TH at the TH pin (see the Typical Operating Characteristics for appropriate resistor sizing). An averaging RMS power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the open-collector LOS output. To prevent LOS chatter in the region of the programmed threshold, approximately db of hysteresis is built into the LOS assert/deassert function. Once asserted, the LOS is not deasserted until the input amplitude rises to the required level (V DEASSERT ). (See Figures and 5.) Hybrid Lead-Free Package The HETE is a in a hybrid lead-free package. It is a hybrid part, which contains high-lead bumps inside a lead-free thin QFN package. The part is not 1% lead free; however, the high-lead solder in the internal portion of the part does meet the RoHS exemption for high-lead solders. For more information, visit 8

9 GND Figure 5. LOS Output Circuit ESD STRUCTURE Design Procedure Program the LOS Assert Threshold External resistor, R TH, programs the loss-of-signal threshold. See the LOS Threshold vs. R TH graph in the Typical Operating Characteristics to select the appropriate resistor. Select the Coupling Capacitor When AC coupling is desired, coupling capacitors C IN and C OUT should be selected to minimize the receiver s deterministic jitter. Jitter is decreased as the input low-frequency cutoff (f IN ) is decreased. f IN = 1 / [π(5)(c IN )] For ATM/SONET or other applications using scrambled NRZ data, select (C IN, C OUT ).1µF, which provides f IN < 3kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/1B data coding, select (C IN, C OUT ).1µF, which provides f IN < 3kHz. Refer to Application Note HFAN-1.1, Choosing AC- Coupling Capacitors. RSSI Implementation The SFF-87 Digital Diagnostic specification requires monitoring of input receive power. The and MAX37 receiver chipset allows for the monitoring of the average receive power by measuring the average DC current of the photodiode. The MAX37/MAX37 preamp measures the average photodiode current and provides the information to the output common mode. The RSSI detect block senses the common-mode DC level of input signals. IN+ and IN- provide a ground-referenced output signal (RSSI) proportional to the photodiode current. LOS The advantage of this implementation is that it allows the TIA to be packaged in a low-cost, conventional - pin TO-6 header. The RSSI output is connected to an analog input channel of the DS1858/DS1859 SFP controller to convert the analog information into a 16-bit word. The DS1858/DS1859 provide the receive-power information to the host board of the optical receiver through a - wire interface. The DS1859 allows for internal calibration of the receive power monitor. The MAX37/MAX37 and the have been optimized to achieve RSSI stability of.5db within the 6µA to 5µA range of average input photodiode current. To achieve the best accuracy, MAXIM recommends receive-power calibration at the low end (6µA) and the high end (5µA) of the required range. See the RSSI Current Gain graph in the Typical Operating Characteristics. Connecting to the Dallas DS1858/DS1859 For best use of the RSSI monitor, capacitor C1 and resistor R1 shown in the first Typical Application Circuit need to be placed as close as possible to the Dallas diagnostic monitor with the ground of C1 and R1 the same as the DS1858/DS1859 ground. Capacitor C1 suppresses system noise on the RSSI signal. R1 = 3kΩ and C1 =.1µF is recommended. EMI Performance The has been designed for better EMI performance. To help reduce EMI, special care has been taken to produce symmetrical signal outputs. See the eye diagram of the single-ended output in the Typical Operating Characteristics. Table 1. Logic Table for Polarity and CML Output-Level Settings OUTPOL Open 3kΩ to GND GND DESCRIPTION N oni nver ti ng outp ut w i th ful l C M L outp ut l evel N oni nver ti ng outp ut w i th r ed uced C M L outp ut l evel Inverting output with reduced CML output level Inverting output with full CML output level Chip Information TRANSISTOR COUNT: 1385 PROCESS: SiGe Bipolar 9

10 OFFSET CORRECTION Functional Diagram OUT- OUT+ IN+ IN- RSSI DETECT POWER DETECT OUTPOL DECODE DISABLE RSSI TH LOS OUTPOL Typical Operating Circuits (continued) SFP OPTICAL RECEIVER HOST BOARD (+3.3V OR APD REFERENCE VOLTAGE) (+3.3V) SUPPLY FILTER HOST FILTER 5-PIN TO HEADER _RX OUTPOL PIN OR APD IN+ OUT+.1μF MAX37 TIA IN- OUT-.1μF SERDES RSSI TH GND DISABLE LOS R TH = 1kΩ.7kΩ TO 1kΩ.97V TO 3.6V DS INPUT DIAGNOSTIC MONITOR R1 3.1kΩ C1.1μF LOS 1

11 (+3.3V OR APD REFERENCE VOLTAGE) MAX SFP OPTICAL RECEIVER (+3.3V) 5-PIN TO HEADER Typical Operating Circuits (continued) HOST BOARD SUPPLY FILTER HOST FILTER _RX OUTPOL PIN OR APD C IN.1μF IN+ OUT+ C OUT.1μF MAX37 TIA IN- OUT- SERDES C IN.1μF C OUT.1μF RSSI TH GND DISABLE LOS DS INPUT DIAGNOSTIC MONITOR R TH = 1kΩ.7kΩ TO 1kΩ.97V TO 3.6V LOS Pin Configuration GND N.C. N.C. RSSI IN+ 11 OUT+ 3 1 IN- OUT- 1 9 OUTPOL TH DISABLE LOS GND 3mm x 3mm QFN 11

12 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to MARKING D D/ E/ E AAAA C L (ND - 1) X e e (NE - 1) X e D/ D 1x16L QFN THIN.EPS LC k L E/ b.1 M C A B E.1 C.8 C A A A1 L C L C L L e e PACKAGE OUTLINE 8, 1, 16L THIN QFN, 3x3x.8mm I 1

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PKG REF. A b D E e L N ND NE A1 A k 8L 3x3 MIN. NOM. MAX BSC REF - - 1L 3x3 MIN. NOM. MAX BSC REF L 3x3 MIN. NOM. MAX BSC REF PKG. CODES MIN. EXPOSED PAD VARIATIONS D NOM. MAX. MIN. E NOM. MAX. PIN ID JEDEC TQ x 5 WEEC T x 5 WEED-1 T x 5 WEED-1 T T x 5 WEED- T1633F-3.65 T x 5 WEED x 5 WEED- T1633FH x 5 WEED x 5 WEED- T x 5 WEED- NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y1.5M ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS.. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-1. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN. mm AND.5 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO REVISION C. 1. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 1. WARPAGE NOT TO EXCEED.1mm. PACKAGE OUTLINE 8, 1, 16L THIN QFN, 3x3x.8mm I Revision History Pages changed at Rev 1: 1, 8, 1. Pages changed at Rev : 7, 1, 13. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.