Technical Note PowerPC Embedded Processors Video Security with PowerPC

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1 Introduction For many reasons, digital platforms are becoming increasingly popular for video security applications. In comparison to traditional analog support, a digital solution can more effectively customize both system performance and cost in terms of resolution, frame acquisition frequency, storage, and transmission. This technical note describes a practical implementation, including test results and optimization, of a digital video platform based on IBM PowerPC technology. Considerations When developing a new system, one begins by considering how much pixel resolution per frame is needed and at what frequency images should be acquired. Based on these two parameters, there are numerous options available for compressing, broadcasting, and storing information. Compression: The MPEG algorithm has a long computational time requirement and the compression rate is very high. lternately, the Motion JPEG algorithm needs less computational time, but there is more data to transfer and store. Broadcasting: Ethernet network, Internet, wireless Storage: Compact Flash, hard disk igital Video Platform Implementation Most video surveillance systems do not require a very high resolution or a very quick sampling rate. This means that, with a fast enough transmission link, it is possible to transmit every frame acquired and compressed with a JPEG algorithm. If you choose a powerful enough CPU, you might be able to perform image compression in software and thereby reduce the system complexity and cost. The following example describes an implementation that performs image compression in-software with a powerful processor, such as the PowerPC 405EP running at 266 MHz, with the IBM PowerPC architecture. In this implementation (shown in the block diagram in Figure 1 on page 2), the video stream comes from a CC camera or from a video decoder. Suppose a resolution of 288 * 360 pixel (about 300 KB per frame) and a medium resolution of 12 frames per second. This amount of data must be managed by a very fast processor (one able to pick up all bytes, transfer them into a large memory, and make all the calculations required for the compression). Therefore, you need to choose a processor with a fast direct memory access (M) and sufficient million instructions per second (MIPS). n Ethernet MC enables sharing the video in a local network or with a remote host. The solution can be found in a processor like the PowerPC 405EP, which has all the required features: a powerful 32-bit core at 266 MHz, fast M channels, an SRM controller, and two Ethernet MCs. In Figure 1 on page 2, an SRM (K4S561632C) is used. This SRM offers a very effective compromise between speed, density, and price to fulfill the large memory requirements demanded for data manipulation. The SRM video decoder data bus and two flash memories (one for the boot phase of the system and one for the code storage) are connected on the processor bus. For these components, the following STMicroelectronics flash memory products are used: a flash with boot sectors (M50FW040N1T) and a high-density/lowcost flash for the code (M58LV064150N1T). STMicroelectronics can also supply the network interface with the MMI to be linked with the PowerPC MC (STE100P). ecember 8, 2003 Page 1

2 Figure 1. PowerPC 405EP block diagram Compression and Broadcasting K4S561632C SRM M50FW040N Boot Flash 4 Mb (512 k x 8-bit/256k x 16-bit) Package: 48 pin TSOP CMOS 3.0 Volt only, Boot Sector Flash Memory 256 Mb CMOS SRM Packages: 54 pin TSOP Freq.: 100 MHz Cas Latency: 3(2) S R M M58LV Flash 64 Mb (4M x 16-bit) CMOS 3.0 Volt-only package: 48 pin TSOP, Uniform Sector Flash Memory with Versatile I/O Memory Bus EBI PowerPC 405EP Controls M IQ T Video ecoding F I F O Video ecoder N L O G x2 channels Video Camera RJ45 STE100P Ethernet Controller E T H ETH I 2 C ebugging Interface The total bytes transfer in our hypothesis is: 288 * 360 * 3 bytes (per pixel) * 12 frame/s = 3.7 MB/s The video decoder bus has an 8-bit width, so having 133 MHz for the EBI (but 50 ns minimum access time for the decoder), we must insert 6 wait states and 2 clocks for a read of 8 bits. This means 1/133 * 8 = 60 ns to read 1 byte. You can then enable the 32 bytes buffer of the PowerPC M, considering that it takes 60 * 32 = about 2 µs to read 32 bytes. To this time, you must add the time spent in BURST writing the data in the SRM: 8 x (32 bits x 1/133 MHz) = 1.92 µs + (1/133 MHz) = 1.92 µs ns (where 7.52 ns is negligible compared to 1.92 µs) Our results show that we can transfer 1/2 µs * 32 bytes = 16 MB/s. We see that the transfer rate on the PowerPC 405EP EBI is so fast that we can consider transferring up to 4 camera video signals simultaneously. Page 2 ecember 8, 2003

3 fter all data are transferred in the SRM, we can start performing the JPEG algorithm that will reduce the size of data by 20 times. The JPEG algorithm reduces every frame from 300 KB to 15 KB. Test escription The following test was performed by Wind River on an IBM PowerPC platform to show the application environment and test results. Wind River performed tests on an Olivia platform (a PowerPC 405GP evaluation board made by Wind River) based on the PowerPC 405 VEST CPU. This chip is less powerful than the PowerPC 405EP used in the implementation described previously (150 MIPS for the VEST versus 300 MIPS for the PowerPC 405EP). In this test, Wind River PowerPC 405 Tornado 2 (TK ZC-0) was installed and Olivia band support package (BSP) (from Wind River and IBM) release 1.3/3 was used. For JPEG compression software, open source files were downloaded from the Internet: Time-stamps were located at the beginning and at the end of the encoding routine. n encoding time of T~235 µs was retrieved for each frame. The encoding time can be divided as shown in Figure 2. Figure 2. Encoding time where: Time 1: Reading BMP from RM Time 2: Compressed JPEG picture read and copied into its own buffer Time 3: Compression process The 158 µs are the result of the compression of 18 picture blocks of 16 * 360 each (16 lines of 360). Each block is thus encoded in 8~9 µs. Optimization and Results Our requirement of 12 frames/second gives 1000 µs /12 frames/s = 84 µs for frame-encoding time. Using the above test conditions, we could reach 235 µs for the whole operation. We then need to gain a ratio of 3:1 to stay within 84 µs. This gain seems achievable considering the following: CPU performance: Tests were performed on the VEST chip, given for 150 MIPS. The PowerPC 405EP is given for 300 MIPS. We can expect a gain in the range of 2:1. ecember 8, 2003 Page 3

4 Source code: The compression source code can be optimized. The main parts of the algorithm handle file reading and the block compression process (some loops can probably be avoided). Part of the compression algorithm can be coded in-assembler using the special extension instruction set macxxx. We expect a gain in the range of 2:1. rchitecture-specific: The use of the PowerPC 405EP cache could be tuned to perform part of the compression process in the instruction cache; this is to be studied in a future article. Conclusion Our conclusion is that, with software optimization and with a more powerful CPU such as the PowerPC 405EP, a compression time of less than 60 µs/frame (235 µs/4) for a CIF PL video picture with a compression ratio of 20:1 can be obtained. s an example, a hard disk size to store one day of video would consist of: 15 KB x 12 f/s x 3600 s x 24 = 15.5 GB instead of 300 KB x 12 f/s x 3600 s x 24 = 311 GB. Using the components listed in Table 1, it should be possible to share one 32-GB hard disk for two digital video streams per 24 hours. Table 1. Components and part numbers Component Part Number Supplier Boot Flash M50FW040N STMicroelectronics Processor PPC405EP IBM FLSH M58LV STMicroelectronics SRM K4S561632C Samsung Ethernet Controller STE100P STMicroelectronics rticle from Paolo Trere, Field pplication Engineer WBC Milano Revision Log Revision ate Contents of Modification ecember 8, 2003 Initial release (00). ecember 8, 2003 Page 4

5 Copyright International Business Machines Corporation 2003 ll Rights Reserved Printed in the United States of merica ecember 2003 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo PowerPC Other company, product, and service names may be trademarks or service marks of others. ll information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. ll information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMTION CONTINE IN THIS OCUMENT IS PROVIE ON N S IS BSIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics ivision 2070 Route 52, Bldg. 330 Hopewell Junction, NY The IBM home page can be found at ibm.com The IBM Microelectronics ivision home page can be found ibm.com/chips ecember 8, 2003