AND9191/D. KAI-2093 Image Sensor and the SMPTE Standard APPLICATION NOTE.

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1 KAI-09 Image Sensor and the SMPTE Standard APPLICATION NOTE Introduction The KAI 09 image sensor is designed to provide HDTV resolution video at 0 fps in a progressive scan mode. In this mode, the sensor can be read out in a manner that is compatible with the Society of Motion Pictures and Television Engineers (SMPTE) 7 video standard. The sensor can also be read out in an interlaced fashion. However, in order to provide interlaced video in accordance with the SMPTE 7 standard, the KAI 09 image sensor must be clocked at a pixel rate exceeding that in the sensor specification. For extremely high light level situations, it is sometimes desirable to electronically shutter at the beginning of each line rather than each frame. Due to the extra time that this operation requires, and the timing requirements imposed by SMPTE 7, this mode of operation, whether progressive scan or interlaced, also requires pixel rates that exceed those recommended in the sensor specification. In the pages that follow is a description of the timing required for each of these modes of operation. Description of SMPTE 7 HDTV Standard SMPTE 7 is standard for HDTV video. CCD timing parameters specified by the standard are summarized in Table 1. Table 1. SMPTE 7 TIMING REQUIREMENTS Samples per Active Line (S/AL) 190 Active Lines per Frame 1080 Frame Rate (Hz) 0 Scanning Format Progressive or Interlaced Interface Sampling Frequency (MHz) 7. Samples per Total Line (S/TL) 00 Total Lines per Frame 11 Description of the KAI 09 The KAI 09 is a high performance interline charge coupled device (CCD) designed for applications requiring HDTV resolution and frame rates. The device is built using an advanced two phase, double polysilicon, NMOS CCD technology. The p+npn photodiodes eliminate image lag while providing antiblooming protection and electronic shutter capability. The 7. square pixels provide high sensitivity and large dynamic range. The device has two outputs, each capable of operating at 0 MHz for >0 fps operation. The sensor architecture is shown in Figure 1. Semiconductor Components Industries, LLC, 01 October, 01 - Rev. 1 Publication Order Number: AND9191/D

2 light shielded rows buffer rows Video L empty pixels 8 light shielded columns buffer columns 190 x 1080 imaging pixels buffer rows light shielded rows buffer columns 8 light shielded columns empty pixels Video R Single Output Dual Output Figure 1. Sensor Architecture Each line, which for two output operation is half of the HCCD, includes empty pixels, 8 dark pixels, buffer pixels, and 90 active pixels, in that order, for a total of 99 pixels. Vertical to Horizontal Transfer According to the 7 standard, and assuming two output operation, each output will read out 00/ = 1100 pixels per line. Since there are only 99 pixels per line corresponding to each output, there is a window of = 10 pixel periods during which the vertical to horizontal transfer can take place. At the standard s rate of 7.1 MHz, 1 pixel period = 7 ns, so 10 pixel periods =.8 s. In all cases discussed below, when reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. Progressive Scan Operation For progressive scan operation, one vertical to horizontal transfer is required per line. From Figure of the Appendix, the minimum time for VCCD transfer is 1. s. Following the transfer, a waiting period of at least 1. s is required (HCCD delay). The total time required is therefore. s, which is less than the.8 s allowed. This means that enough time is provided so that video can come directly off the chip as specified by SMPTE 7. Progressive Scan Operation with Electronic Shuttering Each Line For high luminance applications, it is sometimes desirable to drain the photodiode before each line transfer. This is only required if the antiblooming protection provided by the sensor s vertical overflow drain is not sufficient to drain away charge accumulated in the photodiode during frame read out. Electronic shuttering cannot be performed in parallel with VCCD transfers without losing some charge from the vertical shift registers. Therefore the two operations must be performed serially as listed below: Shutter pulse (.0 s) Shutter delay (1.0 s) VCCD Transfer (1. s) HCCD delay (1. s) A total time of. s is needed to perform these operations, which is more than the.8 s allowed. Therefore, if the device must be shuttered during each line transfer, video cannot be streamed directly from the CCD in conformance with SMPTE 7. Rather, the CCD must be clocked faster than 7.1 MHz to create a larger window for shuttering and transferring each line. The video must be buffered and then transmitted according to the standard. The required pixel rate is calculated using (1100 samples line) (7.1E samples s) (99 pixels) (R pixels s) T (eq. 1) where T is the time needed between horizontal line read outs, and R is the required pixel rate. For T =. s, Equation 1 gives a required pixel rate of.0 MHz. Interlaced Operation Interlaced operation requires two vertical transfers per line, as shown in Figure of the Appendix. After each transfer, a HCCD delay is required. The total time needed for these two transfers per line is * 1. =. s. Since this is more than.8 s, the sensor must be run at a higher pixel rate and the video must be buffered. According to Equation 1, the pixel rate required for interlaced operation is 0.8 MHz.

3 Interlaced Operation with Electronic Shuttering Each Line If interlaced operation and electronic shuttering of each line are both required, the following tasks must be performed during each shift period: Shutter pulse (.0 s) Shutter delay (1.0 s) VCCD Transfer (1. s) HCCD delay (1. s) VCCD Transfer (1. s) HCCD delay (1. s) A total time of 9. seconds is needed to perform these operations. According to Equation 1. this requires a pixel rate of 8.8 MHz and buffering of the video. SUMMARY Table. PIXEL RATE SUMMARY Scan Mode Progressive scan with shuttering once per frame Progressive scan with shuttering once per line Required Pixel Rate (MHz) Interlaced with shuttering once per frame 0.8 Interlaced with shuttering once per line 8.8 In the KAI 09 sensor specification, all sensor performance parameters are measured at 0 MHz. ON Semiconductor cannot guarantee that the sensor will meet these specifications when operated at speeds greater than 0 MHz. Increased sensor noise should be expected when operating the sensor at speeds greater than 0 MHz. APPENDIX KAI 09 TIMING Table. KAI 09 TIMING REQUIREMENTS Symbol Description Min. Nom. Max. Units T HD HCCD Delay s T VCCD VCCD Transfer Time s Photodiode Transfer Time s VCCD Pedestal Time 0 0 s VCCD Delay s T R Reset Pulse Time 10 ns T S Shutter Pulse Time 10 s T SD Shutter Pulse Delay s T H HCCD Clock Period 0 00 ns T VR VCCD Rise/Fall Time s

4 Progressive Frame Timing = VE = VO Line 1091 Line 109 Line 1 Frame Timing for Vertical Binning by = VE = VO Line Line Line 1 Figure. Progressive Frame Timing

5 Interlaced Frame Timing Field Integration Mode Even Field Readout = VE = VO Interlaced Frame Timing Field Integration Mode Odd Field Readout = VE = VO Figure. Interlaced Frame Timing Field Integration Mode

6 Interlaced Frame Timing Frame Integration Mode Even Field Readout E O E O Figure. Interlaced Frame Timing Frame Integration Mode

7 Progressive Line Timing T VCCD T HD φr Single Output Pixel Count Dual Output Interlaced Line Timing and Line Timing for Vertical Binning by Two E, O x T VCCD T HD φr Single Output Pixel Count Dual Output Pixel Count Figure. Line Timing 7

8 Electronic Shutter Line Timing T VCCD Vshutter T HD T S VSUB T SD φr Integration Time Definition Vshutter Integration Time VSUB Figure. Electronic Shutter Timing Diagram ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 1, Denver, Colorado 8017 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND9191/D

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