NOT RECOMMENDED FOR NEW DESIGNS - THE ISL IS A 100% COMPATIBLE IMPROVED ALTERNATIVE. Features. Offset DAC PGA. 8 bit ADC.

Transcription

1 40MHz Triple Video Digitizer with Digital PLL NOT RECOMMENDED FOR NEW DESIGNS - THE ISL IS 00% COMPTIBLE IMPROVED LTERNTIVE DTSHEET FN27 Rev 3.00 The X904 3-channel, -bit nalog Front End (FE) contains all the components necessary to digitize analog RGB or YUV graphics signals from personal computers, workstations and video set-top boxes. The fully differential analog design provides high PSRR and dynamic performance to meet the stringent requirements of the graphics display industry. The FE s 40MSPS conversion rate supports resolutions up to SXG at 75Hz refresh rate, while the front end's high input bandwidth ensures sharp images at the highest resolutions. To minimize noise, the X904's analog section features 2 sets of pseudo-differential RGB inputs with programmable input bandwidth, as well as internal DC restore clamping (including mid-scale clamping for YUV signals). This is followed by the programmable gain/offset stage and the three 40MSPS nalog-to-digital Converters (DCs). utomatic Black Level Compensation (BLC eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The X904's digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 0MHz to 40MHz with sampling clock jitter of 250ps peak to peak. Features 40MSPS maximum conversion rate Low PLL clock jitter (250ps 40MSPS) 64 interpixel sampling positions 0.35V p-p to.4v p-p video input range Programmable bandwidth (00MHz to 70MHz) 2 channel input multiplexer RGB and YUV 4:2:2 output formats 5 embedded voltage regulators allow operation from single 3.3V supply and enhance performance, isolation Completely independent bit gain/0 bit offset control CSYNC and SOG support Trilevel sync detection 990mW typical P 40MSPS Pb-free plus anneal available (RoHS compliant) pplications LCD Monitors and Projectors Digital TVs Plasma Display Panels RGB Graphics Processing Scan Converters Simplified Block Diagram RGB/YPbPr IN RGB/YPbPr IN Voltage Clamp PG + Offset DC BLC bit DC or 6 x3 RGB/YUV OUT HSYNC OUT SOG IN /2 HSYNC IN /2 VSYNC IN /2 Sync Processing Digital PLL VSYNC OUT HS OUT PIXELCLK OUT FE Configuration and Control FN27 Rev 3.00 Page of 29

2 Ordering Information PRT NUMBER PRT MRKING MXIMUM PIXEL RTE TEMP RNGE ( C) PCKGE X904L2-3.3 X904L MHz 0 to 70 2 MQFP X904L2-3.3-Z (See Note) X904L-3.3Z 40MHz 0 to 70 2 MQFP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram V CLMP Offset DC 0 BLC R IN R IN 2 V IN + V IN - PG + bit DC R P R S V CLMP Offset DC 0 BLC G IN RGB GND G IN 2 RGB GND 2 B IN B IN 2 V IN + V IN - PG + bit DC V IN + V CLMP Offset DC V IN - PG + bit DC 0 BLC Output Data Formatter G P G S B P B S DTCLK SOG IN SOG IN 2 HSYNC IN HSYNC IN 2 VSYNC IN Sync Processing FE Configuration and Control DTCLK HS OUT VS OUT VSYNC IN 2 HSYNC OUT CLOCKINV XTL IN Digital PLL VSYNC OUT XTLCLK OUT XTL OUT SCL SD SDDR Serial Interface FN27 Rev 3.00 Page 2 of 29

3 bsolute Maximum Ratings Voltage on V, V D, or V X (referenced to GND =GND D =GND X ) V Voltage on any analog input pin (referenced to GND ) V to V Voltage on any digital input pin (referenced to GND D ) V to +6.0V Current into any output pin 20m Operating Temperature range C to +70 C Junction Temperature C Storage Temperature C to +50 C Recommended Operating Conditions Temperature (Commercial) C to +70 C Supply Voltage V = V D = V X = 3.3V CUTION: Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. T Electrical Specifications Specifications apply for V = V D = V X = 3.3V, pixel rate = 40MHz, f XTL = 25MHz, T = 25 C, unless otherwise noted SYMBOL PRMETER COMMENT MIN TYP MX UNIT FULL CHNNEL CHRCTERISTICS DC Resolution Bits Missing Codes Guaranteed monotonic None Conversion Rate Per Channel 0 40 MHz DNL Differential Non-Linearity ± LSB INL Integral Non-Linearity ±. ±2.75 LSB Gain djustment Range ±6 db Gain djustment Resolution Bits Gain Matching Between Channels Percent of full scale ± % Full Channel Offset Error, BLC enabled DC LSBs, over time and temperature ±0.25 ±0.5 LSB Offset djustment Range, BLC enabled or disabled Overvoltage Recovery Time DC LSBs (see BLC applications information section) For 50% overrange, maximum bandwidth setting ±27 LSB 5 ns NLOG VIDEO INPUT CHRCTERISTICS (R IN, G IN, B IN, R IN 2, G IN 2, B IN 2) Input Range V P-P Input Bias Current DC restore clamp off ±0.0 ± µ Input Capacitance 5 pf Full Power Bandwidth Programmable 70 MHz INPUT CHRCTERISTICS (SOG IN, SOG IN 2) V IH /V IL Input Threshold Voltage Programmable - See Register Listing for Details 0 to -0.3 V Hysteresis Centered around threshold voltage 40 mv Input capacitance 5 pf INPUT CHRCTERISTICS (HSYNC IN, HSYNC IN 2) V IH /V IL Input Threshold Voltage Programmable - See Register Listing for Details 0.4 to 3.2 V Hysteresis Centered around threshold voltage 240 mv R IN Input impedance.2 k FN27 Rev 3.00 Page 3 of 29

4 Electrical Specifications Specifications apply for V = V D = V X = 3.3V, pixel rate = 40MHz, f XTL = 25MHz, T = 25 C, unless otherwise noted (Continued) SYMBOL PRMETER COMMENT MIN TYP MX UNIT Input capacitance 5 pf DIGITL INPUT CHRCTERISTICS (SD, SDDR, CLOCKINV IN, RESET) V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0. V I Input leakage current RESET has a 70k pullup to V D ±0 n Input capacitance 5 pf SCHMITT DIGITL INPUT CHRCTERISTICS (SCL, VSYNC IN, VSYNC IN 2) V T + Low to High Threshold Voltage.45 V V T - High to Low Threshold Voltage 0.95 V I Input leakage current ±0 n Input capacitance 5 pf DIGITL OUTPUT CHRCTERISTICS (DTCLK, DTCLK) V OH Output HIGH Voltage, I O = 6m 2.4 V V OL Output LOW Voltage, I O = -6m 0.4 V DIGITL OUTPUT CHRCTERISTICS (R P, G P, B P, R S, G S, B S, HS OUT, VS OUT, HSYNC OUT, VSYNC OUT ) V OH Output HIGH Voltage, I O = m 2.4 V V OL Output LOW Voltage, I O = -m 0.4 V R TRI Pulldown to GND D when three-state R P, G P, B P, R S, G S, B S only 5 k DIGITL OUTPUT CHRCTERISTICS (SD, XTLCLK OUT ) V OH Output HIGH Voltage, I O = 4m XTLCLK OUT only; SD is open-drain 2.4 V V OL Output LOW Voltage, I O = -4m 0.4 V POWER SUPPLY REQUIREMENTS V nalog Supply Voltage V V D Digital Supply Voltage V V X Crystal Oscillator Supply Voltage V I nalog Supply Current Operating 0 90 m I D Digital Supply Current Operating (grayscale) m I X Crystal Oscillator Supply Current m P D Total Power Dissipation Operating (average).0.5 W Power-down mode 50 0 mw J Thermal Resistance, Junction to mbient 30 C/W C TIMING CHRCTERISTICS PLL Jitter ps p-p Sampling Phase Steps 5.6 per step 64 Sampling Phase Tempco ± ps/ C Sampling Phase Differential Nonlinearity Degrees out of 360 ±3 HSYNC Frequency Range 0 50 khz f XTL Crystal Frequency Range MHz FN27 Rev 3.00 Page 4 of 29

5 Electrical Specifications Specifications apply for V = V D = V X = 3.3V, pixel rate = 40MHz, f XTL = 25MHz, T = 25 C, unless otherwise noted (Continued) SYMBOL PRMETER COMMENT MIN TYP MX UNIT t SETUP DT valid before rising edge of DTCLK 5pF DTCLK load, 5pF DT load (Note ) t HOLD DT valid after rising edge of DTCLK 5pF DTCLK load, 5pF DT load (Note ).3 ns 2.0 ns C TIMING CHRCTERISTICS (2 WIRE INTERFCE) f SCL SCL Clock Frequency khz Maximum width of a glitch on SCL that will be suppressed 2 XTL periods min 0 ns t SCL LOW to SD Data Out Valid 5 XTL periods plus SD s RC time constant See comment µs t BUF Time the bus must be free before a new transmission can start.3 µs t LOW Clock LOW Time.3 µs t HIGH Clock HIGH Time 0.6 µs t SU:ST Start Condition Setup Time 0.6 µs t HD:ST Start Condition Hold Time 0.6 µs t SU:DT Data In Setup Time 00 ns t HD:DT Data In Hold Time 0 ns t SU:STO Stop Condition Setup Time 0.6 µs t DH Data Output Hold Time 4 XTL periods min 60 ns NOTES:. Setup and hold times are at a 40MHz DTCLK rate. t F t HIGH t LOW t R SCL t SU:DT t SU:ST t HD:ST t HD:DT t SU:STO SD IN t t DH t BUF SD OUT FIGURE. 2 WIRE INTERFCE TIMING DTCLK DTCLK t SETUP t HOLD Pixel Data FIGURE 2. DT OUTPUT SETUP ND HOLD TIMING FN27 Rev 3.00 Page 5 of 29

6 HSYNC IN The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the FE s output signals t HSYNCin-to-HSout = 7.5ns + (PHSE/64 +.5)*t PIXEL nalog Video In P 0 P P 2 P 3 P 4 P 5 P 6 P 7 P P 9 P 0 P P 2 DTCLK R P /G P /B P.5 DTCLK Pipeline Latency D 0 D D 2 D 3 R S /G S /B S HS OUT Programmable Width and Polarity FIGURE BIT OUTPUT MODE HSYNC IN Th HSYNC d ( bl l di t ili ) th t th DPLL i l k d t The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the FE s output signals t HSYNCin-to-HSout = 7.5ns + (PHSE/64 +.5)*t PIXEL nalog Video In P 0 P P 2 P 3 P 4 P 5 P 6 P 7 P P 9 P 0 P P 2 DTCLK.5 DTCLK Pipeline Latency G P G 0 (Y o ) G (Y ) G 2 (Y 2 ) R P B 0 (U o ) R (V ) B 2 (U 2 ) B P HS OUT Programmable Width and Polarity FIGURE BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNLS) FN27 Rev 3.00 Page 6 of 29

7 HSYNC IN The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the FE s output signals t HSYNCin-to-HSout = 7.5ns + (PHSE/ )*t PIXEL nalog Video In P 0 P P 2 P 3 P 4 P 5 P 6 P 7 P P 9 P 0 P P 2 DTCLK R P /G P /B P D 0 D 2 R S /G S /B S D D 3 HS OUT Programmable Width and Polarity FIGURE 5. 4 BIT OUTPUT MODE HSYNC HSYNC IN The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the FE s output signals t HSYNCin-to-HSout = 7.5ns + (PHSE/64 +.5)*t PIXEL nalog Video In P 0 P P 2 P 3 P 4 P 5 P 6 P 7 P P 9 P 0 P DTCLK R P /G P /B P D 0 D 2 R S /G S /B S D HS OUT Programmable Width and Polarity FIGURE 6. 4 BIT OUTPUT MODE, INTERLEVED TIMING FN27 Rev 3.00 Page 7 of 29

8 Pinout X904 (2-PIN MQFP) TOP VIEW NC 02 R S 5 NC 2 0 R S 6 GND 3 00 R S 7 V BYPSS 4 99 V D GND 5 9 GND D V 6 97 G P 0 R IN 7 96 G P GND 95 G P 2 V BYPSS 9 94 G P 3 GND 0 93 G P 4 V 92 G P 5 G IN 2 9 G P 6 RGB GND 3 90 G P 7 SOG IN 4 9 V D GND 5 GND D V BYPSS 6 7 G S 0 GND 7 6 G S V 5 G S 2 B IN 9 4 G S 3 V 20 3 G S 4 GND 2 2 G S 5 R IN 2 22 G S 6 GND 23 0 G S 7 G IN V CORE RGB GND GND D SOG IN V D GND GND D B IN B P 0 V B P GND B P 2 V COREDC 3 72 B P 3 GND D 32 7 B P 4 HSYNC IN B P 5 HSYNC IN B P 6 V 35 6 B P 7 GND V D GND X GND D V X 3 65 VREG IN XTLIN XTLOUT CLOCKINVIN V PLL GNDD VSYNCIN VSYNCIN2 RESET XTLCLOCKOUT S DDR SD SCL GNDD V CORE GNDD V D B S 7 B S 6 B S 5 B S 4 B S 3 B S 2 B S B S 0 NC VREGOUT VSYNCOUT HSYNCOUT VSOUT HS OUT V D GNDD DTCLK DTCLK GNDD R P 0 R P R P 2 R P 3 R P 4 R P 5 R P 6 R P 7 V D GNDD V CORE GNDD R S 0 R S R S 2 R S 3 R S 4 FN27 Rev 3.00 Page of 29

9 Pin Descriptions SYMBOL PIN DESCRIPTION R IN 7 nalog input. Red channel. DC couple or C couple through 0.µF. G IN 2 nalog input. Green channel. DC couple or C couple through 0.µF. B IN 9 nalog input. Blue channel. DC couple or C couple through 0.µF. RGB GND 3 nalog input. Ground reference for the R, G, and B inputs of channel in the DC coupled configuration. Connect to the same ground as channel 's R, G, and B termination resistors. This signal is not used in the C-coupled configuration, but the pin should still be tied to GND. SOG IN 4 nalog input. Sync on Green. Connect to G IN through a 0.0µF capacitor in series with a 500 resistor. HSYNC IN 33 Digital input, 5V tolerant, 240mV hysteresis,.2k impedance to GND. Connect to channel 's HSYNC signal through a 60 series resistor. VSYNC IN 44 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 's VSYNC signal. R IN 2 22 nalog input. Red channel 2. DC couple or C couple through 0.µF. G IN 2 24 nalog input. Green channel 2. DC couple or C couple through 0.µF. B IN 2 2 nalog input. Blue channel 2. DC couple or C couple through 0.µF. RGB GND 2 25 nalog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration. Connect to the same ground as channel 's R, G, and B termination resistors. This signal is not used in the C-coupled configuration, but the pin should still be tied to GND. SOG IN 2 26 nalog input. Sync on Green. Connect to G IN through a 0.0µF capacitor in series with a 500 resistor. HSYNC IN 2 34 Digital input, 5V tolerant, 240mV hysteresis,.2k impedance to GND. Connect to channel 2's HSYNC signal through a 60 series resistor. VSYNC IN 2 45 Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal. CLOCKINV IN 4 Digital input, 5V tolerant. When high, changes the pixel sampling phase by 0 degrees. Toggle at frame rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D GND if unused. RESET 46 Digital input, 5V tolerant, active low, 70k pull-up to V D. Take low for at least µs and then high again to reset the X904. This pin is not necessary for normal use and may be tied directly to the V D supply. XTL IN 39 nalog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is.0v P-P centered around 0.5V. XTL OUT 40 nalog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is.0v P-P centered around 0.5V. XTLCLK OUT V digital output. Buffered crystal clock output at f XTL or f XTL /2. May be used as system clock for other system components. SDDR 4 Digital input, 5V tolerant. ddress = 0x4C (0x9 including R/W bit) when tied low. ddress = 0x4D (0x9 including R/W bit) when tied high. SCL 50 Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface. SD 49 Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface. R P V digital output. Red channel, primary pixel data. 5K pulldown when three-stated. R S V digital output. Red channel, secondary pixel data. 5K pulldown when three-stated. G P V digital output. Green channel, primary pixel data. 5K pulldown when three-stated. G S V digital output. Green channel, secondary pixel data. 5K pulldown when three-stated. B P V digital output. Blue channel, primary pixel data. 5K pulldown when three-stated. B S V digital output. Blue channel, secondary pixel data. 5K pulldown when three-stated. DTCLK 2 3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 4 bit mode. DTCLK V digital output. Inverse of DTCLK. FN27 Rev 3.00 Page 9 of 29

10 Pin Descriptions (Continued) SYMBOL PIN DESCRIPTION HS OUT V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals) VS OUT V digital output.rtificial VSYNC output aligned with pixel data. VSYNC is generated pixel clocks after the trailing edge of HS OUT. This signal is usually not needed - use VSYNC OUT as VSYNC source. HSYNC OUT V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC period. HS OUT should be used to detect the beginning of a line. This output will pass composite sync signals and Macrovision signals if present on HSYNC IN or SOG IN. VSYNC OUT 2 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a frame and measure the VSYNC period. V 6,,, 20, 29, 35 GND 3, 5,, 0, 5, 7, 2, 23, 27, 30, 36 V D 54, 67, 77, 9, 99,, 24 GND D 32, 43, 5, 53, 66, 76, 7,, 9, 0, 0, 20, 23 Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND with 0.µF. Ground return for V and V BYPSS. Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND D with 0.µF. Ground return for V D, V CORE, V COREDC, and V PLL. V X 3 Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND X with 0.µF. GND X 37 Ground return for V X. V BYPSS 4, 9, 6 Bypass these pins to GND with 0.µF. Do not connect these pins to each other or anything else. VREG IN V input voltage for V CORE voltage regulator. Connect to a 3.3V source, and bypass to GND D with 0.µF. VREG OUT 64 Regulated output voltage for V PLL, V COREDC and V CORE ; typically.9v. Connect only to V PLL, V COREDC and V CORE and bypass at input pins as instructed below. Do not connect to anything else - this output can only supply power to V PLL, V COREDC and V CORE. V COREDC 3 Internal power for the DC s digital logic. Connect to VREG OUT through a 0 resistor and bypass to GND D with 0.µF. V PLL 42 Internal power for the PLL s digital logic. Connect to VREG OUT through a 0 resistor and bypass to GND D with 0.µF. V CORE 52, 79, 09 Internal power for core logic. Connect to VREG OUT and bypass each pin to GND D with 0.µF. NC, 2, 63 Reserved. Do not connect anything to these pins. FN27 Rev 3.00 Page 0 of 29

11 Register Listing DDRESS REGISTER (DEFULT VLUE) BIT(s) FUNCTION NME DESCRIPTION 0x0 SYNC Status (read only) 0 HSYNC ctive 0: HSYNC is Inactive : HSYNC is ctive HSYNC2 ctive 0: HSYNC2 is Inactive : HSYNC2 is ctive 2 VSYNC ctive 0: VSYNC is Inactive : VSYNC is ctive 3 VSYNC2 ctive 0: VSYNC2 is Inactive : VSYNC2 is ctive 4 SOG ctive 0: SOG is Inactive : SOG is ctive 5 SOG2 ctive 0: SOG2 is Inactive : SOG2 is ctive 6 PLL Locked 0: PLL is unlocked : PLL is locked to incoming HSYNC 7 CSYNC Detected at Sync Splitter Output 0: Composite Sync signal not detected : Composite Sync signal is detected 0x02 SYNC Polarity (read only) 0 HSYNC Polarity 0: HSYNC is ctive High : HSYNC is ctive Low HSYNC2 Polarity 0: HSYNC2 is ctive High : HSYNC2 is ctive Low 2 VSYNC Polarity 0: VSYNC is ctive High : VSYNC is ctive Low 3 VSYNC2 Polarity 0: VSYNC2 is ctive High : VSYNC2 is ctive Low 4 HSYNC Trilevel 0: HSYNC is Standard Sync : HSYNC is Trilevel Sync 5 HSYNC2 Trilevel 0: HSYNC2 is Standard Sync : HSYNC2 is Trilevel Sync 7:6 N/ Returns 0 0x03 HSYNC Slicer (0x44) 2:0 HSYNC Threshold 000 = lowest (0.4V) ll values referred to 00 = default (2.0V) voltage at HSYNC input = highest (3.2V) pin, 240mV hysteresis 3 Reserved Set to 00 6:4 HSYNC2 Threshold See HSYNC 7 Disable Glitch Filter 0: HSYNC/VSYNC Digital Glitch Filter Enabled (default) : HSYNC/VSYNC Digital Glitch Filter Disabled 0x04 SOG Slicer (0x0) 3:0 SOG and SOG2 Threshold 4 SOG Filter Enable 5 SOG Hysteresis Disable 0x0 = lowest (0mV) 40mV hysteresis at 0x = default (60mV) all settings 0xF = highest (300mV) 20mV step size 0: SOG low pass filter disabled (default) : SOG low pass filter enabled, 4MHz corner 0: 40mV SOG hysteresis enabled : 40mV SOG hysteresis disabled (default) 7:6 Reserved Set to 00. FN27 Rev 3.00 Page of 29

12 Register Listing (Continued) DDRESS REGISTER (DEFULT VLUE) BIT(s) FUNCTION NME DESCRIPTION 0x05 Input configuration (0x00) 0 Channel Select 0: VG : VG2 Input Coupling 0: C coupled (positive input connected to clamp DC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DC) : DC coupled (+ and - inputs are brought to pads and never connected to clamp DCs). nalog clamp signal is turned off in this mode. 2 RGB/YUV 0: RGB inputs (Clamp DC = 300mV for R, G, B, half scale analog shift for R, G, and B, base BLC target code = 0x00 for R, G, and B) : YUV inputs (Clamp DC = 600mV for R and B, 300mV for G, half scale analog shift for G channel only, base BLC target code = 0x00 for G, = 0x0 for R and B) 3 Sync Type 0: Separate HSYNC/VSYNC : Composite (from SOG or CSYNC on HSYNC) 4 Composite Sync Source 5 COST CLMP enable 0: SOG IN : HSYNC IN Note: If Sync Type = 0, the multiplexer will pass HSYNC IN regardless of the state of this bit. 0: DC restore clamping and BLC suspended during COST : DC restore clamping and BLC continue during COST 7:6 Reserved Set to 00. 0x06 Red Gain (0x55) 7:0 Red Gain Channel gain, where: gain (V/V) = /70 0x07 Green Gain (0x55) 7:0 Green Gain 0x0 Blue Gain (0x55) 7:0 Blue Gain 0x00: gain = 0.5 V/V (.4VP-P input = full range of DC) 0x55: gain =.0 V/V (0.7VP-P input = full range of DC) 0xFF: gain = 2.0 V/V (0.35VP-P input = full range of DC) 0x09 0x0 Red Offset (0x0) Green Offset (0x0) 7:0 7:0 Red Offset Green Offset BLC enabled: digital offset control. LSB change in this register will shift the DC output by LSB. BLC disabled: analog offset control. These bits go to the upper bits of the 0 bit offset DC. LSB change in this 0x0B Blue Offset (0x0) 7:0 Blue Offset register will shift the DC output approximately LSB (Offset DC range = 0) or 0.5LSBs (Offset DC range = ). 0x00 = min DC value or -0x0 digital offset, 0x0 = mid DC value or 0x00 digital offset, 0xFF = max DC value or +0x7F digital offset 0x0C Offset DC Configuration (0x00) 0 Offset DC Range 0: ±/2 DC fullscale ( DC LSB ~ DC LSB) : ±/4 DC fullscale ( DC LSB ~ /2 DC LSB) Reserved Set to 0. 3:2 Red Offset DC LSBs These bits are the LSBs necessary for 0 bit manual offset DC control. 5:4 Green Offset DC Combine with their respective MSBs in registers 0x09, 0x0, LSBs and 0x0B to achieve 0 bit offset DC control. 7:6 Blue Offset DC LSBs FN27 Rev 3.00 Page 2 of 29

13 Register Listing (Continued) DDRESS REGISTER (DEFULT VLUE) BIT(s) FUNCTION NME DESCRIPTION 0x0D FE Bandwidth (0x0E) 0 Unused Value doesn t matter 3: FE BW 3dB point for FE lowpass filter 000: 00MHz : 70MHz (default) 7:4 Peaking 0000: Disabled (default) See Bandwidth and Peaking Control section for more information 0x0E PLL Htotal MSB (0x03) 5:0 PLL Htotal MSB 4 bit HTOTL (number of active pixels) value 0x0F PLL Htotal LSB (0x20) 7:0 PLL Htotal LSB The minimum HTOTL value supported is 0x200. HTOTL to PLL is updated on LSB write only. 0x0 PLL Sampling Phase (0x00) 5:0 PLL Sampling Phase Used to control the phase of the DC s sample point relative to the period of a pixel. djust to obtain optimum image quality. One step = (.56% of pixel period). 0x PLL Pre-coast (0x0) 7:0 Pre-coast Number of lines the PLL will coast prior to the start of VSYNC. pplies only to internally generated COST signals. 0x2 PLL Post-coast (0x00) 7:0 Post-coast Number of lines the PLL will coast after the end of VSYNC. pplies only to internally generated COST signals. 0x3 PLL Misc (0x00) 0 PLL Lock Edge HSYNC PLL Lock Edge HSYNC2 0: Lock on trailing edge of HSYNC (default) : Lock on leading edge of HSYNC 0: Lock on trailing edge of HSYNC2 (default) : Lock on leading edge of HSYNC2 2 Reserved Set to 0. 3 CLKINV IN Pin Disable 0: CLKINV IN pin enabled (default) : CLKINV IN pin disabled (internally forced low) 5:4 CLKINV IN Pin Function 00: CLKINV (default) 0: External CLMP (see Note) 0: External COST : External PIXCLK Note: the CLMP pulse is used to - perform a DC restore (if enabled) - start the BLC function (if enabled), and - update the data to the Offset DCs (always). When in the default internal CLMP mode, the X904 automatically generates the CLMP pulse. If External CLMP is selected, the Offset DC values will only change on the leading edge of CLMP. If there is no internal clamp signal, there will be up to a 00ms delay between when the PG gain or offset DC register is written to, and when the PG or offset DC is actually updated. 6 XTLCLKOUT Frequency 0: XTLCLK OUT = f CRYSTL (default) : XTLCLK OUT = f CRYSTL /2 7 Disable XTLCLKOUT 0 = XTLCLK OUT enabled = XTLCLK OUT is logic low 0x4 0x5 DC Restore and BLC starting pixel MSB (0x00) DC Restore and BLC starting pixel LSB (0x00) 4:0 DC Restore and BLC starting pixel (MSB) 7:0 DC Restore and BLC starting pixel (LSB) Pixel after HSYNC IN trailing edge to begin DC restore and BLC functions. 3 bits. Set this register to the first stable black pixel following the trailing edge of HSYNC IN. 0x6 DC Restore Clamp Width (0x0) 7:0 DC Restore clamp width (pixels) Width of DC restore clamp used in C-coupled configurations. Has no effect on BLC. Minimum value is 0x02 (a setting of 0x0 or 0x00 will not generate a clamp pulse). FN27 Rev 3.00 Page 3 of 29

14 Register Listing (Continued) DDRESS REGISTER (DEFULT VLUE) BIT(s) FUNCTION NME DESCRIPTION 0x7 BLC Configuration (0x40) 0 BLC disable 0: BLC enabled (default) : BLC disabled Reserved Set to 0. 3:2 BLC pixel width Number of black pixels averaged every line for BLC function 00: 6 pixels [default] 0: 32 pixels 0: 64 pixels : 2 pixels 6:4 BLC bandwidth BLC Time constant (lines) = 2 (5+[6:4]) 000 = 32 lines 00 = 52 lines (default) = 4096 lines 7 Reserved Set to 0. 0x Output Format (0x00) 0 Bus Width 0: 24 bits: Data output on R P, G P, B P only; R S, G S, B S are all driven low (default) : 4 bits: Data output on R P, G P, B P, R S, G S, B S Interleaving (4 bit mode only) 2 Bus Swap (4 bit mode only) 0: No interleaving: data changes on same edge of DTCLK (default) : Interleaved: Secondary databus data changes on opposite edge of DTCLK from primary databus 0: First data byte after trailing edge of HSOUT appears on R P, G P, B P (default) : First data byte after trailing edge of HSOUT appears on R S, G S, B S (primary and secondary busses are reversed) 3 Reserved Set to (24 bit mode only) 5 DTCLK Polarity 0: Data is formatted as 4:4:4 (RGB, default) : Data is decimated to 4:2:2 (YUV), blue channel is driven low 0: HS OUT, VS OUT, and Pixel Data change on falling edge of DTCLK (default) : HS OUT, VS OUT, and Pixel Data change on rising edge of DTCLK 6 VSOUT Polarity 0: ctive High (default) : ctive Low 7 HSOUT Polarity 0: ctive High (default) : ctive Low 0x9 HSOUT Width (0x0) 7:0 HSOUT Width HSOUT width, in pixels. Minimum value is 0x0 for 24 bit modes, 0x02 for 4 bit modes. 0x Output Signal Disable (0x00) 0 Three-state R P 0 = Output byte enabled Three-state R S = Output byte three-stated These bits override all other I/O settings 2 Three-state G P Output data pins have 5k pulldown resistors to GND D. 3 Three-state G S 4 Three-state B P 5 Three-state B S 6 Three-state DTCLK 7 Three-state DTCLK 0 = DTCLK enabled = DTCLK three-stated 0 = DTCLK enabled = DTCLK three-stated FN27 Rev 3.00 Page 4 of 29

15 Register Listing (Continued) DDRESS REGISTER (DEFULT VLUE) BIT(s) FUNCTION NME DESCRIPTION 0xB Power Control (0x00) 0 Red Power Down Green Power Down 2 Blue Power Down 3 PLL Power Down 0 = Red DC operational (default) = Red DC powered down 0 = Green DC operational (default) = Green DC powered down 0 = Blue DC operational (default) = Blue DC powered down 0 = PLL operational (default) = PLL powered down 7:4 Reserved Set to 0 0xC Reserved (0x47) 7:0 Reserved Set to 0x49 for best performance with NTSC and PL video 0x23 DC Restore Clamp (0x0) 3:0 Reserved Set to 000 6:4 DC Restore Clamp Impedance DC Restore clamp's ON resistance. Shared for all three channels 0: Infinite (clamp disconnected) (default) : 600 2: 00 3: 533 4: 400 5: 320 6: 267 7: 22 7 Reserved Set to 0 Technical Highlights The X904 provides all the features of traditional triple channel video FEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL ll video FEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically this function has been implemented as a traditional analog PLL. t SXG and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum tradeoff for a wide range of pixel rates). s display resolutions and refresh rates have increased, however, the pixel period has decreased. n XG pixel at a 60Hz refresh rate has 5.4ns to change and settle to its new value. But at UXG 75Hz, the pixel period is 4.9ns. Most consumer graphics cards spend most of that time slewing to the new pixel value. The pixel may settle to its final value with ns or less before it begins slewing to the next pixel. In many cases it never settles at all. So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The X904's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point. The crystal-locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. n intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (0MHz or higher) to SXG 75Hz (40MHz). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. utomatic Black Level Compensation (BLC ) and Gain Control Traditional video FEs have an offset DC prior to the DC, to both correct for offsets on the incoming video signals and add/subtract an offset for user brightness control. This solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then servos the offset DCs until that offset is nulled (or produces the desired DC output code). Once this has been accomplished, the offset (both the offset in the FE and the offset of the video card generating the signal) is subject to drift - the temperature inside a monitor or projector can easily change 50 C between power-on/offset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment have reached steady state. Offset can drift significantly over 50 C, reducing FN27 Rev 3.00 Page 5 of 29

16 image quality and requiring that the user do a manual calibration once the monitor has warmed up. In addition to drift, many FEs exhibit interaction between the offset and gain controls. When the gain is changed, the magnitude of the offset is changed as well. This again increases the complexity of the firmware as it tries to optimize gain and offset settings for a given video input signal. Instead of adjusting just the offset, then the gain, both have to be adjusted interactively until the desired DC output is reached. The X904 simplifies offset and gain adjustment and completely eliminates offset drift using its utomatic Black Level Compensation (BLC ) function. BLC monitors the black level and continuously adjusts the X904's 0 bit offset DCs to null out the offset. ny offset, whether due to the video source or the X904's analog amplifiers, is eliminated with 0 bit (/4 of an bit DC LSB) accuracy. ny drift is compensated for well before it can have a visible effect. Manual offset adjustment control is still available - an bit register allows the firmware to adjust the offset ±64 codes in exactly DC LSB increments. nd gain is now completely independent of offset - adjusting the gain no longer affects the offset, so there is no longer a need to program the firmware to cope with interactive offset and gain controls. Finally, there should be no concerns over BLC itself introducing visible artifacts; it doesn't. BLC operates at a very low frequency, changing the offset in /4 LSB increments, so it doesn't cause visible brightness fluctuations. nd once BLC is locked, if the offset doesn't drift, the DCs won't change. If desired, BLC can be disabled, allowing the firmware to work in the traditional way, with 0 bit offset DCs under the firmware's control. Gain and Offset Control To simplify image optimization algorithms, the X904 features fully-independent gain and offset adjustment. Changing the gain does not affect the DC offset, and the weight of an Offset DC LSB does not vary depending on the gain setting. The full-scale gain is set in the three -bit registers (0x06-0x0). The X904 can accept input signals with amplitudes ranging from 0.35V P-P to.4v P-P. The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x0, which forces the DC to output code 0x00 (or 0x0 for U and V channels in YUV mode) during the back porch period when BLC is enabled. RGB Inputs For RGB inputs, the black/blank levels are identical and equal to 0V. The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals. Component YUV Inputs In addition to RGB and RGB with SOG, the X904 has an option that is compatible with the component YPbPr and YCbCr video inputs typically generated by DVD players. While the X904 digitizes signals in these color spaces, it does not perform color space conversion; if it digitizes an RGB signal, it outputs digital RGB, while if it digitizes a YPbPr signal, it outputs digital YPbPr. For simplicity s sake we will call these non-rgb signals YUV. The Luminance (Y) signal is applied to the Green Channel and is processed in a manner identical to the Green input with SOG described previously. The color difference signals U and V are bipolar and swing both above and below the black level. When the YUV mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x0. Setting configuration register 0x05[2] = enables the YUV signal processing mode of operation. TBLE. YUV MPPING (4:4:4) INPUT SIGNL X904 INPUT CHNNEL X904 OUTPUT SSIGNMENT OUTPUT SIGNL Y Green Green Y 0 Y Y 2 Y 3 U Blue Blue U 0 U U 2 U 3 V Red Red V 0 V V 2 V 3 The X904 can optionally decimate the incoming data to provide a 4:2:2 output stream (configuration register 0x[4] = ) as shown in Table 2. TBLE 2. YUV MPPING (4:2:2) INPUT SIGNL X904 INPUT CHNNEL X904 OUTPUT SSIGNMENT OUTPUT SIGNL Y Green Green Y 0 Y Y 2 Y 3 U Blue Blue driven low V Red Red U 0 V U 2 V 3 Functional Description Inputs The X904 digitizes analog video inputs in both RGB and Component (YPbPr) formats, with or without embedded sync (SOG). FN27 Rev 3.00 Page 6 of 29

17 Input Coupling Inputs can be either C-coupled (default) or DC-coupled (see register 0x05[]). C coupling is usually preferred since it allows video signals with substantial DC offsets to be accurately digitized. The X904 provides a complete internal DC-restore function, including the DC restore clamp (See Figure 7) and programmable clamp timing (registers 0x4, 0x5, 0x6, and 0x23). When C-coupled, the DC restore clamp is applied every line, a programmable number of pixels after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the clamp will not be applied while the DPLL is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or Macrovision signals. fter the trailing edge of HSYNC, the DC restore clamp is turned on after the number of pixels specified in the DC Restore and BLC Starting Pixel registers (0x4 and 0x5) has been reached. The clamp is applied for the number of pixels specified by the DC Restore Clamp Width Register (0x6). The clamp can be applied to the back porch of the video, or to the front porch (by increasing the DC Restore and BLC Starting Pixel registers so all the active video pixels are skipped). If DC-coupled operation is desired, the input to the DC will be the difference between the input signal (R IN, for example) and that channel s ground reference (RGB GND in that example). SOG For component YUV signals, the sync signal is embedded on the Y channel s video, which is connected to the green input, hence the name SOG (Sync on Green). The horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. The sync tip level is typically 0.3V below the video black level. To minimize the loading on the green channel, the SOG input for each of the green channels should be C-coupled to the X904 through a series combination of a 0nF capacitor and a 500 resistor. Inside the X904, a window comparator compares the SOG signal with an internal 4 bit programmable threshold level reference ranging from 0mV to 300mV below the minimum sync level. The SOG threshold level, hysteresis, and low-pass filter is programmed via register 0x04. If the Sync-On-Green function is not needed, the SOG IN pin(s) may be left unconnected. DC Restoration utomatic Black Level Compensation (BLC ) Loop V CLMP DC Restore Clamp DC CLMP GENERTION To BLC Block Offset DC 0 Fixed Offset BLC 0 0 BLC Offset Control Registers BLC 0x00 Fixed Offset R(GB) IN R(GB) GND R(GB) IN 2 R(GB) GND 2 VG VG2 V IN + V IN PG Input Bandwidth Bandwidth Control bit DC To Output Formatter FIGURE 7. VIDEO FLOW (INCLUDING BLC ) FN27 Rev 3.00 Page 7 of 29

18 CTIVITY 0x0[6:0] & POLRITY 0x02[5:0] DETECT HSYNC IN HSYNC SLICER 0x03[2:0] CSYNC SOURCE HSYNC OUT VSYNC IN SOG IN HSYNC IN 2 VSYNC IN 2 SOG IN 2 SOG SLICER 0xC HSYNC2 SLICER 0x03[6:4] SOG SLICER 0xC 0: VG 0x05[0] : VG2 HSYNC IN SOG IN VSYNC IN 00, 0, : HSYNC IN 0x05[4:3] 0: SOG IN COST GENERTION 0x, 0x2, 0x3[2] SYNC SPLITTER Pixel Data from FE VSYNC 24 SYNC TYPE : SYNC SPLTR 0x05[3] 0: VSYNC IN VSYNC OUT R P R S G P CLOCKINV IN XTL IN XTL OUT 0: PLL 0x0E through 0x3 HS PIXCLK Output Formatter 0x, 0x9, 0x G S B P B S DTCLK DTCLK 2 0x3 [6] : 2 HS OUT VS OUT XTLCLOCK OUT FIGURE. SYNC FLOW SYNC Processing The X904 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync-On-Green (SOG) signal embedded on the Green video input. The X904 has SYNC activity detect functions to help the firmware determine which sync source is available. PG The X904 s Programmable Gain mplifier (PG) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is: Gain V V --- = GainCode where GainCode is the value in the Gain register for that particular color. Note that for a gain of V/V for GainCode should be 5 (0x55). This is a different center value than the 2 (0x0) value used by some other FEs, so the firmware should take this into account when adjusting gains. The PGs are updated by the internal clamp signal once per line. In normal operation this means that there is a maximum delay of one HSYNC period between a write to a Gain register for a particular color and the corresponding change in that channel s actual PG gain. If there is no regular HSYNC/SOG source, or if the external clamp option is enabled (register 0x3[5:4]) but there is no external clamp signal being generated, it may take up to 00ms for a write to the Gain register to update the PG. This is not an issue in normal operation with RGB and YUV signals. Bandwidth and Peaking Control Register 0x0D[3:] controls a low pass filter allowing the input bandwidth to be adjusted with three bit resolution between its default value (0x0E = 70MHz) and its minimum bandwidth (0x00, for 00MHz). Typically the higher the resolution, the higher the desired input bandwidth. To minimize noise, video signals should be digitized with the minimum bandwidth setting that passes sharp edges. FN27 Rev 3.00 Page of 29

19 Table 3 shows the corner frequency for different register settings. TBLE 3. BNDWIDTH CONTROL 0x0D[3:0] VLUE (LSB = x = don t care ) 000x 00x 00x 0x 00x 0x 0x x FE BNDWIDTH 00MHz 30MHz 50MHz 0MHz 230MHz 320MHz 40MHz 70MHz Register 0x0D[7:4] controls a programmable zero, allowing high frequencies to be boosted, restoring some of the harmonics lost due to excessive EMI filtering, cable losses, etc. This control has a very large range, and can introduce high frequency noise into the image, so it should be used judiciously, or as an advanced user adjustment. Table 4 shows the corner frequency of the zero for different peaking register settings. TBLE 4. PEKING CORNER FREQUENCIES 0X0D[7:4] VLUE 0x0 0x 0x2 0x3 0x4 0x5 0x6 0x7 0x 0x9 0x 0xB 0xC 0xD 0xE 0xF ZERO CORNER FREQUENCY Peaking disabled 00MHz 400MHz 265MHz 200MHz 60MHz 35MHz 5MHz 00MHz 90MHz 0MHz 70MHz 65MHz 60MHz 55MHz 50MHz Offset DC The X904 features a 0 bit Digital-to-nalog Converter (DC) to provide extremely fine control over the full channel offset. The DC is placed after the PG to eliminate interaction between the PG (controlling contrast ) and the Offset DC (controlling brightness ). In normal operation, the Offset DC is controlled by the BLC circuit, ensuring that the offset is always reduced to sub-lsb levels (See the following BLC section for more information). When BLC is enabled, the Offset registers (0x09, 0x0, 0x0B) control a digital offset added to or subtracted from the output of the DC. This mode provides the best image quality and eliminates the need for any offset calibration. If desired, BLC can be disabled (0x7[0]=) and the Offset DC programmed manually, with the most significant bits in registers 0x09, 0x0, 0x0B, and the 2 least significant bits in register 0x0C[7:2]. The default Offset DC range is ±27 DC LSBs. Setting 0x0C[0]= reduces the swing of the Offset DC by 50%, making Offset DC LSB the weight of /th of an DC LSB. This provides the finest offset control and applies to both BLC and manual modes. utomatic Black Level Compensation (BLC ) BLC is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the DC and servoing the 0 bit analog DC to force those errors to zero. When BLC is enabled, the user offset control is a digital adder, with bit resolution (See Table 5). When the BLC function is enabled (0x7[0]=0), the BLC function is executed every line after the trailing edge of HSYNC. If register 0x05[5] = 0 (the default), the BLC function will not be triggered while the DPLL is coasting, preventing any composite sync edges, equalization pulses, or Macrovision signals from corrupting the black data and potentially adding a small error in the BLC accumulator. fter the trailing edge of HSYNC, the start of BLC is delayed by the number of pixels specified in registers 0x4 and 0x5. fter that delay, the number of pixels specified by register 0x7[3:2] are averaged together and added to the BLC s accumulator. The accumulator stores the average black levels for the number of lines specified by register 0x7[6:4], which is then used to generate a 0 bit DC value. The default values provide excellent results with offset stability and absolute accuracy better than DC LSB for most input signals. Increasing the BLC pixel width or the BLC bandwidth settings decreases the BLC s absolute DC error further. DC The X904 features 3 fully differential, 40MSPS bit DCs. FN27 Rev 3.00 Page 9 of 29

20 TBLE 5. OFFSET DC RNGE ND OFFSET DC DJUSTMENT OFFSET DC RNGE 0x0C[0] 0 BIT OFFSET DC RESOLUTION BLC 0x7[0] USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09-0x0B ONLY ( BIT OFFSET CONTROL) USER OFFSET CONTROL RESOLUTION USING REGISTERS 0x09-0x0B ND 0x0C[7:2] (0 BIT OFFSET CONTROL) DC LSBs (0.6mV) 0 (BLC on) DC LSB (digital offset control) N/ 0.25 DC LSBs (0.34mV) 0 (BLC on) DC LSB (digital offset control) N/ DC LSBs (0.6mV) 0.25 DC LSBs (0.34mV) (BLC off).0 DC LSB (analog offset control) 0.25 DC LSB (analog offset control) (BLC off) 0.5 DC LSB (analog offset control) 0.25 DC LSB (analog offset control) Clock Generation Digital Phase Lock Loop (DPLL) is employed to generate the pixel clock frequency. The HSYNC input and the external XTL provide a reference frequency to the PLL. The PLL then generates the pixel clock frequency that is equal to the incoming HSYNC frequency times the HTOTL value programmed into registers 0x0E and 0x0F. The stability of the clock is very important and correlates directly with the quality of the image. During each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. t higher frequencies, the pixel time transitions at a faster rate, which makes the stable pixel time even smaller. ny jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately. Sampling Phase The X904 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x0. HSYNC Slicer To further minimize jitter, the HSYNC inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mV steps with 240mV of hysteresis, and a subsequent digital glitch filter that ignores any HSYNC transitions within 00ns of the initial transition. This processing greatly increases the FE s rejection of ringing and reflections on the HSYNC line and allows the FE to perform well even with pathological HSYNC signals. Voltages given above and in the HSYNC Slicer register description are with respect to a 3.3V sync signal at the HSYNC IN input pin. To achieve 5V compatibility, a 60 series resistor should be placed between the HSYNC source and the HSYNC IN input pin. Relative to a 5V input, the hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer step size will be 400mV*5V/3.3V = 600mV per step. The best HSYNC slicer threshold is generally 00mV (00b) when locking on the rising edge of an HSYNC signal, or 2.4V (0b) when locking on the falling edge. SOG Slicer The SOG input has programmable threshold, 40mV of hysteresis, and an optional low pass filter than can be used to remove high frequency video spikes (generated by overzealous video peaking in a DVD player, for example) that can cause false SOG triggers. The SOG threshold sets the comparator threshold relative to the sync tip (the bottom of the SOG pulse). good default SOG slicer threshold setting is 0x6 (hysteresis and low pass filter enabled, threshold lowered slightly to accommodate weak sync tips). SYNC Status and Polarity Detection The SYNC Status register (0x0) and the SYNC Polarity register (0x02) continuously monitor all 6 sync inputs (VSYNC IN, HSYNC IN, and SOG IN for each of 2 channels) and report their status. However, accurate sync activity detection is always a challenge. Noise and repetitive video patterns on the Green channel may look like SOG activity when there actually is no SOG signal, while non-standard SOG signals and trilevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected. s a consequence, not all of the activity detect bits in the X90xx are correct under all conditions. Table 6 shows how to use the SYNC Status register (0x0) to identify the presence of and type of a sync source. The firmware should go through the table in the order shown, stopping at the first entry that matches the activity indicators in the SYNC Status register. Final validation of composite sync sources (SOG or Composite sync on HSYNC) should be done by setting the Input Configuration register (0x05) to the composite sync source determined by this table, and confirming that the CSYNC detect bit is set. The accuracy of the Trilevel Sync detect bit can be increased by multiple reads of the Trilevel Sync detect bit. See the Trilevel Sync Detect section for more details. For best SOG operation, the SOG low pass filter (register 0x04[4]) should always be enabled to reject the high frequency peaking often seen on video signals. FN27 Rev 3.00 Page 20 of 29

21 TBLE 6. SYNC SOURCE DETECTION TBLE HSYNC DETECT VSYNC DETECT SOG DETECT TRILEVEL DETECT RESULT X X Sync is on HSYNC and VSYNC 0 X X Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on HSYNC and confirm that CSYNC detect bit is set Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude is too low to set trilevel detect bit. Use video mode table to determine if this video mode is likely to have trilevel sync, and set clamp start, width values appropriately if it is. 0 0 Sync is composite sync on SOG. Sync is likely to be trilevel X No valid sync sources on any input. HSYNC and VSYNC ctivity Detect ctivity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the SOG activity bit is also set. SOG ctivity Detect The SOG activity detect bit monitors the output of the SOG slicer, looking for 64 consecutive pulses with the same period and duty cycle. If there is no signal on the Green (or Y) channel, the SOG slicer will clamp the video to a DC level and will reject any sporadic noise. There should be no false positive SOG detects if there is no video on Green (or Y). If there is video on Green (or Y) with no valid SOG signal, the SOG activity detect bit may sometimes report false positives (it will detect SOG when no SOG is actually present). This is due to the presence of video with a repetitive pattern that creates a waveform similar to SOG. For example, the desktop of a PC operating system is black during the front porch, horizontal sync, and back porch, then increases to a larger value for the visible portion of the screen. This creates a repetitive video waveform very similar to SOG that may falsely trigger the SOG ctivity detect bit. However, in these cases where there is active video without SOG, the SYNC information will be provided either as separate H and V sync on HSYNC IN and VSYNC IN, or composite sync on HSYNC IN. HSYNC IN and VSYNC IN should therefore be used to qualify SOG. The SOG ctive bit should only be considered valid if HSYNC ctivity Detect = 0. Note: Some pattern generators can output HSYNC and SOG simultaneously, in which case both the HSYNC and the SOG activity bits will be set, and valid. Even in this case, however, the monitor should still choose HSYNC over SOG. TriLevel Sync Detect Unlike SOG detect, the TriLevel Sync detect function does not check for 64 consecutive trilevel pulses in a row, and is therefore less robust than the SOG detect function. It will report false positives for SOG-less video for the same reasons the SOG activity detect does, and should therefore be qualified with both HSYNC and SOG. TriLevel Sync Detect should only be considered valid if HSYNC ctivity Detect = 0 and SOG ctivity Detect =. If there is a SOG signal, the TriLevel Detect bit will operate correctly for standard trilevel sync levels (600mVp-p). In some real-world situations, the peak-to-peak sync amplitude may be significantly smaller, sometimes 300mVp-p or less. In these cases the sync slicer will continue to operate correctly, but the TriLevel Detect bit may not be set. Trilevel detection accuracy can be enhanced by polling the trilevel bit multiple times. If HSYNC is inactive, SOG is present, and the TriLevel Sync Detect bit is read as a, there is a high likelihood there is trilevel sync. CSYNC Present If a composite sync source (either CSYNC on HSYNC or SOG) is selected through bits 3 and 4 of register 0x05, the CSYNC Present bit in register 0x0 should be set. CSYNC Present detects the presence of a low frequency, repetitive signal inside HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source. SYNC Output Signals The X904 has 2 pairs of HSYNC and VSYNC output signals, HSYNC OUT and VSYNC OUT, and HS OUT and VS OUT. HSYNC OUT and VSYNC OUT are buffered versions of the incoming sync signals; no synchronization is done. These signals should be used for mode detection. HS OUT and VS OUT are generated by the X904 s logic and are synchronized to the output DTCLK and the digital pixel data on the output databus. HS OUT is used to signal the start of a new line of digital data. VS OUT is not needed in most applications. Both HSYNC OUT and VSYNC OUT (including the sync separator function) remain active in power down mode. This allows them to be used in conjunction with the Sync Status registers to detect valid video without powering up the X904. HSYNC OUT HSYNC OUT is an unmodified, buffered version of the incoming HSYNC IN or SOG IN signal of the selected channel, with the incoming signal s period, polarity, and width to aid in mode detection. HSYNC OUT will be the same format as the incoming sync signal: either horizontal or composite sync. If a SOG input FN27 Rev 3.00 Page 2 of 29