ANALYSIS OF LOW-POWER AND AREA-EFFICIENT SHIFT REGISTERS USING DIGITAL PULSED LATCHES

Transcription

1 ANALYSIS OF LOW-POWER AND AREA-EFFICIENT SHIFT REGISTERS USING DIGITAL PULSED LATCHES #1G.N.P.JYOTHI,PG Scholar, Dept of ECE (VLSID), Sri Sunflower College of Engineering and Technology, Lankapalli, (A.P),INDIA. #2Mr. D.SRIDHAR M.Tech., (Ph.D) Associate Professor,Head of the Department of ECE,SSCET, Lankapalli,(A.P), INDIA. ID: ABSTRACT: The architecture of a shift register is quite simple. An N-bit shift register is composed of series connected N data flip-flops. The speed of the flip-flop is less important than the area and power consumption because there is no circuit between flip-flips in the shift register. The smallest flip-flop is suitable for the shift register to reduce the area and power consumption. This project proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. The architecture of a shift register is quite simple. An N- bit shift register is composed of series connected N data flip-flops. The speed of the flip-flop is less important than the area and power consumption because there is no circuit between flip-flips in the shift register. The smallest flip-flop is suitable for the shift register to reduce the area and power consumption. Recently, pulsed latches have replaced flip-flops in many applications, because a pulsed latch is much smaller than a flip-flop. But the pulsed latch cannot be used in a shift register due to the timing problem between pulsed latches. Keywords:Area-Efficient, Flip-Flop, Pulsed Clock, Pulsed Latch,Shift Register. I INTRODUCTION A shift register is the basic building block in a VLSI circuit. Shift registers are commonly used in many applications, such as digital filters, communication receivers, and image processing ICs. Recently, as the size of the image data continues to increase due to the high demand for high quality image data, the word length of the shifter register increases to process large image data in image processing ICs. An image-extraction and vector generation VLSI chip uses a 4K-bit shift register. A 10- bit 208 channel output LCD column driver IC uses a 2Kbit shift register. A 16-megapixel CMOS image sensor uses a 45K-bit shift register. As the word length of the shifter register increases, the area and power consumption of the shift register become important design considerations. Fi g. 1. (a) Master-slave flip-flop. (b) Pulsed latch. This paper proposes a low-power and area-efficient shift register using pulsed latches. The shift register solves the timing problem using multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. PAPER AVAILABLE ON 164

2 II.LITERATURE SURVEY Flip-flops and latches (collectively referred to as timing elements inthis paper) are heavily studied circuits, as they have a large impact onboth cycle time and energy consumption in modern synchronous systems. Previous work has focused on the energy-delay productof timing elements (TEs), but real designs include many TEs that arenot on the critical path and this timing slack can be exploited by usingslower, lower energy TEs. Instead of simultaneously optimizing fordelay and energy, critical TEs should be optimized to reduce delay andnoncritical TEs should be optimized to reduce energy. For example,used different structures for critical and noncritical flip-flops inthe context of a logic synthesis design flow. Previous work often measured energy consumption using a limitedset of data patterns with the clock switching every cycle. But real designs have a wide variation in clock and data activityacross different TE instances. For example, low-power microprocessorsmake extensive use of clock gating resulting in manytes whose energy consumption is dominated by input data transitionsrather than clock transitions. Other TEs, in contrast, have negligibledata input activity but are clocked every cycle. Show significant energy savings when each TE instanceis selected from a heterogeneous library of designs, each tunedto a different operating regime. Detailed energy analysis to comparea number of TE designs, including designs that exploit particularcombinations of signal activity and timing slack. We gather statisticson TE activity in a pipelined MIPS microprocessor running SPECint95benchmarks and show that activity-sensitive TE selection can reducetotal TE energy without increasing cycle time. To the best of our knowledge,this paper is the first work that systematically exploits signal activitytogether with timing slack to reduce TE energy by selecting differentstructures. Fig.2.Shift register with latches and a pulsed clock signal (a)schematic(b)wavforms One solution for the timing problem is to add delay circuits between latches, as shown in Fig. 3. The output signal of the latch is delayed and reaches the next latch after the clock pulse. As a result, all latches have constant input signals during the clock pulse and no timing problem occurs between the latches. However, the delay circuits cause large area and power overheads. Another solution is to use multiple non-overlap delayed pulsed clock signals, as shown in Fig. 4. The delayed pulsed clock signals are generated when a pulsed clock signal goes through delay circuits. Each latch uses a pulsed clock signal which is delayed from the pulsed clock signal used in its next latch. Therefore, each latch updates the data after its next latch updates the data. As a result, each latch has a constant input during its clock pulse and no timing problem occurs between latches. However, this solution also requires many delay circuits. III. PROBLEM OUTLINE The pulsed latch cannot be used in shift registers due tothe timing problem, as shown in Fig. 2(a). The shift register in Fig. consists of several latches and a pulsed clock signal(clk_pulse). The operation waveforms in Fig 2(b).show thetiming problem in the shifter register. The output signal of thefirst latch (Q1) changes correctly because the input signal ofthe first latch (IN) is constant during the clock pulse width. But the second latch has an uncertain output signal(q2) because its input signal (Q1) changes during the clockpulse width. Fig.3. Schematic of Shift register with latches, delay circuits, and a pulsed clock signal. PAPER AVAILABLE ON 165

3 OBJECTIVE The shift register solves the timing problem using multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. In the proposed system we are implementing the application of the shift registers in the design and implementation of the encoder and decoder.the delayed pulsed clock signals are generated when a pulsed clock signal goes through delay circuits. Each latch uses a pulsed clock signal which is delayed from the pulsed clock signal used in its next latch. Therefore, each latch updates the data after its next latch updates the data. As a result, each latch has a constant input during its clock pulse and no timing problem occurs between latches. A master-slave flip-flop using two latches can be replaced by a pulsed latch consistingof a latch and a pulsed clock signal. All pulsed latches share the pulse generation circuit for the pulsed clock signal. As a result, the area and power consumption of the pulsed latch become almost half of those of the master-slave flip-flop. The pulsed latch is an attractive solution for small area and low power consumption. The pulsed latch cannot be used in shift registers due to the timing problem. IV. METHODOLOGY Recently, many methodologies have been introduced for reducing dynamic power for systems-on-chip(socs). These methodologies, however, impose restrictive physical constraints which have schedule impact or which are heavily dependent on logic functions such as clock gating. This article presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. It reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power.real designs have shown approximately a 20 percent reduction in dynamic power using the methodology described below. Dynamic power is consumed across all elements of a chip. The clock network is one of the large consumers of dynamic power. According to a recent IBM study [1], half of dynamic power is dissipated in the clock network. Therefore, reducing power in the clock network can impact the overall dynamic power significantly. Designers already use a variety of techniques to reduce the clock power using smaller clock buffers, reducing the overall wiring capacitance, employing clock gating to reduce the dynamic power [2], and de-cloning to move the clock buffers at higher levels of hierarchy. Even with these techniques, the dynamic power of clock network can be large since registers are used as state elements in the design. In general, a flip-flop is used as the register. A conventional flip-flop is composed of two latches (master and slave) triggered by a clock signal. Flip-flop synchronization with the clock edge is widely used because it is matched with static timing analysis (STA). Timing optimization based on STA is must for SoCs. On the other hand, designers may choose to use a latch for storing the state. A latch is simple and consumes much less power than that of the flip-flop. However, it is difficult to apply static timing analysis with latch design because of the data transparent behavior. Fig. 4. Schematic of Shift register with latches and delayed pulsed clock signals A methodology has been developed which uses latches triggered with pulse clock waveforms. With this methodology, designers can apply static timing analysis and timing optimization to a latch design while reducing the dynamic power of the clock networks. The following describes this pulsed latch design methodology in detail PAPER AVAILABLE ON 166

4 and gives some guidelines as to how designers can apply this methodology in their designs. V.RESULTS Fig 7: RTL Schematic of Top module In the simulations, the shift register with K=4 operates up to Fclk=840MHZ, but in the measurements, the clock frequency was 100 MHz due to the frequency limitation of the experimental equipment. Fig. 18(a) represents a clock signal of 100 MHz, an input signal (IN), two output signals from the first sub shift resister (Q1 and Q2). Fig. 18(b) shows a clock signal of 10MHz, an input signal (IN), eight output signals Fig.5: Simulation result of shift register Fig 8:SHIFT REGISTER in ENCODER & DECODER Fig.6:Simulation result of Non overlapped pulsed Shift register Fig 9: Design Summary Of The 256-Bit Pulsed Latch PAPER AVAILABLE ON 167

5 VI.CONCLUSION This project proposed a low-power and area-efficient shiftregister using pulsed latches. The shift register reduces area andpower consumption by replacing flipflops with pulsed latches.the timing problem between pulsed latches is solved usingmultiple non-overlap delayed pulsed clock signals instead of asingle pulsed clock signal. A small number of the pulsed clocksignals is used by grouping the latches to several sub shifterregisters and using additional temporary storage latches. VII REFERENCES [1] P. Reyes, P. Reviriego, J. A. Maestro, and O. Ruano, New protection techniques against SEUs for moving average filters in a radiation environment, IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp , Aug [2] M. Hatamianet al., Design considerations for gigabit ethernet 1000 base-t twisted pair transceivers, Proc. IEEE Custom Integr. CircuitsConf., pp , [3] H. Yamasaki and T. Shibata, A real-time imagefeature-extraction and vector-generation vlsi employing arrayed-shift-register architecture, IEEE J. Solid-State Circuits, vol. 42, no. 9, pp , Sep [4] H.-S. Kim, J.-H.Yang, S.-H.Park, S.-T.Ryu, and G.-H. Cho, A 10-bit column-driver IC with parasiticinsensitive iterative charge-sharing based capacitorstring interpolation for mobile active-matrix LCDs, IEEE J. Solid-State Circuits, vol. 49, no. 3, pp , Mar [5] S.-H. W. Chiang and S. Kleinfelder, Scaling and design of a 16-megapixel CMOS image sensor for electron microscopy, in Proc. IEEENucl. Sci. Symp. Conf. Record (NSS/MIC), 2009, pp [6] S. Heo, R. Krashinsky, and K. Asanovic, Activitysensitive flip-flop and latch selection for reduced energy, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 15, no. 9, pp , Sep VIII AUTHORS D. Sridhar Working as Head of the Department of ECE, received the M.Tech degree in VLSI System Design from Avanthi Institute of Engineering and Technology, Narsipatnam, B.Tech degree in Electronics and Communication Engineering at Gudlavalleru Engineering College and also Pursuing his Ph.D in Low Power VLSI. He has total Teaching Experience (UG and PG) of 11 years. He has guided and co-guided 8 P.G students.his Research areas included VLSI system Design, Digital signal Processing, Embedded Systems. G.N.P.JYOTHI,,PG scholar Dept of ECE (VLSID), Sri Sunflower College of Engineering and Technology, B.Tech degree in Electronics and Communication Engineering at Shri Vishnu Engineering college For Women, Bhimavaram. PAPER AVAILABLE ON 168