LCLS Machine Protection System Engineering Design Specifications

Transcription

1 LCLS Engineering Specifications Document# Project Management Revision 2 LCLS Machine Protection System Engineering Design Specifications Stephen Norum Author Signature Date Hamid Shoaee System Manager Signature Date David Schultz Electron Beam Systems Manager Signature Date Patrick Krejcik System Physicist Signature Date Darren Marsh Quality Assurance Manager Signature Date Brief Summary: The Machine Protection System (MPS) is an interlock system used to turn off or reduce the rate of the beam in response to fault conditions that may either damage or cause unwanted activation of machine parts. Change History Log Revision Number Revision Date Sections Affected Description of Change 000 November 8, 2006 All Initial version 001 January 5, 2007 All Updated hardware design 002 December 10, 2007 All DRAFT Page 1 of 74

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3 Contents 1 Introduction 7 2 Requirements Protection Timing Configurability Automatic Recovery User Interface and Diagnostics Physical Overview 11 4 Inputs Fault Signals Multi-Bit States Latching Logic Levels Connection to Link Nodes Uploading MPS Algorithm to the Link Processor EPICS Event Generator Chatter Faults Outputs Mitigation Devices Laser Light Mitigation Pockels Cell Injector Mechanical Shutter Beam Containment System Electron Beam Mitigation Single Bunch Beam Dumper EPICS Event Generator Link Communication MPS Link Protocol MPS Link Protocol Message Types Page 3 of 74

4 6.2.1 Link Synchronization Link Node Status Link Node Unlatch Link Node Output Control MPS Link Protocol Timing Link Synchronization and Link Node Status Logic Rate Limiting Automatic Recovery MPS Algorithm Bypassing Device Faults Setting and Changing Device Fault Thresholds Hardware Overview Link Processor Link Node Link Node Digital Ouput Digital Input Response Time Naming PV Names Testing MPS Algorithm Testing Simulate Mode Gigabit Ethernet Device Configuration User Interface 43 Appendices 44 A List of Acronyms 47 B Link Node FGPA Registers 49 B.1 Latched Input Card State Registers B.1.1 Latched State of Input Cards 0 and Page 4 of 74

5 B.1.2 Latched State of Input Cards 2 and B.1.3 Latched State of Input Cards 4 and B.2 Current Input Card State Registers B.2.1 Current State of Input Cards 0 and B.2.2 Current State of Input Cards 2 and B.2.3 Current State of Input Cards 4 and B.3 Output Card Registers B.3.1 Output Card Control B.3.2 Output Card Status B.4 Input Card Channel Debounce Registers B.4.1 Debounce Times of Input Card 0 Channels 0 through B.4.2 Debounce Times of Input Card 0 Channels 8 through B.4.3 Debounce Times of Input Card 1 Channels 0 through B.4.4 Debounce Times of Input Card 1 Channels 8 through B.4.5 Debounce Times of Input Card 2 Channels 0 through B.4.6 Debounce Times of Input Card 2 Channels 8 through B.4.7 Debounce Times of Input Card 3 Channels 0 through B.4.8 Debounce Times of Input Card 3 Channels 8 through B.4.9 Debounce Times of Input Card 4 Channels 0 through B.4.10 Debounce Times of Input Card 4 Channels 8 through B.4.11 Debounce Times of Input Card 5 Channels 0 through B.4.12 Debounce Times of Input Card 5 Channels 8 through B.4.13 Debounce Times of Input Card 6 Channels 0 through B.4.14 Debounce Times of Input Card 6 Channels 8 through B.4.15 Debounce Times of Input Card 7 Channels 0 through B.4.16 Debounce Times of Input Card 7 Channels 8 through B.5 Timestamp and Timing Registers B.5.1 Current Timeslot B.5.2 Current Timestamp Seconds Past Epoch B.5.3 Current Timestamp Nanoseconds and Pulse ID C Uniblitz Shutter Electronic Synchronization System 73 Page 5 of 74

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7 1 Introduction This document discusses the Machine Protection System (MPS) design. The MPS is an interlock system to turn off or reduce the rate of the beam in response to fault conditions that may either damage or cause unwanted activation of machine parts. The three active devices in the LCLS MPS are an abort kicker that is able to kick a single electron bunch, and a Pockels cell and mechanical shutter that block the laser light. The MPS is able to reduce the beam rate below operators requested beam rate only. It cannot raise the beam rate above operators requested beam rate. Separate systems support the MPS to protect other energized devices such as power supplies, magnets, and klystrons. A separate beam containment system uses redundant hardware to ensure that no beam or radiation reaches potentially occupied areas. An interim MPS has been developed for early installation in 2006 to provide an MPS during injector commissioning. System requirements are found in ESD , LCLS Machine Protection System Requirements at Links to many MPS related documents including a list of MPS input devices and rate limiting conditions are kept online at and Page 7 of 74

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9 2 Requirements The primary goal of the MPS is to limit any beam loss near the permanent magnet material of the undulator to a reasonable level. The MPS must also protect other sections of the LCLS from radiation damage from the beam. The MPS must react to a fault before the next beam pulse. The LCLS has a nominal rate of 120 Hz, giving the MPS 8.33 ms to react to a fault. 2.1 Protection 1. The MPS must limit the undulator s radiation dosage to below a specified amount. 2. Beamline components are to be protected from excessive beam exposure to prevent damage to the vacuum system and unnecessary activation. 2.2 Timing 1. Must protect machine in less than 8.33 ms. 2. Mitigation devices can limit beam rate from 120 Hz to 0 Hz including intermediate values 60 Hz, 30 Hz, 10 Hz, 1 Hz as well as the single shot and burst modes. 2.3 Configurability 1. Must be able to change configuration of the logic and beam rate. 2. Add and remove inputs to MPS. 3. Bypass device fault inputs to MPS. 4. Set and change fault thresholds. 5. Understand machine modes. 2.4 Automatic Recovery 1. After a fault is corrected, the MPS will has the ability to raise the beam rate to the rate before the fault. Page 9 of 74

10 2. The MPS is configured for which inputs allow automatic recovery and when it is to be used. 2.5 User Interface and Diagnostics 1. A user interface will provide diagnostics and status information for the MPS including the cause of an MPS trip. 2. When a trip occurs, the MPS uses the timing system to signal devices to stop their circular data buffers for use in postmortem analysis. 2.6 Physical 1. Size: Must fit within a standard instrument rack. 2. Weight: Must be supported by a standard instrument rack. 3. Temperature: 0 C to 50 C. Page 10 of 74

11 3 Overview The MPS determines the maximum allowed beam rate by processing MPS device fault input signals with a rate limiting algorithm. The algorithm, run on a piece of hardware, called the Link Processor, obtains the state of device faults from Link Nodes. Placed periodically along the LCLS beam line, Link Nodes gather the fault status from mulitple MPS devices such as Protection Ion Chambers (PICs) and limit switches. Figure 3.1 shows an overview of the Link Node and Link Processor inputs and outputs. Timing System MPS Link Processor EPICS Gb Ethernet over Cat6 1000BASE-X Switch Gb Ethernet over Fiber MPS Link Node E MPS Link Node E MPS Link Node E MPS Link Node E MPS Link Node E MPS Link Node E Digital I/O over Copper Device Device Device Device Device Device Device Device Device Device Device Mitigation Device Mitigation Device Figure 3.1. Overview of Link Processor and Link Node Signals The Link Processor is composed of an MVME 6100 loaded with an Event Receiver (EVR) for timing system communication. Link Nodes are rackmount SLAC design and feature pluggable input and output cards. The Link Processor and Link Nodes communicate over a dedicated Gigabit Ethernet network to share status and control data and also have Input Output Controller (IOC) functionality to communicate with other devices on the control system network. Page 11 of 74

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13 4 Inputs 4.1 Fault Signals The MPS monitors binary fault signals provided by external devices. Each signal can represent two states. Groups of signals can be combined to represent many states. Devices, such as PICs, that fault when thresholds are exceeded will use hardware external to the Link Nodes to convert faults into binary signals before being read by the Link Nodes. Slow changing devices (like magnets) are able to provide their fault status to the Link Processor through EPICS Multi-Bit States Multiple signals can be combined to provide more states for a device. For example, many moving devices provide two limit switch inputs to the MPS for a single device. The two limit switches, each providing a binary state, are combined by the MPS to create four states. An example of a device with two limit switches providing two signals and multiple states is shown below in Table 4.1. Table 4.1. Example Multi-Bit States for a Moving Device In Limit Switch Out Limit Switch State 0 0 Moving 0 1 Device is Out 1 0 Device is In 1 1 Invalid/Broken Latching To avoid missing a quickly changing fault input, faults can be latched on rising or falling edges in the following ways: 1. Not latched. 2. Latched, cleared on read. Equivalent to Latching Digital Input Module (LDIM). 3. Latched, cleared on EPICS IOC originating reset command. Page 13 of 74

14 4.1.3 Logic Levels The MPS continues the use of the 0/24 V voltage range currently used by many MPS devices. Table 4.2. Logic Levels Voltage (V) Logic State Connection to Link Nodes Device fault signals are grouped geographically and input to the nearest Link Node s terminal block. Periodically placing Link Nodes down the beam line will keep cable lengths short and devices grouped logically. 4.2 Uploading MPS Algorithm to the Link Processor The MPS algorithm is loaded as a part of the Link Processor s IOC executable using the standard IOC booting method. 4.3 EPICS The Link Processor will communicate with other IOCs to gather fault information for slow devices (such as magnets) and provides the user with MPS status and control. The Link Processor and Link use watchdogs that cause the MPS to rate limit the beam to 0 Hz if fresh EPICS data is not available after a specified period of time. 4.4 Event Generator The Link Processor uses an EVR to verify the MPS information it sends the Event Generator (EVG) (see Section 5.5). Page 14 of 74

15 4.5 Chatter Faults Faults that quickly and constantly switch from true to false will be ignored for a specified amount of time. Page 15 of 74

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17 5 Outputs Output signals refer to signals that are sent from the Link Processor and Link Nodes. Figure 5.1 shows an overview of the LCLS beam line and the location of the mitigation devices. Gun BX01 BX02 Linac-X BC1 TD11 BC2 50B1 D10 Dump BX3_ Energy Collimator SBBD (BYKIK) BX3_ Collimators TDUND Undulator (34 sections) BYD Photon Section BXS Energy Spectrometer Dump Dump Main Dump Figure 5.1. Overview of LCLS Beam Line and Mitigation Devices 5.1 Mitigation Devices The Link Processor sends commands to local Link Nodes to control the following mitigation devices: 1. Pockels Cell. 2. Injector mechanical shutter. 3. Single Bunch Beam Dumper. The Single Bunch Beam Dumper (SBBD) s performance is monitored on every pulse. If it fails to meet the MPS requirements, the MPS will use the Pockels cell and injector mechanical shutter to limit beam. In the case that the MPS does not successfully mitigate a fault, the Beam Containment System (BCS) will use a mechanical shutter to block light on the cathode (see Section 5.2.3). 5.2 Laser Light Mitigation The MPS can stop laser light with either the Pockels cell or injector mechanical shutter. The most upstream device is the Pockels cell. The pockels cell blocks light to both the injector cathode and the virtual cathode, whose image is used for feedback. The injector mechanical shutter is further downstream and blocks light to the injector cathode only. Page 17 of 74

18 Injector Mirror Injector Cathode Injector Mechanical Shutter Splitter Virtual Cathode and Joule Meter BCS Mechanical Shutter Compressor and Trippler System (IR to UV) Pockels Cell Figure 5.2. Path of Laser Light and Mitigation Devices Pockels Cell The Pockels cell gates the injector laser. It gates beam from 120 Hz to 10 Hz. Lower rates are gated by the injector mechanical shutter. To ensure the virtual cathode has sufficient data for feedback, the Pockels cell does not rate limit the beam below 10 Hz Injector Mechanical Shutter The injector mechanical shutter gates the injector laser. It is used to gate a 10 Hz or less frequent beam to 1 Hz or 0 Hz. The injector mechanical shutter is also used to gate a single pulse when the machine is running in Single Shot mode. To avoid wear on the shutter, the shutter only gates beam at a maximum rate of 1 Hz. The shutter is configured to be normally closed. The shutter controller uses a TTL gate input signal provided by the MPS as shown in Table Beam Containment System The injector mechanical shutter control signal is checked against a shutter readback signal provided by the shutter s Electronic Synchronization System (ESS) (See Appendix C). A shutter fault occurs when the shutter control does not match the shutter s readback signal from the ESS. See Table 5.2. Page 18 of 74

19 Table 5.1. Injector Mechanical Shutter Control Signals Beam Rate, f b (Hz) Output (TTL) f b > 1 High f b = 1 1 Hz trigger with < 0.1 s high-time f b = 0 Low Table 5.2. Shutter Fault Logic Shutter Open Shutter Readback Shutter OK The MPS provides a dry contact for the BCS to search. The contact is closed while the shutter is operating correctly and open when the shutter has failed as shown in Figure 5.3. When the relay opens, the BCS blocks light on both the injector and virtual cathode by closing its own mechanical shutter. Note that a shutter control fault is a fault of the MPS itself and is not a BCS fault. Shutter Open Shutter Readback XNOR R e l a y + Shutter OK Shutter OK BCS Figure 5.3. MPS Shutter Fault Output to BCS 5.3 Electron Beam Mitigation Single Bunch Beam Dumper The SBBD is used to kick beam in the Linac To Undulator (LTU) section. It can rate limit the beam from 120 Hz to 0 Hz while the linac is kept at a constant rate. The SBBD is triggered at 120 Hz. The trigger is moved from standby time to beam time in order to abort the beam. The amplitude of the SBBD s current is monitored on every pulse. If the amplitude does not fall within a specified range at trigger time, the SBBD has failed Page 19 of 74

20 and the MPS uses the Pockels cell and mechanical shutter to continue rate limiting at the correct rate. The MPS continues to trigger the SBBD after an SBBD fault. If the SBBD begins to operate correctly, the MPS returns to using the SBBD as the mitigation device. The SBBD trigger is created following the logic shown in Figure 5.4. The user may request to fire the SBBD at beam time (abort) or after beam time (standby). If the MPS chooses to abort the beam, the Link Processor does not transmit MPS Permit signal to the local Link Node. The inverse of this signal is ANDed with an always present Abort trigger generated by an EVR. This signal is ORed with the user request to create a trigger for the SBBD. The SBBD ignore standby triggers that follow an abort triggers. Table 5.3 details which trigger is used by the SBBD. Standby Trigger (EVR) AND MPS Permit (DM) User's Request (IOC) AND NOT OR Trigger to SBBD Abort Trigger (EVR) AND Figure 5.4. SBBD Control Logic Table 5.3. Trigger Used By SBBD MPS Permit User s Request Trigger Used By SBBD 0 0 Abort 0 1 Abort 1 0 Abort 1 1 Standby 5.4 EPICS MPS device fault signal status and configuration checks will be available through EPICS. The Link Processor provides Process Variables (PVs) with information acquired from the MPS hardware including Link Nodes and itself. Page 20 of 74

21 5.5 Event Generator The MPS provides eight bits of information to the EVG as recorded in Figure 5.5 and Table Beam Destination Rate Limit Beam Permit Figure 5.5. MPS Data Sent to EVG Page 21 of 74

22 Table 5.4. Layout of MPS Data Given to EVG Purpose State Value Description of State Beam Permit Rate Limit Beam Destination Beam Not Permitted Beam Permitted Communication Failure Hz Hz Hz Hz Hz Hz Undefined No Beam Destination Specified Gun Spectrometer Dump Straight Ahead Beam Dump (SAB) Insertable Tune Up Dump (TD11) Insertable Tune Up Dump (TD21) D10 Dump Single Bunch Beam Dumper (SBBD) Insertable Tune Up Dump (TDUND) Main Dump Experimental Huts Page 22 of 74

23 6 Link Communication Link Nodes and the Link Processor communicate using the protocols shown in Table 6.1. The link, network, and transport layers encapsulate the custom application layer protocol, MPS Link Protocol (MLP). Table 6.1. MPS 2007 Link Communication Protocols Layer Protocol Link Gigabit Ethernet Network IPv4 Transport UDP Application MLP 6.1 MPS Link Protocol MLP defines a set of header bits and a data section. The data section has a maximum payload of 1466 bytes to ensure the entire message fits within a single standard Ethernet frame. An MLP frame has the following structure and is shown graphically in Figure 6.1. Protocol Version (1 byte) The current protocol version is placed in this field. A zero rate fault is created when an unexpected protocol version is received. Message Type (1 byte) This field is used to inform the receiver of the data format of the following data field. Data (0 to 1466 bytes) The data field has a maximum payload of 1466 bytes to ensure the MLP datagram is not split into multiple Ethernet frames. 6.2 MPS Link Protocol Message Types The MLP defines the following message types. Message sizes do not include the Ethernet, IPv4, UDP, or MLP headers Link Synchronization The Link Processor sends this broadcast message to all Link Nodes on update of the timestamp from the timing system (360 Hz). The synchronization message is also used as Page 23 of 74

24 72 to to to Ethernet IPv4 UDP MPS Link Protocol CRC to 1466 Protocol Version Message Type Data Figure 6.1. MPS Link Protocol Datagram (sizes in bytes) Page 24 of 74

25 a request for Link Node status. Details Structure Message Type Value 0x51 Broadcast Type Broadcast, Link Processor to Link Nodes Message Size 11 bytes Timestamp Seconds Past Epoch (4 bytes) The current timestamp s seconds past epoch field. Timestamp Nanoseconds and Pulse ID (4 bytes) The current timestamp s nanoseconds past second and the Pulse ID. Timeslot (1 byte) The current timeslot. Data For EVG (2 bytes) Synchronization data for the EVG. Data includes beam rates for each destination and the beam s current destination Link Node Status Upon receipt of a Link Synchronization message (Section 6.2.1), Link Nodes sends their current status of their input bits directly to the Link Processor. Details Structure Message Type Value 0xAC Broadcast Type Unicast, Link Node to Link Processor Message Size 26 bytes Timestamp Seconds Past Epoch (4 bytes) The last received timestamp s seconds past epoch field. Timestamp Nanoseconds and Pulse ID (4 bytes) The last received timestamp s nanoseconds past second and the Pulse ID. Timeslot (1 byte) The last received timeslot. Link Node ID (1 byte) The Link Node s ID number. Page 25 of 74

26 Input Card Status (12 bytes) The latched state of all 96 Link Node inputs. Unused inputs are included in this field. Output Card Status (2 bytes) The current state of the Link Node s 8 outputs, 4 trigger inputs, and 4 trigger outputs. Link Node Status (2 bytes) The latched state of internal Link Node errors Link Node Unlatch After the Link Processor has handled the device status information from a Link Node Status message (Section 6.2.2), it sends a Link Node Unlatch message back to the Link Node. This message informs Link Nodes of which faults the Link Processor has received and can therefore be unlatched. This message mirrors the Link Node Status message. After processing a Link Node Status message, the Link Processor can change the Message Type value of the message to 0x71 and send the message back to the Link Node as a Link Node Unlatch message. Details Structure Message Type Value 0x71 Broadcast Type Unicast, Link Processor to Link Node Message Size 26 bytes Unused (9 bytes) Unused. Link Node ID (1 byte) The Link Node s ID number. Device Status (12 bytes) The device states from the last received Link Node Status message. Unused (2 bytes) Unused. Link Node Status (2 bytes) The internal Link Node error states from the last received Link Node Status message Link Node Output Control The Link Processor sends this control message as a broadcast to all Link Nodes. This message supports only 64 Link Nodes. If more Link Nodes need to be addressed, multiple Page 26 of 74

27 Link Node Output Control message can be sent, or this message can be sent as unicast. Details Structure Message Type Value 0x61 Broadcast Type Broadcast, Link Processor to Link Nodes Message Size 256 bytes Output States and Triggers (256 bytes) A 64 element array with the element format: 1 byte Link Node ID. 2 byte Output states. Two bits per output. See Table byte Trigger outputs. One bit per trigger using the four least significant bits of the byte to control the four triggers. Table 6.2. Output State Value Effects Value Effect On Output 0x00 No change 0x01 Set output state to 0 0x10 Set output state to 1 0x11 No change 6.3 MPS Link Protocol Timing Synchronization of the Link Processor and Link Nodes occurs at 360 Hz. Latency of messages can be calculated with the following values: Therefore, the maximum fiber propagation time, t pmax, is t pmax = l max n c 1.5 km = c = µs Page 27 of 74

28 Table 6.3. Symbol Descriptions and Values Description Symbol Value Bit Rate R Gbit/s Max Datagram Size d max 1526 bytes Encoding Overhead E 10/8 Fiber Index of Refraction at 1310 nm n Maximum Fiber Length in MPS l max 1.5 km Number of Link Nodes N LN 30 the time to send out a full datagram, t f d, is t f d = d max E R 1526 B 10/8 = Gbit/s = µs and the time to serially receive full datagrams from all nodes all from the maximum distance, t worst, is t worst = N LN ( tpmax + t f d ) = 30 ( µs µs) = 30 ( µs) = µs Link Synchronization and Link Node Status Figure 6.2 shows the timing of transmitting Link Synchronization, Link Node Output Control, and Link Node Status messages during an 8.3 ms period. Time to send the Link Node Status messages from the Link Nodes to the Link Processor assumes t worst. Page 28 of 74

29 2.77 ms Link Synchronization Link Node Output Control From Link Processor 1 From Link Nodes t (ms) 0.7 ms Link Node Status Figure 6.2. Timing Diagram of Link Communication During a 120 Hz Pulse Page 29 of 74

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31 7 Logic 7.1 Rate Limiting Depending on a fault s severity, the MPS may limit beam rate rather than abort all pulses. The MPS can rate limit the beam from 120 Hz to 0 Hz. An example of an MPS rate limiting decision is the limiting of the integrated radiation dosage in the undulator. If the undulator exceeds a cumulative dosage threshold over one second, the MPS may decide to lower the beam rate to mitigate the fault. Cumulative Radiation Dose 120 Hz Beam... No Beam Hz Beam 10 Hz Beam Loss Threshold Pulse Time (s) Figure 7.1. Example of Integrated Radiation Dosage in the Undulator Figure 7.1 shows an example of integrated radiation dose in the undulator. The MPS calculates the integrated radiation dosage as the cumulative beam loss per second. The beam rate begins at 120 Hz. The loss threshold is exceeded by the 20 th pulse in the first second. The MPS must limit the beam rate to less than 20 pulses/1 s = 20 Hz. The MPS chooses to limit the beam rate to 10 Hz, resets the cumulated beam loss, and waits 1 pulse at 10 Hz = 0.1 s to begin the 10 Hz integration. The last pulse at 120 Hz is also the first pulse at 10 Hz. If the machine continues to lose a similar amount of beam per pulse, the cumulated beam loss will only reach 10 Hz/20 Hz = 50% of the loss threshold. 7.2 Automatic Recovery After certain rate limiting faults clear, the MPS has the option to restore the beam rate to an operator s current requested beam rate. Each fault is configured to either support automatic recovery or require an operator to manually reset the beam rate after the fault clears. Page 31 of 74

32 7.3 MPS Algorithm An MPS algorithm file is compiled into an the Link Processor s executable. The Link Processor uses the logic to process fault inputs from the Link Nodes and EPICS to limit the beam s rate when necessary. Mitigation devices are monitored by the MPS. If a mitigation device is not performing to specifications, the MPS will limit beam with a different mitigation device. 7.4 Bypassing Device Faults Device faults can be bypassed via an EPICS display if authorized with a correct name and password. After authorization, the operator can bypass a fault by selecting a fault, choosing its bypass state, and supplying an expiration date or a bypass duration. For example, an operator can choose to bypass a flow switch for one day by selecting the flow switch input, selecting its OK state, and giving a bypass duration of 24 hours. The operator could also specify the expiration duration of 24 hours by selecting an expiration date of tomorrow. 7.5 Setting and Changing Device Fault Thresholds Fault thresholds are changed by the MPS device s IOC. The IOCs use Channel Access (CA) security to ensure that users are authorized with a name and password before changes are made. Page 32 of 74

33 8 Hardware Overview The MPS a client/server design. The client, the Link Processor, requests data from servers, the Link Nodes, in order to determine the maximum allowed beam rate. The Link Processor and Link Nodes communicate over Gigabit Ethernet. 8.1 Link Processor The Link Processor is the core of the MPS. It a specialized EPICS IOC running on an MVME 6100 that gathers fault information from Link Nodes, determines the maximum allowable beam rate, and transmits mitigation control signals to Link Nodes. The Link Processor interfaces with EPICS, the timing system through a mounted EVR, and Link Nodes through Gigabit Ethernet. 8.2 Link Node Link Nodes gather inputs from MPS fault devices using digital input cards (see Section 9.2). They package these inputs into an Ethernet frame and send the data to the Link Processor. After processing of the inputs, the Link Processor responds to the Link Nodes with control commands to either permit or deny beam. The Link Nodes control mitigation devices using digital output cards (see Section 9.1). See Chapter 9 for Link Node details. Page 33 of 74

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35 9 Link Node Link Nodes gather inputs from MPS fault devices using digital input cards (see Section 9.2). They package these inputs into an Ethernet frame and send the data to the Link Processor. After processing of the inputs, the Link Processor responds to the Link Nodes with control commands to either permit or deny beam. The Link Nodes control mitigation devices using digital output cards (see Section 9.1). Figure 9.1 shows the Link Node circuit board layout. Figure 9.1. Circuit Board Layout of the Link Node Hardware Page 35 of 74

36 9.1 Digital Ouput Link Nodes use digital output cards to send signals to mitigation devices, the EVG, and other devices. The cards provide eight output channels of 0/24 V signals for logic levels 0 and 1 respectively. The cards also feature four trigger inputs and four trigger outputs. The digital output card s circuit board layout is shown in Figure 9.2. Figure 9.2. Circuit Board Layout of Digital Output Card 9.2 Digital Input Link Nodes use digital input cards to read signals from MPS hardware. See Section for more information on logic levels. The input card has sixteen input channels. The digital input card s circuit board layout is shown in Figure Response Time Debounce time is individually programmable from 10 µs to 5 s (inclusive) in eight steps. Page 36 of 74

37 Figure 9.3. Circuit Board Layout of Digital Input Card Table 9.1. Selectable Debounce Times Mode Debounce Time 0 10 µs µs 2 1 ms 3 10 ms ms ms 6 1 s 7 5 s Page 37 of 74

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39 10 Naming The MPS follows the LCLS naming format for its PV names and internal names used by the mpl! (mpl!) PV Names Page 39 of 74

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41 11 Testing 11.1 MPS Algorithm Testing Test software is used to check the algorithm s runtime correctness testing to ensure that the algorithm was correctly implemented. The algorithm s syntax is checked at compile time Simulate Mode The MPS can be put into a simulate mode where a combination of inputs and outputs can be real or simulated. Real signals reflect actual hardware signals while simulated values can be read from and written to with software. When in simulate mode, operators can toggle input bits and view the results of the MPS algorithm from an EPICS interface Gigabit Ethernet Link Nodes have an echo function to return a test message sent from the Link Processor Device Configuration On request, the Link Processor and Link Nodes report their current configurations through EPICS. Page 41 of 74

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43 12 User Interface The MPS will use LCLS standard EPICS displays for control and monitoring of MPS signals. CA security will be used to authorize MPS threshold and bypass changes with a user name and password. The displays will provide the current state of MPS fault inputs along with an associated string and severity level. For example, a multi-bit limit switch input where both an in and out limit switch are not pressed may map to a string Moving colored yellow to reflect a moderate fault severity. The interface will provide displays with rate limiting information including the maximum allowed beam rate and enabled mitigation devices. The configuration of MPS devices will also be available from the displays. Page 43 of 74

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45 Appendices Page 45 of 74

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47 A List of Acronyms BCS Beam Containment System CA Channel Access ESS Electronic Synchronization System see Appendix C EVG Event Generator EVR Event Receiver IOC Input Output Controller LDIM Latching Digital Input Module LTU Linac To Undulator MLP MPS Link Protocol MPS Machine Protection System PIC Protection Ion Chamber PV Process Variable SBBD Single Bunch Beam Dumper Page 47 of 74

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49 B Link Node FGPA Registers FPGA registers are provided to the ColdFire processor, USB interface, and fiber interface to read and set FPGA states and settings. All registers are big-endian. B.1 Latched Input Card State Registers Table B.1. Input Card Status Register Values Value Input Channel State 0 Input is low or unplugged 1 Input is high B.1.1 Latched State of Input Cards 0 and 1 Address 0x The latched state of input cards 0 and 1. Inputs are latched to the fault state if their signal is unplugged or stays faulted for the input specific debounce time Input Card 1 Input Card 0 Bit Description Default Value CPU Link 31:16 Latched state of Input Card 1. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Latched state of Input Card 0. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R B.1.2 Latched State of Input Cards 2 and 3 Address 0x Page 49 of 74

50 The latched state of input cards 2 and 3. Inputs are latched to the fault state if their signal is unplugged or stays faulted for the input specific debounce time Input Card 3 Input Card 2 Bit Description Default Value CPU Link 31:16 Latched state of Input Card 3. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Latched state of Input Card 2. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R B.1.3 Latched State of Input Cards 4 and 5 Address 0x The latched state of input cards 4 and 5. Inputs are latched to the fault state if their signal is unplugged or stays faulted for the input specific debounce time Input Card 5 Input Card 4 Bit Description Default Value CPU Link 31:16 Latched state of Input Card 5. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Latched state of Input Card 4. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R Page 50 of 74

51 B.2 Current Input Card State Registers Table B.2. Input Card Status Register Values Value Input Channel State 0 Input is low or unplugged 1 Input is high B.2.1 Current State of Input Cards 0 and 1 Address 0x The current state of input cards 0 and 1. States follow signal levels after the signals are held constant for the input specific debounce time Input Card 1 Input Card 0 Bit Description Default Value CPU Link 31:16 Current state of Input Card 1. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Current state of Input Card 0. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R B.2.2 Current State of Input Cards 2 and 3 Address 0x The current state of input cards 2 and 3. States follow signal levels after the signals are held constant for the input specific debounce time Input Card 3 Input Card 2 Page 51 of 74

52 Bit Description Default Value CPU Link 31:16 Current state of Input Card 3. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Current state of Input Card 2. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R B.2.3 Current State of Input Cards 4 and 5 Address 0x The current state of input cards 4 and 5. States follow signal levels after the signals are held constant for the input specific debounce time Input Card 5 Input Card 4 Bit Description Default Value CPU Link 31:16 Current state of Input Card 5. Bit 16 through 31 map to the card inputs 0 through 15 respectively. 15:0 Current state of Input Card 4. Bit 0 through 15 map to the card inputs 0 through 15 respectively. 0x0000 R R 0x0000 R R Page 52 of 74

53 B.3 Output Card Registers B.3.1 Output Card Control Address 0x The output card has eight digital output channels and four trigger outputs. Each output is controlled by two bits in this register. See Table B.3 for a description of how these bit pairs map to output states. Table B.3. Digital Output Control Values Value Digital Output State 00 Set low 01 Set high 10 Undefined 11 Do not change Table B.4. Trigger Control Values Value Trigger Control 0 No output 1 Trigger TC3 TC2 TC1 TC0 OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 Bit Description Default Value CPU Link 31:20 Unused 19 Trigger 3 control 0 R R/W 18 Trigger 2 control 0 R R/W 17 Trigger 1 control 0 R R/W 16 Trigger 0 control 0 R R/W 15:14 Output channel 7 control 00 R R/W 13:12 Output channel 6 control 00 R R/W 11:10 Output channel 5 control 00 R R/W 9:8 Output channel 4 control 00 R R/W 7:6 Output channel 3 control 00 R R/W 5:4 Output channel 2 control 00 R R/W 3:2 Output channel 1 control 00 R R/W 1:0 Output channel 0 control 00 R R/W Page 53 of 74

54 B.3.2 Output Card Status Address 0x The output card has eight output channels. The output state of each channel is represented by a bit in this register. See Table B.5 for a description of register values. Table B.5. Output Card Status Register Values Value Output Channel State 0 Output is low 1 Output is high OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 Bit Description CPU Link 31:8 Unused 7 Current output state of channel 7 R R 6 Current output state of channel 6 R R 5 Current output state of channel 5 R R 4 Current output state of channel 4 R R 3 Current output state of channel 3 R R 2 Current output state of channel 2 R R 1 Current output state of channel 1 R R 0 Current output state of channel 0 R R Page 54 of 74

55 B.4 Input Card Channel Debounce Registers Table B.6. Debounce Register Values Mode Register Value Debounce Time µs µs ms ms ms ms s s B.4.1 Debounce Times of Input Card 0 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 0. See Table B.6 for mapping of register values to debounce times D007 D006 D005 D004 D003 D002 D001 D000 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 0 Channel R/W R/W 20:18 Debounce time of Input Card 0 Channel R/W R/W 17:15 Debounce time of Input Card 0 Channel R/W R/W 14:12 Debounce time of Input Card 0 Channel R/W R/W 11:9 Debounce time of Input Card 0 Channel R/W R/W 8:6 Debounce time of Input Card 0 Channel R/W R/W 5:3 Debounce time of Input Card 0 Channel R/W R/W 2:0 Debounce time of Input Card 0 Channel R/W R/W Page 55 of 74

56 B.4.2 Debounce Times of Input Card 0 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 0. See Table B.6 for mapping of register values to debounce times D015 D014 D013 D012 D011 D010 D009 D008 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 0 Channel R/W R/W 20:18 Debounce time of Input Card 0 Channel R/W R/W 17:15 Debounce time of Input Card 0 Channel R/W R/W 14:12 Debounce time of Input Card 0 Channel R/W R/W 11:9 Debounce time of Input Card 0 Channel R/W R/W 8:6 Debounce time of Input Card 0 Channel R/W R/W 5:3 Debounce time of Input Card 0 Channel R/W R/W 2:0 Debounce time of Input Card 0 Channel R/W R/W Page 56 of 74

57 B.4.3 Debounce Times of Input Card 1 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 1. See Table B.6 for mapping of register values to debounce times D107 D106 D105 D104 D103 D102 D101 D100 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 1 Channel R/W R/W 20:18 Debounce time of Input Card 1 Channel R/W R/W 17:15 Debounce time of Input Card 1 Channel R/W R/W 14:12 Debounce time of Input Card 1 Channel R/W R/W 11:9 Debounce time of Input Card 1 Channel R/W R/W 8:6 Debounce time of Input Card 1 Channel R/W R/W 5:3 Debounce time of Input Card 1 Channel R/W R/W 2:0 Debounce time of Input Card 1 Channel R/W R/W Page 57 of 74

58 B.4.4 Debounce Times of Input Card 1 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 1. See Table B.6 for mapping of register values to debounce times D115 D114 D113 D112 D111 D110 D109 D108 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 1 Channel R/W R/W 20:18 Debounce time of Input Card 1 Channel R/W R/W 17:15 Debounce time of Input Card 1 Channel R/W R/W 14:12 Debounce time of Input Card 1 Channel R/W R/W 11:9 Debounce time of Input Card 1 Channel R/W R/W 8:6 Debounce time of Input Card 1 Channel R/W R/W 5:3 Debounce time of Input Card 1 Channel R/W R/W 2:0 Debounce time of Input Card 1 Channel R/W R/W Page 58 of 74

59 B.4.5 Debounce Times of Input Card 2 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 2. See Table B.6 for mapping of register values to debounce times D207 D206 D205 D204 D203 D202 D201 D200 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 2 Channel R/W R/W 20:18 Debounce time of Input Card 2 Channel R/W R/W 17:15 Debounce time of Input Card 2 Channel R/W R/W 14:12 Debounce time of Input Card 2 Channel R/W R/W 11:9 Debounce time of Input Card 2 Channel R/W R/W 8:6 Debounce time of Input Card 2 Channel R/W R/W 5:3 Debounce time of Input Card 2 Channel R/W R/W 2:0 Debounce time of Input Card 2 Channel R/W R/W Page 59 of 74

60 B.4.6 Debounce Times of Input Card 2 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 2. See Table B.6 for mapping of register values to debounce times D215 D214 D213 D212 D211 D210 D209 D208 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 2 Channel R/W R/W 20:18 Debounce time of Input Card 2 Channel R/W R/W 17:15 Debounce time of Input Card 2 Channel R/W R/W 14:12 Debounce time of Input Card 2 Channel R/W R/W 11:9 Debounce time of Input Card 2 Channel R/W R/W 8:6 Debounce time of Input Card 2 Channel R/W R/W 5:3 Debounce time of Input Card 2 Channel R/W R/W 2:0 Debounce time of Input Card 2 Channel R/W R/W Page 60 of 74

61 B.4.7 Debounce Times of Input Card 3 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 3. See Table B.6 for mapping of register values to debounce times D307 D306 D305 D304 D303 D302 D301 D300 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 3 Channel R/W R/W 20:18 Debounce time of Input Card 3 Channel R/W R/W 17:15 Debounce time of Input Card 3 Channel R/W R/W 14:12 Debounce time of Input Card 3 Channel R/W R/W 11:9 Debounce time of Input Card 3 Channel R/W R/W 8:6 Debounce time of Input Card 3 Channel R/W R/W 5:3 Debounce time of Input Card 3 Channel R/W R/W 2:0 Debounce time of Input Card 3 Channel R/W R/W Page 61 of 74

62 B.4.8 Debounce Times of Input Card 3 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 3. See Table B.6 for mapping of register values to debounce times D315 D314 D313 D312 D311 D310 D309 D308 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 3 Channel R/W R/W 20:18 Debounce time of Input Card 3 Channel R/W R/W 17:15 Debounce time of Input Card 3 Channel R/W R/W 14:12 Debounce time of Input Card 3 Channel R/W R/W 11:9 Debounce time of Input Card 3 Channel R/W R/W 8:6 Debounce time of Input Card 3 Channel R/W R/W 5:3 Debounce time of Input Card 3 Channel R/W R/W 2:0 Debounce time of Input Card 3 Channel R/W R/W Page 62 of 74

63 B.4.9 Debounce Times of Input Card 4 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 4. See Table B.6 for mapping of register values to debounce times D407 D406 D405 D404 D403 D402 D401 D400 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 4 Channel R/W R/W 20:18 Debounce time of Input Card 4 Channel R/W R/W 17:15 Debounce time of Input Card 4 Channel R/W R/W 14:12 Debounce time of Input Card 4 Channel R/W R/W 11:9 Debounce time of Input Card 4 Channel R/W R/W 8:6 Debounce time of Input Card 4 Channel R/W R/W 5:3 Debounce time of Input Card 4 Channel R/W R/W 2:0 Debounce time of Input Card 4 Channel R/W R/W Page 63 of 74

64 B.4.10 Debounce Times of Input Card 4 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 4. See Table B.6 for mapping of register values to debounce times D415 D414 D413 D412 D411 D410 D409 D408 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 4 Channel R/W R/W 20:18 Debounce time of Input Card 4 Channel R/W R/W 17:15 Debounce time of Input Card 4 Channel R/W R/W 14:12 Debounce time of Input Card 4 Channel R/W R/W 11:9 Debounce time of Input Card 4 Channel R/W R/W 8:6 Debounce time of Input Card 4 Channel R/W R/W 5:3 Debounce time of Input Card 4 Channel R/W R/W 2:0 Debounce time of Input Card 4 Channel R/W R/W Page 64 of 74

65 B.4.11 Debounce Times of Input Card 5 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 5. See Table B.6 for mapping of register values to debounce times D507 D506 D505 D504 D503 D502 D501 D500 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 5 Channel R/W R/W 20:18 Debounce time of Input Card 5 Channel R/W R/W 17:15 Debounce time of Input Card 5 Channel R/W R/W 14:12 Debounce time of Input Card 5 Channel R/W R/W 11:9 Debounce time of Input Card 5 Channel R/W R/W 8:6 Debounce time of Input Card 5 Channel R/W R/W 5:3 Debounce time of Input Card 5 Channel R/W R/W 2:0 Debounce time of Input Card 5 Channel R/W R/W Page 65 of 74

66 B.4.12 Debounce Times of Input Card 5 Channels 8 through 15 Address 0x This register controls the desired debounce times for channels 8 through 15 of input card 5. See Table B.6 for mapping of register values to debounce times D515 D514 D513 D512 D511 D510 D509 D508 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 5 Channel R/W R/W 20:18 Debounce time of Input Card 5 Channel R/W R/W 17:15 Debounce time of Input Card 5 Channel R/W R/W 14:12 Debounce time of Input Card 5 Channel R/W R/W 11:9 Debounce time of Input Card 5 Channel R/W R/W 8:6 Debounce time of Input Card 5 Channel R/W R/W 5:3 Debounce time of Input Card 5 Channel R/W R/W 2:0 Debounce time of Input Card 5 Channel R/W R/W Page 66 of 74

67 B.4.13 Debounce Times of Input Card 6 Channels 0 through 7 Address 0x This register controls the desired debounce times for channels 0 through 7 of input card 6. See Table B.6 for mapping of register values to debounce times D607 D606 D605 D604 D603 D602 D601 D600 Bit Description Default Value CPU Link 31:24 Unused 23:21 Debounce time of Input Card 6 Channel R/W R/W 20:18 Debounce time of Input Card 6 Channel R/W R/W 17:15 Debounce time of Input Card 6 Channel R/W R/W 14:12 Debounce time of Input Card 6 Channel R/W R/W 11:9 Debounce time of Input Card 6 Channel R/W R/W 8:6 Debounce time of Input Card 6 Channel R/W R/W 5:3 Debounce time of Input Card 6 Channel R/W R/W 2:0 Debounce time of Input Card 6 Channel R/W R/W Page 67 of 74