EE241 - Spring 2001 Advanced Digital Integrated Circuits. References

Transcription

1 EE241 - Spring 2001 Advanced Digital Integrated Circuits Lecture 28 References Rabaey, Digital Integrated Circuits and EE241 (1998) notes Chapter 25, ing of High-Performance Processors by D.K. Bhavsar 1

2 Project Reports Title of the project/ your names and addresses Abstract (100 words) Motivation Problem statement Possible solutions from literature (from midterm report) Proposed comparison/solution. Discuss why did you select this particular one. Conditions/assumptions of your design Analysis: Does it work? Analytical analysis, simulation results. Conclusion. What is this approach good for? What else could be done? References Due on May 10, at 10am (on the web) Project Presentations PowerPoint presentations due May 10, at 10am on the web. From 1-5pm in BWRC front classroom. Time per group: 2mins + 5mins x #people + 5mins for discussion #slides < #minutes for presentation Final exam is in 3 Evans Hall on Wednesday, March 16, 5-8pm. 2

3 Diagnostic test Classification» used in chip/board debugging» defect localization go/no go or production test» Used in chip production Parametric test»x ε [v,i] versus x ε [0,1]» check parameters such as NM, V t,t p, T Chip Debugging Design errors or fabrication defects? Micro-probing the die (1-01.pF) E-beam Single-die repair (FIB) 3

4 ing is Expensive VLSI testers cost $1-5M Volume manufacturing requires large number of testers, maintenance er time costs are in /sec cost contributes 20-30% to total chip cost Types of ing Step Design Prototype Manufacture Shipping System Integration Service Error Source Design flaws Design flaws Prototype flaws Physical defects Man. test, transport Same Stress, Age Type Design ver. Functional test Manuf. test Functional test Diagnosis 4

5 Fault Models Most Popular - Stuck - at model 0 sa0 (output) 1 sa1 (input) Covers almost all (other) occurring faults, such as opens and shorts. x1 x2 α β γ Z x3 α, γ : x1 sa1 β : x1 sa0 or x2 sa0 γ : Z sa1 Problem with stuck-at model: CMOS open fault x1 x2 x1 Z x2 Sequential effect Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive! 5

6 Problem with stuck-at model: CMOS short fault 0 C D 0 A B Causes short circuit between Vdd and GND for A=C=0, B=1 0 1 A B C D Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration Design for ability N inputs Combinational Logic K outputs N inputs Combinational Logic K outputs Module Module M state regs (a) Combinational function (b) Sequential engine 2 N patterns 2 N+M patterns Exhaustive test is impossible or unpractical 6

7 Problem: Controllability/Observability Combinational Circuits: controllable and observable - relatively easy to determine test patterns Sequential Circuits: State! Turn into combinational circuits or use self-test Memory: requires complex patterns Use self-test Approaches Ad-hoc testing Scan-based Self- Problem is getting harder» increasing complexity and heterogeneous combination of modules in system-on-achip.» Advanced packaging and assembly techniques extend problem to the board level 7

8 Generating and Validating -Vectors Automatic test-pattern generation (ATPG)» for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output» majority of available tools: combinational networks only» sequential ATPG available from academic research Fault simulation» determines test coverage of proposed test-vector set» simulates correct network in parallel with faulty networks Both require adequate models of faults in CMOS integrated circuits Scan-based ScanIn ScanOut In Register Combinational Logic A Register Combinational Logic B Out 8

9 Polarity-Hold SRL (Shift-Register Latch) System Data System Clock Scan Data Shift A Clock D C SI A L1 Q Q SO Shift B Clock B L2 SO Introduced at IBM and set as company policy (LSSD) Scan-Path Flip-Flop OUT SCAN PHI2 PHI1 SCANIN SCANOUT IN LOAD KEEP 9

10 Scan Flip-Flop in AMD K-6 Scan-based Operation In 0 In 1 In 2 In 3 ScanIn ScanOut Latch Latch Latch Latch Out 0 Out 1 Out 2 Out 3 φ 1 φ 2 N cycles scan-in 1 cycle evaluation N cycles scan-out 10

11 Scan Self-test Stimulus Generator (Sub)-Circuit Under Response Analyzer Controller Rapidly becoming more important with increasing chip-complexity and larger modules 11

12 Linear-Feedback Shift Register (LFSR) R R R S 0 S 1 S Pseudo-Random Pattern Generator Signature Analysis In Counter R Counts transitions on single-bit stream Compression in time 12

13 Built-In Self- Memory Self- data-in FSM Memory Under data-out Signature Analysis address & R/W control Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s 13

14 Boundary Scan (JTAG) Printed-circuit board Logic Packaged IC Scan-in Scan-out si so scan path normal interconnect Bonding Pad Board testing becomes as problematic as chip testing ing on-chip Logic 14

15 ing Mixed Analog-Digital ICs 15