Menu. 68HC12 Timer Block Diagram EEL 3744 EEL Input Capture (IC)

Transcription

1 Intro to Input Capture Input Capture Programming Example >Measure the Elapsed time between Events Another Input Capture Programming Example >Detect a Signal Pattern XMEGA Input Capture Menu Look into my... See docs/examples on web-site: doc8331 (Sec 14-15), doc8385 (Sec 16-17), doc8045 IC3.asm, IC5_Det.asm 1 68HC12 Timer Block Diagram Tech: Fig

2 68HC12 Main Timer System S&HE: Fig 10.1 shown and HC12 TIOS: Timer Input Capture/Output Compare Select Register & DDRT TIOS - Timer Input Capture/Output Compare Select Register $0080 RESET >0 = IC; 1= OC IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS DDRT - Data Direction Register for Port T >0 = Input; 1 = Output $00AF DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 DDRT RESET

3 $0084 RESET $0085 RESET 68HC12 TCNT and TSCR Bit Bit 8 TCNT High Bit Bit 0 TCNT Low $0086 RESET TEN (Timer Enable) in TSCR: >0 = disable >1 = enable TEN TSWAI TSBCK TFFCA TSCR Block Diagram of Input Capture 68HC12 Input Capture Block Diagram ICx Interrupt Line ICx Flag S&HE: Fig 10.4 ICx Interrupt Enable Free-running Counter TCx Register In TCTL3 or TCTL4 EDGxB EDGxA Edge Control 00 Disabled 01 Rising Edge 10 Falling Edge 11 Any Edge Pin Tech: Tab

4 68HC12 Input Capture / Output Compare Registers TCx - Timer Input Capture / Output Compare x $0090 Bit Bit 8 TC0 $0091 Bit Bit 0 $0092 Bit Bit 8 TC1 $0093 Bit Bit 0 $009C Bit Bit 8 TC6 $009D Bit Bit 0 $009E Bit Bit 8 TC7 $009F Bit Bit 0 RESET = $ HC12 TCTL3 & TCTL4: Time Control Registers TCTL3 & TCTL4- Timer Control Registers >Edge B (falling edge) and Edge A (rising edge) $008A RESET Edg7B Edg7A Edg6B Edg6A Edg5B Edg5A Edg4B Edg4A TCTL $008B RESET Edg3B Edg3A Edg2B Edg2A Edg1B Edg1A Edg0B Edg0A TCTL Disabled 01 Rising Edge 10 Falling Edge 11 Any Edge Tech: Tab

5 $008C RESET 68HC12 TMSK1: Timer Interrupt Mask 1 TFLG1: Timer Interrupt Flag 1 TMSK1: Timer Interrupt Mask 1 (for IC/OC) >0 = Interrupt disabled; 1 = Interrupt enabled C7I C6I C5I C4I C3I C2I C1I C0I TMSK TFLG1: Timer Interrupt Flag 1 (for IC/OC) > 0 = No interrupt (or interrupt cleared); 1 = Interrupt has occurred $008E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1 RESET CxF Flag: Automatically set each time specified IC edge detected To clear, write a 1 to the flag bit 9 68HC12 Measuring Elapsed Time: IC Programming Example Measure the Elapsed time between Events using Input Capture Elapsed time Programming Example: Measure Elapsed Time Between Events using IC3 IC3.asm With simulator, use the signal generator > Select square wave with frequency of (10kHz) For f=10khz, T=100 s If E=0.125 s (simulator), then T = 800 E-clocks If E=0.5 s (our UF board), T = 200 E-clocks Can you send the time in units of s to an LCD? 10 5

6 68HC12 Best and Worst Case for IC Best Case vs. Worst Case of Input Capture Elapsed time > Interrupt Latency How long do we wait to get to the interrupt service routine? Does this effect the pin action of the ICx feature? Definition: M&M: Sec 8.8 Latency -- the time that elapses between a stimulus and the response to it [synonyms: reaction time, response time] 11 68HC12 Signal Detection: Another IC Programming Example Detect a Signal Pattern using Input Capture T (Period) T (Period) T (Period) T (Period) Time Unit: E-cycles IC5_Det.asm 12 6

7 See doc8045: Section 6 describes several similar examples of how to complete tasks. XMEGA Input Capture Example Task: Configure TCC0 with Input Capture Channel A enabled. The Input Capture is triggered by the falling edge of PC0 See doc8045: Sec Configure PC0 for input, triggered on falling edge 2. Select PC0 as multiplexer input for event channel 0 3. Configure TCC0 for input capture by setting event source and event action to Input capture in CTRLD 4. Enable input capture channel A by setting the CCAEN bit in CTRLB 5. Start the TC by selecting a clock source (CLKSEL in CTRLA) 6. Wait for Input Capture Interrupt Flag A in INTFLAGS to be set 7. Read input capture value from the CCA[H:L] register 8. Go to step 4 13 See doc8331, Sec 14 & doc8385, Sec 16 doc8045 XMEGA Input Capture Input Capture available > Input capture with noise cancelling > Frequency capture > Pulse width capture > 32-bit capture One compare match or input capture interrupt/event per CC channel Not possible to use the same TC module for both input capture and compare match at the same time Input capture can be used to time stamp events > I.e., measure waveform parameters like frequency or duty cycle 14 7

8 See doc8331: Figure XMEGA Input Capture Select the input capture event action to allow the interrupt flags to be set and indicate that there are valid capture results in the corresponding CC register Two timer/counters can be used together to enable 32-bit input capture The Capture X results are put in a CC register 15 EEL 3744 Sec 3-5 XMEGA CCx The compare/capture channels consist of a set of 16-bit registers named CCx[H:L], where x indicates the channel >Timer0, with 4 channels, has CCA[H:L], CCB[H:L], CCC[H:L] and CCD[H:L] >Timer1, with 2 channels has CCA[H:L] and CCB[H:L]. >Each CCx[H:L] register has a buffer register, CCxBUF[H:L] 16 8

9 Sec 3.6 XMEGA Event Input Selection The TC input capture system uses the event system to trigger an input capture (see Lab 7) When the TC is used for input capture, all enabled input capture channels must be associated with an event channel > The EVSEL[3:0] bits of the CTRLD register select the event channels that are associated with the input capture channels > EVSEL3 must be 1 to select an event source > EVSEL[2:0] selects between the 8 event channels TCpy_CTRLD, p=c, D, E, or F; y=0,1, or 2; example TCF0_CTRD 17 Sec 3.6 XMEGA Event Input Selection The event channels associated with the different channels cannot be selected individually The % is the modulo operator > Note that when a set of event channels have been selected for the TC, this does not mean that these event channels are used exclusively by the TC > The TC simply listens to the selected channels and is able to receive events on these event channels Table 3-2 Input capture channel Global event channel A N B (N+1)% 8 C (if available) (N+2) % 8 D (if available) (N+3) %

10 Sec 3.6 XMEGA Event Input Selection Example 1: > CTRLD s EVSEL3 = 1 and EVSEL[2:0] = 0 means that input capture channels A, B, C and D are triggered by event channels 0, 1, 2 and 3 respectively Example 1: > CTRLD s EVSEL3 = 1 and EVSEL[2:0] = 6 means that input capture channels A, B, C and D are triggered by event channels 6, 7, 0 and 1 respectively Table 3-2 See doc8331, Sec Input capture channel Global event channel A N B (N+1)% 8 C (if available) (N+2) % 8 D (if available) (N+3) % 8 19 Sec 3.6 XMEGA Event Input Selection and Bouncing If the event source is subject to noise, e.g., caused by the bouncing of an external switch, it is possible to enable digital filtering on the event channel >See application note AVR1001 for more information on the event system and its digital filtering capabilities 20 10

11 See doc8331: Figure XMEGA Capture Channel The CC channels can be used as capture channels to capture external events and give them a timestamp To use capture, the counter must be set for normal operation 21 See doc8331: Section EVACT[2:0]: Event Action > These bits define the event action the timer performs on an event according Selecting any of the capture event actions changes the behavior of the CCx registers and related status and control bits to be used for capture The error status flag (ERRIF) will indicate a buffer overflow in this configuration XMEGA TC CTRLD Control register D EVACT[2:0] Group Config Event Action 000 Off None 001 CAPT Input capture 010 UpDwn Externally ctrl count 011 QDEC Quad decode 100 Restart Restart per 101 FRQ Freq capture 110 PW PW capture TCpy_CTRLD, p=c, D, E, or F; y=0,1, or 2; example TCF0_CTRD 22 11

12 See doc8331: Section XMEGA TC CTRLA Control Register A CLKSEL[3:0]: Clock Select CLKSEL[2:0] 0000 Group Config Off Description None (TC OFF) 0001 DIV1 Prescaler: Clk 0010 DIV2 Prescaler: Clk/ DIV4 Prescaler: Clk/4 See doc8331: 0100 DIV8 Prescaler: Clk/8 Table DIV64 Prescaler: Clk/ DIV256 Prescaler: Clk/ DIV1024 Prescaler: Clk/1024 nnn event channel 1nnn EVCHn Event channel n, n=0,,7 TCpy_CTRLA, p=c, D, E, or F; y=0,1, or 2; example TCF0_CTRD 25 See doc8331: Section XMEGA TC CTRLB Control Register B CCxEN: Compare or Capture Enable >Setting these bits in the FRQ or PWM waveform generation mode of operation will override the port output register for the corresponding OCn output pin >When input capture operation is selected, the CCxEN bits enable the capture operation for the corresponding CC channel TCpy_CTRLB, p=c, D, E, or F; y=0,1, or 2; example TCF0_CTRB 26 12

13 XMEGA TC Normal Mode Sec Normal Mode MUST BE USED for Input Capture > Counter will count in the direction set by the DIR bit in CTRLF for each clock until it reaches TOP set by PER[H:L] or BOTTOM (zero) > When TOP is reached when up-counting the counter will be reset to zero > When BOTTOM is reached when downcounting, the counter will wrap around to the value in PER[H:L] 28 XMEGA TC Input Capture Setup Setup GPIO for input pin and event on any edge > PORTF_DIR, PORTF_PIN0CTRL Configure TC system (and event system) > TCF0_CTRLA, TCF0_CTRLB, TCF0_CTRLD, EVSYS_CH0MUX, TCF0_PER Configure TC interrupts or use Event System > TCF0_INTCTRLB, PMIC_CTRL Input Capture TC interrupt service routine > TCF0_CCA, TCF0_CTRLFSET Sec

14 See doc8045: Section 6 describes several similar examples of how to complete tasks. XMEGA Input Capture Example Task: Configure TCC0 with Input Capture Channel A enabled. The Input Capture is triggered by the falling edge of PC0 See doc8045: Sec Configure PC0 for input, triggered on falling edge 2. Select PC0 as multiplexer input for event channel 0 3. Configure TCC0 for input capture by setting event source and event action to Input capture in CTRLD 4. Enable input capture channel A by setting the CCAEN bit in CTRLB 5. Start the TC by selecting a clock source (CLKSEL in CTRLA) 6. Wait for Input Capture Interrupt Flag A in INTFLAGS to be set 7. Read input capture value from the CCA[H:L] register 8. Go to step 4 31 The End! 32 14