COSC3215. Input Capture Output Compare
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1 COSC3215 Input Capture Output Compare
2 Time Base A 16-bit free running counter is used as a time base for the IC/OC system. CLK0 CLK1 4:1 MUX Timer Clock TIMCLK PACK/256 PACK/65536 PACK PCLK
3 CLK1 CLK0 Action 0 0 PCLK 0 1 PACLK 1 0 PACLK/ PACLK/65536
4
5 TOF bit is set when the free running counter changes from $FFFF to $0000. Reset by writing 1 to it. It is cleared by any access to the counter if the TFFCA is set
6 $0004
7 IC/OC The TIM module in HCS12 is equipped with 8 complete and individual dual function input capture/output compare channels. Channels are connected via IOC[7:0] pins which share port T PT[7:0] Configures through TIOS register where IOCn is 1 for output compare, 0 for IC
8 Input Capture The input capture system is a 16-bit binary stopwatch. It can capture the time of a specific, user-defined, event. The event could be falling, rising, or any edge. Since the free running counter is used by all the channels, it is a bad idea to reset it, rather elapsed time between two events is used.
9 Input Capture MCLK C3I CLI prescalar TEN Free running counter C3F TC3H TC3H IOS3=0 IOC pin 3 16-bit latch Edge detect EDG3A EDG3B
10
11 Indicates an interrupt condition has occurred, to clear it write 1 to it. To enable (1) the corresponding flag from issuing an interrupt
12 Input Capture When the user defined event occurs, then 1. The current value of the free running counter is latched in TCnH/L 2. The associated channel flag CnF is set 3. If the corresponding channel interrupt enable CnI has been set, the channel will generate an interrupt event.
13 Capturing width of a single active Assumption high pulse 1. The pulse length is less than the rollover time of the counter. 2. The pulse width is longer than the time it takes to do steps 4 thorough 7 3. The channel is set as input capture (TIOS)
14 Capturing width of a single active high pulse 1. Set the input capture to wait for a rising edge EDG2B:EDG2A =01 2. Monitor the associated flag C2F 3. When the flag is set, it means event occurred, and time is latched in TC2H/L 4. Read the value in TC2H/L and store it somewhere 5. Reset the C2F (write 1)
15 Capturing width of a single active high pulse 6. Set the input capture for a falling edge EDG2B:EDG2A=10 7. Monitor C2F 8. When set, the counter value is latched in TC2H/L 9. Read the value in TC2H/L and store it 10. Calculate the difference between these 2 values 11. Convert it to time (you know the timer clock)
16 Output Compare It allows the user to generate an output signal when the value of the free running counter reaches the value stored in TCnH/L That signal could be 0, 1, or toggle OMn OLn Configuration 0 0 Timer disconnected 0 1 Toggle OCn 1 0 OCn set to Ocn set to high
17 Output Compare MCLK prescalar TEN Free running counter OMn OLn 16-bit latch Edge detect IOC pin 3 TCnH TCnH C3I CLI IOS3=0 CnF
18 OC Channel 7 Channel 7 has a special control over the OC Assume register OC7M Assume register OC7D When TC7 matches TCNT, the logic on the output pins OC i changes if OC7M i is 1 and is changes to OC7D i Can be used for PWM (changes twice in a cycle, one by 7, and one by the port i)
19 Pulse Accumulator 9S12DP256 has twp pulse accumulators, PAA, and PAB. These are connected to TIM inputs 7 and 0 In order to use the PA, you have to disconnect channel 7(0) 0 in the corresponding TIOS bit OM7:OL7 = 00 in TCTL1 OC7M7 set to 0 in OC7M
20 Pulse Accumulator The pulse accumulator can be configured in two modes of operation. Event counter mode: This mode used to count events on the PAI pin Gated time accumulator mode: In this mode, PA count pulses from a divide/64 clock. It is gated because counting is enable when the PAI is high(low) only. It maintain current count when disabled.
21 Interrupt Logic PAOVI PAOVF PAI PAIF PAE PEDGE PACNT3 PACNT2 Edge detect PACLK/256 PACLK/ bit counter PACLK Divide by 64 From PT7 MCLK PAMOD
22 Pulse Accumulator PAI: PA Interrupt PAIF: PA Input edge flag PAOVI: PA Overflow Interrupt PAOVF: PA overflow flag PAE: PA Enable PEDGE: PA edge control PAMOD: PA mode
23 Pulse Accumulator PAMOD=0 PEDGE=1: Rising edge on PT7 increments PEDGE=0; Falling edge on PT7 increments PAMOD=1 PEDGE=1: PT7 LOW increments(- edge) with PMOD/64; PAIF is set with trailing rising edge PEDGE=0: PT7 HIGH increments (- edge)with PMOD/64; PAIF is set on trailing falling edge
24 Event counter mode Interrupt Logic PAOVI PAOVF PAI PAIF PAE PEDGE PACNT3 PACNT2 Edge detect PACLK/256 PACLK/ bit counter PACLK Divide by 64 From PT7 MCLK PAMOD
25 Gated time accumulation mode Interrupt Logic PAOVI PAOVF PAI PAIF PAE PEDGE PACNT3 PACNT2 Edge detect PACLK/256 PACLK/ bit counter PACLK Divide by 64 From PT7 MCLK PAMOD
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