An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVC/H.264 Transform Coding Design

Transcription

1 An Efficient Sprios Sppression echniqe (SPS) and s Applications on PEG-4 AVC/H64 ransform Coding De Kan-Hng Chen, Ko-Chan Chao, Jinn-Shyan Wang, Yan-Sn Ch Department of Electrical Engineering, National Chng Cheng niversy, Chia-Yi 6, aiwan, ROC ~8 ckh@vlsieeccedtw Jin-In Go Department of Compter Science and Information Engineering, National Chng Cheng niversy, Chia-Yi 6, aiwan, ROC ~ jigo@csccedtw ABSRAC his paper proposes an efficient Sprios Sppression echniqe (SPS) and s applications on an PEG-4 AVC/H64 transform coding de here are three techniqes addressed in this paper, which are () the SPS, () the direct -D algorhm, and () the interlaced I/O schedle to solve the de challenges indced by both the real-time processing and low-power reqirements he major novelty of this paper is implementing the SPS concept on the transform archectre for H64, which save 9% power conmption at the cost of 9% area price oreover, the proposed transform de also possesses 65% higher hardware efficiency throgh the PA index than the existing des Categories and Sbject Descriptors B7 [ypes and De Styles]: VLSI General erms: De Keywords: Direct -D integer transform, Digal cinema, H64, HDV, Low-power de, PEG-4/AVC INRODCION ltimedia applications on portable devices attract more and more research interests and de challenges in recent years One of the accompanying challenges is to lower down the power conmption of the circ des so as to prolong the operation time of the portable devices on the basis of limed energy pply H64 is an emerging mltimedia CODEC system and has high possibily to be applied in wireless environments de to s ificant compression ratio improvement and network friendly de as compared to previos PEG standards [] While, H64 CODEC system also indces mch more algorhmic complexy compared wh the former PEG CODEC systems [], which increases the cost in realtime implementing the H64 video coding systems herefore, dedicated low power VLSI des become good choices in the Permission to make digal or hard copies of all or part of this work for personal or classroom se is granted whot fee provided that copies are not made or distribted for prof or commercial advantage and that copies bear this notice and the fll cation on the first page o copy otherwise, or repblish, to post on servers or to redistribte to lists, reqires prior specific permission and/or a fee ISLPED 5, Agst 8-, 5, San Diego, California, SA Copyright 5 AC /5/8 $5 H64 implementation considering both the real-time processing and low-power reqirements here are for kinds of 4x4 transforms in a H64 coding system, ie forward, inverse, forward-hadaard, and inverse- HADAARD transforms he mltiple transforms ( mltransform for short) coding may be reqired simltaneosly in a H64 video encoder and the data processing performance of the mlti-transform coding may be times higher than that of a single transform coding, as depicted in Fig Fig tells that the H64 mlti-transform reqires 9 pixels/sec and 787 pixels/sec data throghpt rates to achieve the processing reqirements of HDV 8i (9x88@6Hz) and digal cinema (496x48@Hz) video formats, respectively Sch strict performance reqirements imply that a high-performance mlti-transform accelerator is inevable (pixels/sec) hro-indi hro-mlti 4CIF (74x576, fps) HDV 7p (8x7, 6 fps) Video formats HDV 8i (9x88, 6 fps) Digal cinema (496x48, fps) Fig : he throghpts reqired to reach the real-time video reqirements, where hro-indi denotes throghpt reqired for individal forward and inverse transforms, and hro-mlti denotes throghpt reqired for mltransform Althogh there are several papers [-7] discssing abot the VLSI de of transform coding for H64, there is still research space to be discovered ch as low-power de, hardware efficiency, and system integration of the mltiple transform de ises he provided data processing rate of the de [4], ie pixels/sec at 8 Hz operating clock, is not fficient for mlti-transform in HDV 8i and digal cinema video coding he data processing rate of the de [5] is only /4 of the de [4] Hence, also cannot reach the real-time processing reqirement of mlti-transform he de [6-7] can satisfy the real-time processing reqirement of mlti-transform, bt they ffer from the wide I/O bandwidth when integrated wh H64 coding systems In addion, all of the existing des do not mention abot the system integration ises and the low-power de ises, which are of great importance 55

2 Considering both the real-time processing and low-power reqirements, we mmarize the proposed techniqes in this de as follows: () An efficient techniqe named Sprios Sppression echniqe (SPS) to eliminate the sprios power conmption in the H64 transform; () A efficient mlti-transform de for H64 exploing the proposed direct -D algorhm; () An interlaced I/O schedle for integrating the proposed mltransform de wh H64 systems Data vales ime (ns) Fig : he data analysis of the inpt data in the proposed transform de when execting H64 forward transform he inpt data of the transform coding in the PEG-//4/H64 systems tend to flctate in a small range of b-width de to the temporal and spatial redndancy in video als However, the transform coding de still needs to provide the maximm data bwidth to avoid accracy loss Hence, the transform coding de might have sprios al transions which dissipate extra power to perform the comptation Fig shows the data (ie and ) analysis of the adder/btractor in PE-I, shown in Fig 6, in the example of forward transforming a real video seqence (he archectre de shown in Fig 6 will be frther discssed in Section) In Fig, most of the inpt data range between - and implying that the high-byte data do not affect the comptation relts From the view point of logic de, the proposed SPS separates the adders/btractors in the transform coding de into two parts, ie ost Significant Part (SP) and Least Significant Part (LSP), and trns off the SP circs whenever they do not affect the comptation relts oreover, the proposed SPS has been applied to an efficient mlti-transform coding de in H64 he high hardware efficiency is achieved by the proposed direct -D transform algorhm which can compte one 4x4 block of the -D transforms in H64 every two cycles whot sing transpose memory or registers herefore, the proposed efficient mltransform coding de can perform HDV 8i and digal cinema video formats when operated at 5 Hz and Hz, respectively he synthesis relts tell that the proposed efficient mlti-transform coding de owns more than Hz clock freqency at the cost of 648 gates, which is eqivalent to that of the row-colmn de [4] he power dissipation meared by NANOSI is 44 mw when the proposed mlti-transform coding de is operated at 5 Hz When the SPS is eqipped, the area cost increases to 789 gates and the power dissipation decreases to 98 mw which implies that the proposed SPS techniqe can save abot 9% power conmption at the cost of 9% area prices when applied to the transform coding for H64 he rest of this paper is arranged as follows: Section describes the proposed de approaches inclding SPS and direct -D transform algorhm Section presents the archectre de of the transform coding for H64 as well as the system integration ises of the proposed de Section4 discsses the implementation and verification of the proposed de he power analysis and comparisons of the proposed de will be illstrated in Section5 Finally, we conclde this paper in Section6 PROPOSED DESIGN APPROACHES Proposed Sprios Sppression echniqe (SPS) o illstrate the inflence of those sprios al transions mentioned in Fig, five cases of a 6-b addion are explored as shown in Fig he st case illstrates a transient state in which the sprios transions of carry als occr in the SP thogh the final relt of the SP are nchanged he nd and rd cases describe the sations of one negative operand adding another posive operand whot and wh carry from LSP, respectively oreover, the 4 th and 5 th cases respectively demonstrate the condions of two negative operands addion whot and wh carry-in from LSP In those cases, the relts of the SP are predictable, therefore the comptations in the SP are seless and can be neglected Eliminating those sprios comptations will not only save the power conmed inside the SPS adder/btractor bt also decrease the glching noises which will affect the next arhmetic circs Case (): (A 5 A 4 A 8 ) = ( ), (B 5 B 4 B 8 ) = (), C 7 = (8) (64) (9) Case (): (A 5 A 4 A 8 ) = (), (B 5 B 4 B 8 ) = (), C 7 = ( 6) ( 5) ( ) ( 6) ( 5) ( 66) Case (4): (A 5 A 4 A 8 ) = (), (B 5 B 4 B 8 ) = (), C 7 = Case (): (A 5 A 4 A 8 ) = (), (B 5 B 4 B 8 ) = (), C 7 = ( 96) (4) ( 8) ( 96) ( 5) ( 48) ( 8) (9) (64) Case (5): (A 5 A 4 A 8 ) = (), (B 5 B 4 B 8 ) = (), C 7 = Fig : Sprios transion cases in the H64 transform de Fig 4(a) shows a 6-b adder/btractor example based on the proposed SPS In this example, the 6-b adder/btractor is divided into SP and LSP at the place between the 8 th b and the 9 th b Latches implemented by simple AND gates are sed to control the inpt data of the SP When the SP is trned on, the inpt data remain the same as al, while the SP is trned off, the inpt data become zero vales to avoid glching power conmption Detection logic implementing the KARNAGH maps shown in Fig 4(b) is introdced to determine whether the SP shold be trned off or not Sign-extension circs implemented by Complementary Pass-ransistor (CPL) circs are sed to compensate the of the SP Both the latches and the extension circs are implemented by simple logic gates in order to redce the addional overhead as most as possible 56

3 A[5:8] B[5:8] A[7:] B[7:] A 5 A 4 A A A A A 9 A 8 Latch-A Latch-B A and = & A [5:8]; A nor = ~ A [5:8]; B and = & B [5:8]; Latch-A SP addb LSP addb B nor = ~ B [5:8]; C LSP C LSP A SP = A and (~ A nor ); PS 5 PS 4 Sign-Ext PS PS PS PS PS 9 PS 8 carr-ctrl carr-ctrl Pdo-S [5:8] Sign-Ext B SP = B and (~ B nor ); = ~ [(A and A nor ) & (B and B nor )]; S [5:8] S [7:] C ot AB ASP, BSP carr_ctrl ASP, BSP A-B ASP, BSP carr_ctrl ASP, BSP Detection Logic of SPS A[5:8] B[5:8] Detection Logic carr-ctrl (b) Fig 4: (a) A 6-b low-power adder/btractor example based on the proposed SPS; (b) de of the detection logic Proposed direct -D transform algorhm Becase of the high similary of fnctionaly among the H64 4x4 transforms, we only take the forward transform for example to illstrate the proposed direct -D transform algorhm First, the rowcolmn decomposion method for realizing N-point -D transforms is reviewed as follows: Y N = t ti N = st C C i, t, = t ), s, t = where denotes the inpt data, denotes the intermediate data between the st dimensional and the nd dimensional transforms, Y denotes the otpt data, C denotes the transform coefficients, and denotes the transpose matrix of Obviosly, a block of N N register array or memory is necessary to temporarily store the intermediate data and transpose s direction However, if we bstte Eq () into Eq (), the -D transform can be wrten as Eq (): Y st = C = C s t i ) = C C ) C s C i C i ) ) C s( ) ( ) i Eq () illstrates that if we can obtain the vales of ic, i C,, ( ) ic, ie N or C, = i { t = }, prior to other elements in dring colmn-wise transform, the row-wise transform can continally calclate { Y st s = } and eliminate the transpose storage of { = } oreover, the -D forward transform involves t the following calclation: C ) () () () (a) C k k C k = k = = k k = C C k k k k = (4) = = ( ) ( ) =, = Also, Eq (5) can be acqired from Eq () by specifying t = and t = as follows: Y C s = Y (5) s C = C, s = Becase of =, we can obtain the otpt data t t { Ys and Ys s = } by bstting Eq (4) into Eq (5) to relt in Eq (6) ch that the intermediate data { and = } can be discarded Y Y s s = = = C C C Following the similar procedre, we have: Y Y s s = C = C = C, s =, s = Conseqently, all the otpt data Y can be compted from Eq (6) and Eq (7), which denotes the direct -D transform in the proposed algorhm hs, the transpose storage of the intermediate data is completely removed (6) (7) 57

4 HE ARCHIECRE DESIGN Archectre of this chip In order to meare the power dissipation of the efficient mltransform coding de when processing natral video data, we integrate I/O schedling modles as well as the efficient mltransform coding de into this chip Besides, another mltransform coding de for other research prposes is also involved de to the high similary of the I/O interfaces between these two kinds of mlti-transform coding des Fig 5 illstrates the archectre of this chip inclding the Inpt Schedling odle (IS), the Efficient mlti-ransform coding De (ED), another mlti-transform coding de (PD), and the Otpt Schedling odle (OS) he inpt schedling modle and otpt schedling modle are deed for chip testing he inpt schedling modle can provide eher psedo-random data from the LFSR or the natral video data from the inpt bffer, and controls the timing and order of the inpt data of the transform coding sers can select to se which mlti-transform coding de by the control al named core_sel that is also shown in Fig 5 At last, the otpt schedling modle scans ot the relts of the transform coding de clk start recyc trst_n test_mode core_sel () It can compte the -D transform in H64 directly whot eqipping a transpose memory hese two featres make the proposed archectre become a high performance and low cost de, which will be frther illstrated in Section5 rans_sel PE-I- lsft_en Y << Y /- rsft_en Y >> << >> _ Y /- 8/7 rsft_en lsft_en Y Y Y Y Y Y Y Y Y Y Y Y Comprehensive FS controller 8/7 8/7 8/7 PE-I- PE-I- PE-I-, / -, / PE-II- : SPS adder : Conventional adder - - -, -, 8/9 8/9 -, - PE-II- Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Fig 6: he proposed efficient hardware de for H64 -D mlti-transform coding In_FS Inpt select Sps_sel ot_sel 5b D E 5b 5b In blk In blk [4:] [4:] 4b D E 4b 4b clk rst_n Inv_tran_sel tran_sel _clk Efficient ransform De (ED) Parallel ransform De (PD) 8*8b 6*8b 6*8b 8b Cycle Cycle Cycle 4 Cycle 5 Fi Fi Fi Fi Forward transform Ii Ii Ii Ii Inverse transform Ic Ic Io Fi Fc Fo Ii Ic Io β: inpt process of the forward transform β: core process of the forward transform β : otpt process of the forward transform β : inpt process of the inverse transform β : core process of the inverse transform β: otpt process of the inverse transform α : cycle nmber of each process β : block nmber 5b In blk 5 Inpt Schedling odle (IS) [4:] rst_n Inv_tran_sel tran_sel _clk Sps_sel Fig 5: Chip archectre of the proposed de Otpt Schedling odle (OS) Efficient transform coding archectre for H64 he archectre of proposed efficient mlti-transform de (ED) based on the direct -D algorhm is illstrated in Fig 6 he proposed de possesses two types of PEs he for PEs in the left-hand-side of Fig 6, denoted by PE-I, are sed for compting the st dimensional transforms he two PEs in the right-hand-side of Fig 6, denoted by PE-II, are sed for compting the nd dimensional transforms he proposed mlti-transform de can be configred to compte different types of transforms by inserting mltiplexers appropriately A comprehensive Fine State achine (FS) controller wh a transform selection al not only provides the commands to both the PE-I and PE-II for realizing the transform comptation, bt also enables the sers to select the transform type he proposed de possesses the following two distingishing featres: () It can process one 4x4 block in two clock cycles wh eqivalent hardware cost of the R-C des Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Cycle Fi Fi Fi Fi Fi Fi Fc Fc Fo Fc Fo Fc Fo Fo Fo Ii Ii Ii Ii Ii Ii Ic Ic Fig 7: Interlaced data schedle of the proposed H64 transform de Io Io Io Io Io Io Considerations of system integration One important featre of the proposed de is that they can process mltiple types of transforms needed in H64 encoders o integrate the proposed mlti-transform de to a general H64 system wh data processing capabily of 4 pixels/cycle [4], an interlaced I/O schedle is proposed as shown in Fig 7 here are two types of transforms, ie forward and inverse transforms, arranged in the proposed interlaced I/O schedle Each sqare in Fig 7 represents a process of one 4x residal vector It takes 4 cycles to prepare one 4x4 residal block, cycles for the proposed de to compte the 58

5 relts, and 4 cycles reqired to deliver the 4x4 transformed block to the next stage Becase the processing time reqired for preparing the I/O data, ie 4 cycles, are times of that reqired for compting one type of transform, ie cycles, the proposed de can compte both the forward and the inverse transform dring the same time for data preparation in an interlaced way 4 IPLEENAION AND VERIFICAION he proposed H64 transform de has been coded in hardware description langage (HDL) by following the R [8] coding rles It has been verified throgh C behavioral simlation, nlint HDL coding rle check, VERILOG RL simlation, SYNOPSYS logic synthesis, VERILOG gate-level simlation, Silicon Ensemble placement and roting, de rle check (DRC), layot vers schematic (LVS), and post-layot simlation he proposed de has been implemented sing a 8-m COS technology [9] From Fig 8, we can find that the most optimized synthesis relt is obtained by sing ns timing constraint becase any try to constrict the timing constraint will lead to hge amont of area increment Area (gate) H H_SPS iming constraint (ns) Fig 8: he synthesis relts in terms of area vers timing constraint he SYNOPSYS synthesized relts mmarized in able show that the gate cont of the proposed efficient mlti-transform de is 648 When the SPS adder/btractors are eqipped, the gate cont of the proposed de increases to 789 Besides, the power mearements of the transistor-level simlation by NANOSI are also shown in able From able, we can find that the proposed de conmes 44 mw when targeting at HDV 8i video formats whot voltage scaling When the SPS adder/btractors are eqipped, the power dissipation of the proposed de is redced to 98 mw In other words, the proposed SPS can save abot 9% power dissipation at the cost of abot 9% area increment when applied to the proposed efficient mlti-transform de Frthermore, able reports the chip implementation relts he total area of the test chip shown in Fig 5 is 55x55 mm (inclding I/O pads) when the SC P6 8-µm technology is adopted he realization reports of the efficient mlti-transform de are listed in able (b) he power pply of the proposed de is separated from other modles to make re that only the reqired crrent flow is meared he proposed SPS-based efficient transform de can achieve the video formats of HDV 7p (8x7@6Hz), 8i, and digal cinema by conming 4mW, 98mW, and 956mW when operated at Hz, 5 Hz, and Hz, respectively After voltage scaling, the proposed de can achieve the corresponding video formats by conming 5mW, 46mW, and 8mW wh 6V, 8V, and V, respectively At last, the layot of the proposed chip is shown in Fig 9 able: he performance analysis of the proposed SPS when applied to the efficient mlti-transform de for H64 W/O SPS W/ SPS (mw) redction (%) Freq (Hz) Area (gates) Area inc (%) Cr Path (ns) able (a): he specifications of the proposed chip Proposed SPS-based H64 mlti-transform chip Process SC P6 8m Chip area 55*55 mm Operating freqency Hz able (b): he specifications of the proposed de Proposed SPS-based efficient mlti-transform de Spply voltage ~ 8v Operating freq ~ Hz hroghpt 8 pixels/cycle 5mW@6V/4mW@8v, Hz (7p HD) 46mW@8V/98mW@8v, 5 Hz (8i HD) 8mW@V/956mW@8V, Hz (Digal cinema) Processing capabily Hz (Digal cinema) r cont 86 ED IS OS PD Fig 9: Layot of the proposed chip 59

6 5 PERFORANCE EVALAION AND COPARISON In this section, we will compare the performance of the proposed de wh other existing des In addion to directly compare the reported data from the des [4-6], we also implement the de [4] sing the same COS technology to fairly compare the performance on the data throghpt rate, the hardware cost, and the power dissipation between them and or de able shows the performance comparisons of the proposed mlti-transform de wh the reported data from the existing des he de [4] adopts two -D transform PEs and a 6x6 register array served as transpose memory for -D transform It possesses the throghpt of 4-pixels/cycle and costs 658 gates when implemented in a 5µm technology Becase the clock als of the 6x6 register array shold be conversed every half cycle, the 6x6 register array might conme large amont of power However, the de [4] does not report the power conmption he de [5] ses one -D transform PE and a transpose register array to compte the -D transform It possesses the throghpt of -pixels/cycle and costs 54 gates for single transform when implemented in a 5µm technology he des [6] and [7] directly spread the -D transform comptation he de [6] possesses the throghpt of 6-pixels/cycle and costs 778 gates when implemented in FPGA devices able : Performance comparisons of the proposed efficient mlti-transform de wh reported data from the existed des PA stands for data hroghpt rate Per n Area hroghpt PA ype of Area Freq (pixels/sec/g transform (gate) (Hz) ( pixels ate) /sec) Wang [4] ltiple K Wang [4] redeed ltiple K Li [5] Single K Kordasiewicz [6] Single K Proposed SPSED ltiple K able 4: Performance comparisons of the proposed mlti-transform des wh de [4] re-deed targeting at HDV 8i video format Wang[4] redeed Proposed de hro (pixels/sec) Spply Freq (Hz) (P), (mw) Norm P (%) v Considering the hardware efficiency of a de, we adopt the performance index of hroghpt rate Per n Area (denoted by PA) defined as the ratio of data throghpt rate over hardware cost (in terms of gate cont) When adopting the PA as the comparison index, the higher the PA index is, the more efficient the de is he PA index in able indicates that the proposed SPS-based de is 65% more efficient than the de [4] redeed by sing the same technology According to the PA indexes shown in able, or de is the most efficient de as compared to the existing des [4-6] Frthermore, able 4 lists the post-layot power simlation relts meared by sing NANOSI on the proposed mlti-transform de and the de [4] re-deed by the same technology able 4 shows that the proposed de reqires only half the operating freqency of Wang s de [4] re-deed to accomplish the same throghpt rate In addion, based on the throghpt rate of 4 pixels/sec, Wang s de [4] re-deed and the proposed SPSbased de respectively conme 96mW and 98mW hat is, the proposed de achieve abot % power improvement when compared wh Wang s de [4] re-deed, based on the same data throghpt rate 6 CONCLSIONS his paper proposes an efficient Sprios Sppression echniqe (SPS) and s applications on transform coding IP de for H64 sing the proposed SPS techniqe, the sprios power occrred in the H64 transform coding can be redced he simlations illstrate that the proposed SPS techniqe can save 9% power conmption at the cost of 9% area price In addion, the proposed transform de also possesses higher hardware efficiency than the existing des by adopting the proposed direct -D transform algorhm to remove the transpose memory or registers oreover, the proposed mlti-transform de also takes the system integration ises into accont by balancing the data I/O rate and the data processing rate throgh an interlaced I/O schedle 7 ACKNOWLEDGEEN his work was pported by National Science Concil nder grant: NSC9--E-94-8 REFERENCES [] Stockhammer, Hannksela, and Wiegans, H64/AVC in wireless environments, IEEE ransaction on Circ and System for Video echnology, vol, No 7, pp657-67, Jly, [] R Schafer, Wiegand and H Schwarz, he emerging H64/AVC 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