Xilinx Answer Eye Qualification

Transcription

1 Xilinx Answer Eye Qualification Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability. It is important to note that Answer Records are Web-based content that are frequently updated as new information becomes available. You are reminded to visit the Xilinx Technical Support Website and review (Xilinx Answer 70915) for the latest version of this Answer. Introduction The LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) core is designed for evaluating and monitoring transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, as well as access to ports and the dynamic reconfiguration port attributes of the GTH transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. IBERT eye scan provides a picture of the serial signal error distribution. How can you determine whether the quality of the signal is good or bad? How can you judge from the eye scan if the signal has enough margin? This Long Form Answer Record helps to build a new tool dedicated to automatic eye qualification, combining IBERT with the GT_DEBUGGER (XAPP1322 and XAPP1295). IBERT + GT_DEBUGGER IBERT + GT_DEBUGGER (a.k.a. IBERT+) is an IBERT design with the GT_DEBUGGER s flexibility. A step by step method to modify the IBERT design is provided below. The GT_DEBUGGER s complete flow is described in XAPP1322 (GUI usage) and XAPP1295 (manual.do file edit). This article will use the GT_DEBUGGER GUI. A pre-requisite is that the GT_DEBUGGER is understood and the GUI installed. The GUI usage is not essential, the User could also follow the procedure in XAPP1295 and manually edit the.do file. IBERT design generation IBERT is the first choice debug tool for transceivers and thanks to the GT_DEBUGGER some additional features can be added. The user should start with creating a IBERT design, following the guidelines in IBERT Product Guide, for example (PG196) or (PG173). 1. Create an IBERT project with all high-speed links for test using the latest available VIVADO release. 2. Once the IBERT example design is generated, the User should proceed with synthesizing the design 3. Open the synthesized design and select File->Write Checkpoint 4. Open GT_DEBUGGER, following the guidelines in XAPP1322 (*)

2 5. From Menu File -> New project, create the new project. 6. Once the new Project is created, the GT_DEBUGGER will ask to select a DCP file. Please select the previously generated post synthesis IBERT DCP file. 7. When the DCP file is selected, the Run Analysis button is active. Run Analysis with GT debugger (it might take a long time). In this phase the GT_DEBUGGER reads the IBERT design and lists all available GTs and ports in the.do file.

3 8. Run Configuration with GT debugger -> set DRP yes -> click save all (it might take a longtime ) and then Exit. 9. Instrument with a GPIO all transceivers EYESCANRESET ports 10. Run Generate Bitstream with the GT debugger (it might take a long time) The GT_DEBUGGER can do much more, but for this particular application we only need the DRP port and EYESCANRESET ports activated. A DRP arbiter is automatically inserted so that no DRP access conflicts will happen between IBERT and GT_DEBUGGER.

4 11. The last step is to generate the bitstream. (*) the folder C:\Temp should be present otherwise GT_DEBUGGER will give an error. This requirement will be removed in GT_DEBUGGER GUI next release. The generated bitstream has all original IBERT capabilities together with additional features explained in the next paragraph. Vivado Hardware Manager will configure the FPGA using the new bitstream. Download and use the Tcl scripts GT_DEBUGGER makes a new design with the following structure: Please download from this Answer Record the two additional scripts, eye_qualify.tcl and eye_qualify_proc.tcl, dedicated to IBERT+ and save them in the design directory. The insert_gt_dbg directory contains all of the Tcl procedures for GT_DEBUGGER. In particular we will use insert_gt_dbg_hwproc.tcl and igd_eyescan.tcl. Vector Eyescan and margin analysis There is no apparend difference between IBERT and IBERT+ Once the FPGA is configured, the typical IBERT interface will show up. We can configure the serial links, optimize the TX setup, the PRBS pattern, select the RX equalizer exactly as in IBERT design.

5 IBERT+ can dialogue with the TCL console using some typical GT_DEBUGGER commands and scripts. For example, the script below will draw a vector eyescan with 8 directions. 1. Change the directory to the IBERT+ design 2. Copy and paste the code below into the Vivado Tcl Console source./insert_gt_dbg/insert_gt_dbg_hwproc.tcl source./insert_gt_dbg/igd_eyescan.tcl igd_eyescan init cx0y0 igd_eyescan run cx0y0 prescale_min=-1 prescale_max=-1 max_circle_div=8 init_window=1 The scripts provided with this Answer Record allows you to qualify the eye, automatically measuring some important eye parameters. IBERT counts the number of PRBS errors. However a channel with no errors and noisy signal is very different from another channel with no errors but clean, no jittered eye. Will my channel still have no errors if the temperature grows, or if the cable is more lossy, or if the crosstalk improves? In doing a channel qualification we need to know the signal margin, that is the room that the system has to get worse, before an error is made. IBERT does not measure the signal margin. The original IBERT only provides the eye Open Area. A wide open area eye might have a tiny margin. Because the error distribution eye might be strongly asymmetric, the eye open area is misleading. What we really care about is the vertical (Voltage) and horizontal (Time) distance ftom the data sampler in the middle of the eye to the closest failing corners in the two directions. In the picture below, the horizontal (Time) margin is shown.

6 We want to measure the true margin and compare with a quality mask. The mask used in this Answer Record was built to consider all PVT variations and be a robust term of comparison for target BER of 1E-9 measurements. Because further decreasing the target BER becomes unattainable due to the measurement times that are required, we want to extrapolate the channel behavior at lower BER. For this last operation the knowledge of the system jitter is fundamental. The true margin analysis is performed sourcing the script eye_qualify.tcl. The script can also be copied and pasted line by line into the Vivado Tcl console. The analysis steps are the following: 1) List the channels in the IBERT design 2) For each channel in the list, perform a vector eye scan, measure the margin, and compare against the mask. 3) Extrapolate the mask, assuming that the correct system jitter has been written in the eye_qualify_proc.tcl file 4) Generate a report file with a timestamp and condition summary for documentation. The script will use a vector eye scan with only four corners. In the script the User can select the target BER. The numbers in the diagram represent the exponential of the error rate (with no sign), for example a BER of 1E-5 will appear in the diagram as a 5. Beside the signal margin, also the signal horizontal and vertical offset is reported. The eye offset should be corrected with a fine link tuning. The extrapolated BER is just an indication of how the channel would perform in a much longer acquisition. As with any extrapolation, it can be wrong. In this analysis we assume that most of the deterministic jitter is captured by the initial measurement and we stretch the mask knowing the total random jitter.

7 Report file

8 Conclusion Thanks to the GT_DEBUGGER s flexibility, any GT design (in this Answer Record we used IBERT) can become a powerful quality measurement tool. The scripts provided measures only the relevant information and automatically compares the error distribution with a quality mask. A report file is generated. Please feel free to enhance these scripts and send your feedback to giovanni.guasti@xilinx.com Revision History 04/06/ Initial release