ΗΜΥ 408 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο IP Cores & Video. ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Αναπληρωτής Καθηγητής, ΗΜΜΥ

Transcription

1 ΗΜΥ 408 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο 2018 IP Cores & Video ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Αναπληρωτής Καθηγητής, ΗΜΜΥ ΗΜΥ408 Δ09 FPGA IP Cores & Video.1 Θεοχαρίδης, ΗΜΥ, 2018

2 Design Process Steps (Review) Definition of system requirements. Example: ISA (instruction set architecture) for CPU. Includes software and hardware interfaces including timing. May also include cost, speed, reliability and maintainability specifications. Definition of system architecture. Example: high-level HDL (hardware description language) representation - this is not required in ECE 664 but is done in the real world). Useful for system validation and verification and as a basis for lower level design execution and validation or verification. ΗΜΥ408 Δ09 FPGA IP Cores & Video.2 Θεοχαρίδης, ΗΜΥ, 2018

3 Design Process Steps (Review) Refinement of system architecture In manual design, descent in hierarchy, designing increasingly lower-level components In synthesized design, transformation of high-level HDL to synthesizable register transfer level (RTL) HDL Logic design or synthesis In manual or synthesized design, development of logic design in terms of library components Result is logic level schematic or netlist representation or combinations of both. Both manual design or synthesis typically involve optimization of cost, area, or delay. ΗΜΥ408 Δ09 FPGA IP Cores & Video.3 Θεοχαρίδης, ΗΜΥ, 2018

4 Design Process Steps (Review) Implementation Conversion of the logic design to physical implementation Involves the processes of: Mapping of logic to physical elements, Placing of resulting physical elements, And routing of interconnections between the elements. In case of SRAM-based FPGAs, represented by the programming bitstream which generates the physical implementation in the form of CLBs, IOBs and the interconnections between them ΗΜΥ408 Δ09 FPGA IP Cores & Video.4 Θεοχαρίδης, ΗΜΥ, 2018

5 Design Process Steps (Review) Validation (used at number of steps in the process) At architecture level - functional simulation of HDL At RTL level- functional simulation of RTL HDL At logic design or synthesis - functional simulation of gate-level circuit - not usually done in ECE 408/664 At implementation - timing simulation of schematic, netlist or HDL with implemention based timing information (functional simulation can also be useful here) At programmed FPGA level - in-circuit test of function and timing ΗΜΥ408 Δ09 FPGA IP Cores & Video.5 Θεοχαρίδης, ΗΜΥ, 2018

6 Hardware design in general Logic (RTL) design Logic simulation Logic debugging RTL code (Verilog) Logic synthesis RTL compilation Placement & routing H/W Platform RTL code & FPGA library RTL code & Target library Logic synthesis Placement & routing Logic synthesis Gate-level simulation Gate-level debugging FPGA bit-stream Netlist (EDIF) FPGA BOARD FPGA Debugging Netlist & Gate delay (SDF) GDSII & Test-vector Placement & routing Timing simulation Timing analysis Semiconductor fabrication GDSII General Hardware Design Flow / Methodologies. ΗΜΥ408 Δ09 FPGA IP Cores & Video.6 Θεοχαρίδης, ΗΜΥ, 2018

7 Xilinx HDL/Core Design Flow DESIGN ENTRY RTL HDL EDITING CORE GENERATION RTL HDL-CORE SIMULATION SYNTHESIS IMPLEMENTATION TIMING SIMULATION FPGA PROGRAMMING & IN-CIRCUIT TEST ΗΜΥ408 Δ09 FPGA IP Cores & Video.7 Θεοχαρίδης, ΗΜΥ, 2018

8 Xilinx HDL/core Design Flow Core Generation Select core and specify input parameters CORE GENERATOR EDIF netlist for core_name HDL instantiation module for core_name Other core_name files ΗΜΥ408 Δ09 FPGA IP Cores & Video.8 Θεοχαρίδης, ΗΜΥ, 2018

9 Xilinx HDL/core Design Flow - HDL Functional Simulation HDL instantiation module for core_name Set Up and Map work library RTL HDL Files Testbench HDL Files Test Inputs or Force Files Compile HDL Files Functional Simulate EDIF netlists for core_names HDLSIMULATOR Waveforms or List Files ΗΜΥ408 Δ09 FPGA IP Cores & Video.9 Θεοχαρίδης, ΗΜΥ, 2018

10 Xilinx HDL Design Flow - Synthesis All HDL Files Edit XST Synthesis Constraints Select Top Level EDIF netlists for core_names Synthesis/Implementation Constraints Select Target Device Synthesize XST Gate/Primitive Netlist Files (EDIF or XNF) Synthesis Report Files ΗΜΥ408 Δ09 FPGA IP Cores & Video.10 Θεοχαρίδης, ΗΜΥ, 2018

11 Xilinx HDL/core Design Flow - Implementation Gate/Primitive Netlist Files (XNF or EDN) Netlist Translation Map XILINX DESIGN MANAGER Model Extraction HDL or EDIF for Implemented Design Place & Route Create Bitstream BIT File Timing Model Gen Standard Delay Format File ΗΜΥ408 Δ09 FPGA IP Cores & Video.11 Θεοχαρίδης, ΗΜΥ, 2018

12 Xilinx HDL/core Design Flow- Timing Simulation HDL or EDIF for Implemented Design Standard Delay Format File Set Up and Map work Directory Testbench HDL Files Test Inputs, Force Files Compile HDL Files Compiled HDL HDL Simulate MODELSIM Waveforms or List Files ΗΜΥ408 Δ09 FPGA IP Cores & Video.12 Θεοχαρίδης, ΗΜΥ, 2018

13 Xilinx HDL Design Flow - Programming and In-circuit Verification Bit File Input Byte impact I/O Port FPGA Board Human Inputs Outputs ΗΜΥ408 Δ09 FPGA IP Cores & Video.13 Θεοχαρίδης, ΗΜΥ, 2018

14 The Xilinx Libraries Useful only if you have to instantiate (in your HDL) Xilinx primitives or macros (not all can be instantiated) from the Libraries guide. Note selection guide includes CLB counts and section at front on notation used to describe macros. ΗΜΥ408 Δ09 FPGA IP Cores & Video.14 Θεοχαρίδης, ΗΜΥ, 2018

15 Design Practices Use synchronous design. CLBs are actually reading functions from SRAM! Avoid clock gating. Avoid ripple counters. Avoid use of direct sets and resets except for initialization. Synchronize asynchronous signals as needed. Study timing issues handout. ΗΜΥ408 Δ09 FPGA IP Cores & Video.15 Θεοχαρίδης, ΗΜΥ, 2018

16 System Design Trend Integration Tens to hundreds of chips Chip-set Complexity Single chip ΗΜΥ408 Δ09 FPGA IP Cores & Video.16 Θεοχαρίδης, ΗΜΥ, 2018

17 Traditional System Design Chip Vendor Custom ASIC Chip Vendor Reuse Integration ΗΜΥ408 Δ09 FPGA IP Cores & Video.17 Θεοχαρίδης, ΗΜΥ, 2018

18 How to Implement The SoC? IP (Intellectual Property) Reuse Integration Core Provider SoC ΗΜΥ408 Δ09 FPGA IP Cores & Video.18 Θεοχαρίδης, ΗΜΥ, 2018

19 Design Technology Status Problems * Productivity gap * Shorter time-to-market * Designer shortage Solutions * Higher levels of abstraction * New reuse methodology * New business model ΗΜΥ408 Δ09 FPGA IP Cores & Video.19 Θεοχαρίδης, ΗΜΥ, 2018

20 Why Do We Need Reuse? Reuse practice is everywhere It has been a common practice in software developments for years. It has been a common practice in electronic product developments for years. => Goal: makes our life easier!!! ΗΜΥ408 Δ09 FPGA IP Cores & Video.20 Θεοχαρίδης, ΗΜΥ, 2018

21 Reuse in Software Development Reuse Package Procedure Software Function Reduce program complexity Increase manageability ΗΜΥ408 Δ09 FPGA IP Cores & Video.21 Θεοχαρίδης, ΗΜΥ, 2018

22 Reuse in Chip Design RTL/Logic schematic Layout RTL/Logic Library Reuse Cell Library ALU AND AND OR ΗΜΥ408 Δ09 FPGA IP Cores & Video.22 Θεοχαρίδης, ΗΜΥ, 2018

23 What are IPs (VCs)? IP = Intellectual Property. VC = Virtual Component. Soft IP: synthesizable HDL description. Firm IP: gate-level netlist. Hard IP: silicon block. ΗΜΥ408 Δ09 FPGA IP Cores & Video.23 Θεοχαρίδης, ΗΜΥ, 2018

24 IP Reuse for SOC Design IP1 Virtual Socket Interface(VSI) IP1 IP2 ASIC Intellectual Property (IP) Virtual Component (VC) ΗΜΥ408 Δ09 FPGA IP Cores & Video.24 Θεοχαρίδης, ΗΜΥ, 2018

25 IP-Centric System Design Model IP provider IP provider System design division Reuse System/IPs In-house core providers ΗΜΥ408 Δ09 FPGA IP Cores & Video.25 Θεοχαρίδης, ΗΜΥ, 2018

26 IP Business Model IP Tool Developer IP Business IP Provider IP Integrator ΗΜΥ408 Δ09 FPGA IP Cores & Video.26 Θεοχαρίδης, ΗΜΥ, 2018

27 Essential Issues for IP Reuse Essential Issues for IP Reuse IP Provider IP Business IP Integrator Library Documentation Quality Assurance Standardization Service Business Model Legal Issues Security Exploration Integration Methodology & Environment Standardization IP Tools ΗΜΥ408 Δ09 FPGA IP Cores & Video.27 Θεοχαρίδης, ΗΜΥ, 2018

28 Three Approaches for System Design Platform-based. Core-based. Memory Cores Processor I/O IP Synthesis-based. IP Glue Core CU DP ΗΜΥ408 Δ09 FPGA IP Cores & Video.28 Θεοχαρίδης, ΗΜΥ, 2018

29 System Integration Issues Platform to evaluate various VC blocks to make their choices and to integrate the blocks for their design verification. To verify the hardware design at system level, designers need to co-simulate or co-emulate the design flow using different computational models. Debugging and diagnosis environment to support system integration. ΗΜΥ408 Δ09 FPGA IP Cores & Video.29 Θεοχαρίδης, ΗΜΥ, 2018

30 System Integration Issues (Cont d) Verification methodologies supporting multi-level design process. Multi-level design models - accuracy and consistency. Multiple design teams are formed to work on specific parts of the design. It s very difficult to develop realistic and comprehensive test benches. ΗΜΥ408 Δ09 FPGA IP Cores & Video.30 Θεοχαρίδης, ΗΜΥ, 2018

31 System Integration Issues (Cont d) Functional and architectural level modeling should be used extensively for system function definition and architectural trade-offs. Interface timing errors between subsystems (IPs) increase dramatically. Experiencing multiple design iterations and/or respins due to functional bugs. Pre-existing IP may need to be constantly redesigned. ΗΜΥ408 Δ09 FPGA IP Cores & Video.31 Θεοχαρίδης, ΗΜΥ, 2018

32 Design Flow for System Design Application spec. Analysis System-level synthesis Verification Software spec. Code generation Hardware spec. System integration Object code ΗΜΥ408 Δ09 FPGA IP Cores & Video.32 Θεοχαρίδης, ΗΜΥ, 2018

33 Design Tasks Definition of system-level design specification (Cbased, HDLs). Design evaluation and exploration. Hardware/software codesign. Co-verification: co-simulation and co-emulation. Debugging and diagnosis. Rapid prototyping. ΗΜΥ408 Δ09 FPGA IP Cores & Video.33 Θεοχαρίδης, ΗΜΥ, 2018

34 Reuse Complex IPs/Cores with an RTL Design Flow RTL Comp. Library RTL Spec RTL/Logic Synthesis How??? Complex Core Lib. Cell-based Library Netlist ΗΜΥ408 Δ09 FPGA IP Cores & Video.34 Θεοχαρίδης, ΗΜΥ, 2018

35 Core-based IP Integration Methodology Complex Core Lib. High-level Spec High-level Synthesis Automatically reuse complex macros/cores Design exploration RTL Comp. Library Cell-based Library RTL Spec RTL/Logic Synthesis Netlist ΗΜΥ408 Δ09 FPGA IP Cores & Video.35 Θεοχαρίδης, ΗΜΥ, 2018

36 How to Reuse a Core? Operating procedure VCR Usage (Interface)??? Cores ΗΜΥ408 Δ09 FPGA IP Cores & Video.36 Θεοχαρίδης, ΗΜΥ, 2018

37 Usable-Function 8-bit addition 16-bit addition A[8] B[8] in1 in2 S0 co, C[0:7] <= A[0:7]+B[0:7] A[16] B[16] in1 in2 S1 S0 C <= A + B co + [8] ci C[8:15] <= A[8:15]+B[8:15]+co co + [8] ci out out C[8] C[16] ΗΜΥ408 Δ09 FPGA IP Cores & Video.37 Θεοχαρίδης, ΗΜΥ, 2018

38 Usable-Function (Cont d) S0 8X8 multiplication CNT<=8; Q<=B; P<=0; A[8] B[8] S1 in1 in2 S2 Q(0)= 1 Q(0)= 0 S3 P <= P + A CNT<> 0 co + [8] ci P & Q >> 1 ; CNT<=CNT-1; out S4 C <= P & Q C[16] ΗΜΥ408 Δ09 FPGA IP Cores & Video.38 Θεοχαρίδης, ΗΜΥ, 2018

39 Usage-based Core Database 8-bit addition Usable Function 1 Control interface 1 8-bit adder Core 8X8 multiplication Usable Function n Control interface n ΗΜΥ408 Δ09 FPGA IP Cores & Video.39 Θεοχαρίδης, ΗΜΥ, 2018

40 Core-based Synthesis Flow High-level Design Spec. Compilation Core Selection and Exploration Allocation, Inference, and Instantiation Of Cores Interface Generation Design Integration RTL Design ΗΜΥ408 Δ09 FPGA IP Cores & Video.40 Θεοχαρίδης, ΗΜΥ, 2018

41 Design Exploration Which IPs/cores I should reuse??? What is the design cost and performance by reusing these IPs/cores??? Core Core Core IP IP IP ΗΜΥ408 Δ09 FPGA IP Cores & Video.41 Θεοχαρίδης, ΗΜΥ, 2018

42 The IP/Core Reuse Story Several years ago semiconductor industry raised the productivity crisis in the forthcoming SoC era. Intuitively, integrate existing designs to form an SoC design can bridge the productivity gap. IP-business and SoC design approaches have been emerged in semiconductor industry. Many ASIC design houses/divisions try to re-packaging their existing designs into IPs/Cores. Many system design houses start to investigate the SoC design methodology. ΗΜΥ408 Δ09 FPGA IP Cores & Video.42 Θεοχαρίδης, ΗΜΥ, 2018

43 Current Status on IP Reuse Many system companies tried IP-reuse but not very successful due to the following reasons: => Complex contract negotiation process => inadequate quality assurance from the IP providers that often results in failed projects => Designers resistance to adopt reuse guideline On the IP business side: => Many so-called 3rd-party IP providers are gone. => A small business venue (417M/1999, 51% revenue are dominated by three big players: ARM, MIPS, and RamBus). ΗΜΥ408 Δ09 FPGA IP Cores & Video.43 Θεοχαρίδης, ΗΜΥ, 2018

44 Designers Perspective on Reuse Should I reuse some existing IPs/cores or just design them starting from scratch? The main goal for IP/core reuse is to minimize the overall design effort and thus speed up the time-to-market. How to justify whether reuse will be benefit to my design project? What s designers main concerns on the reuse practice? => If I can fully control my own destiny, I will reuse some IPs for my design!!! The problem is who can give me such guarantee??? ΗΜΥ408 Δ09 FPGA IP Cores & Video.44 Θεοχαρίδης, ΗΜΥ, 2018

45 Designers Technical Concerns on IP Reuse Is the IP source (provider) reliable? How can I make sure the functional correctness of the IP? How much effort do I have to invest in test-bench development for design verification with reused IP? What if I need to modify part of IP design? What if the final timing is not satisfied due to the IP? What s the risk of the design project due to any possible defect caused by the IP? What s the worst scenario when reuse the IP and what are the damage control plan? ΗΜΥ408 Δ09 FPGA IP Cores & Video.45 Θεοχαρίδης, ΗΜΥ, 2018

46 Designers Concerns on Legacy-Core Development and Reuse Take too much effort to develop a reusable core: => I have my dead-line to meet! => What s my incentive to develop a reusable core! It s difficult to reuse a legacy core, if => the documentation is incomplete (the original core was not developed for the reuse purpose) => the original core designer is gone => the original core has known problems or bugs (it will be much easier to redesign it than reuse it) ΗΜΥ408 Δ09 FPGA IP Cores & Video.46 Θεοχαρίδης, ΗΜΥ, 2018

47 SoC Design Issues Management and culture change Design methodology issues Wide-spread IP reuse and exchange may be a long way to go Most today s IPs are unusable, but IP reuse is necessary for SoC designs IP development strategy for easy-reuse needs to be studied further SoC design methodology needs to be studied further ΗΜΥ408 Δ09 FPGA IP Cores & Video.47 Θεοχαρίδης, ΗΜΥ, 2018

48 Understand SoC and IPs ASICs SoC System Hardware Software Consumer Wireless Set-top box PDA Processors Memories OS Application IOs ΗΜΥ408 Δ09 FPGA IP Cores & Video.48 Θεοχαρίδης, ΗΜΥ, 2018

49 Understand SoC and IPs (Con t) Systems define IPs not IPs define the system!!! From systems point of views, the basic IPs include: => Hardware IPs -> Processor-cores -> Memories -> IOs -> ASICs => Software IPs -> OS -> Application ΗΜΥ408 Δ09 FPGA IP Cores & Video.49 Θεοχαρίδης, ΗΜΥ, 2018

50 Concerns!!! There is no viable RTL market for IP. There just is no business Gary Smith Chief Analyst, Dataquest IP that is designed in at the RTL stage is not successful. To be successful, it has to be designed in at the system level Gary Smith We have spent so much time evaluating purchased IP cores and we have concluded that it would be better use of engineering hours to develop the blocks in-house Steve Shulz, TI Verifying IPs is absolute nightmare. It s really hard. We don t trust anything we get we verify the hell out of everything. IP has no self-life without support. Vig Sherrill, ASIC International ΗΜΥ408 Δ09 FPGA IP Cores & Video.50 Θεοχαρίδης, ΗΜΥ, 2018

51 SoC and IPs (Con t) The quality of IPs and support will be the key to the success of the IP business Need to pay much attention on software IP issues Need application and system design expertise Core-based design is effective on IP/core integration Need to develop a combining platform- and core-based design methodology/environment for system designs ΗΜΥ408 Δ09 FPGA IP Cores & Video.51 Θεοχαρίδης, ΗΜΥ, 2018

52 CORE Generator HDL COREGen Behavioral Simulation Instantiate optimized IP within the HDL code Synthesis Functional Simulation Implementation Timing Simulation Download In-Circuit Verification ΗΜΥ408 Δ09 FPGA IP Cores & Video.52 Θεοχαρίδης, ΗΜΥ, 2018

53 Synthesize, Implement, Download Design Verification HDL COREGen Behavioral Simulation Synthesis Implementation Download Functional Simulation Timing Simulation In-Circuit Verification Synthesize, Implement, and Download the bitstream, similar to the original design flow ΗΜΥ408 Δ09 FPGA IP Cores & Video.53 Θεοχαρίδης, ΗΜΥ, 2018

54 Xilinx CORE Generator List of available IP from or Fully Parameterizable ΗΜΥ408 Δ09 FPGA IP Cores & Video.54 Θεοχαρίδης, ΗΜΥ, 2018

55 Xilinx IP Solutions: Core Gen DSP Functions Math Functions Memory Functions $P Reed Solomon $3GPP Turbo Code $P Viterbi Decoder $P Convolution Encoder $P Interleaver/De-interleaver P LFSR P 1D DCT P DA FIR P MAC P MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 points P FFT - 32 Point P Sine Cosine P Direct Digital Synthesizer P Cascaded Integrator Comb P Bit Correlator P Digital Down Converter IP CENTER P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier Enhancements P Divider P CORDIC Base Functions P Binary Decoder P Two's Complement P Shift Register RAM/FF P Gate modules P Multiplexer functions P Registers, FF & latch based P Adder/Subtractor P Accumulator P Comparator P Binary Counter $ - License Fee, P - Parameterized, S - Project License Available, BOLD Available in the Xilinx Blockset for the System Generator for DSP P Asynchronous FIFO P Block Memory modules P Distributed Memory P Distributed Mem Enhance P Sync FIFO (SRL16) P Sync FIFO (Block RAM) P CAM (SRL16) $P PCI 64/66 $PS PCI 32/33 $P PCI-X 64/66 PCI Networking 8B/10B Encoder/Decoder $ POS-PHY L3 $ POS-PHY L4 $ Flexbus 4 $ RapidIO PHY Layer $S HDLC 1 and 32 channel $S G.711 PCM Cores $S ADPCM 32 & 64 channel ΗΜΥ408 Δ09 FPGA IP Cores & Video.55 Θεοχαρίδης, ΗΜΥ, 2018

56 Core Generator: Summary CORE Generator Advantages Can quickly access and generate existing functions No need to reinvent the wheel and re-design a block if it meets specifications IP is optimized for the specified architecture Disadvantages IP doesn t always do exactly what you are looking for Need to understand signals and parameters and match them to your specification Dealing with black box and have little information on how the function is implemented ΗΜΥ408 Δ09 FPGA IP Cores & Video.56 Θεοχαρίδης, ΗΜΥ, 2018

57 Xilinx Smart-IP Technology Pre-defined placement and routing enhances performance and predictability Relative Placement Fixed Placement I/Os Fixed Placement & Pre-defined Routing Other logic has no effect on the core Performance is independent of: Guarantees I/O and Logic Predictability Guarantees Performance 200 MHz 200 MHz Core Placement Number of Cores Device Size 200 MHz 200 MHz ΗΜΥ408 Δ09 FPGA IP Cores & Video.57 Θεοχαρίδης, ΗΜΥ, 2018

58 On-Chip Verification ChipScope ILA System Diagram Chipscope ILA USER FUNCTION USER FUNCTION Target FPGA with ILA cores ILA ILA PC running ChipScope JTAG Control ILA USER FUNCTION MultiLINX Cable or Parallel Cable III JTAG Connection Target Board ΗΜΥ408 Δ09 FPGA IP Cores & Video.58 Θεοχαρίδης, ΗΜΥ, 2018

59 CoreGenerator Use in lab 4 at your own responsibility/risk! Useful in creating modules such as memory, FIFO queues, custom arithmetic modules, etc. Start by creating a new project in CoreGenerator, or a new CoreGenerator module in Xilinx ISE. Make sure your FPGA specs are fed into the CoreGenerator project properties!!! Once you specify the targeted FPGA, then you can browse through the components. ΗΜΥ408 Δ09 FPGA IP Cores & Video.59 Θεοχαρίδης, ΗΜΥ, 2018

60 Core Generator Start Window ΗΜΥ408 Δ09 FPGA IP Cores & Video.60 Θεοχαρίδης, ΗΜΥ, 2018

61 Project Properties ΗΜΥ408 Δ09 FPGA IP Cores & Video.61 Θεοχαρίδης, ΗΜΥ, 2018

62 IP Blocks ΗΜΥ408 Δ09 FPGA IP Cores & Video.62 Θεοχαρίδης, ΗΜΥ, 2018

63 IP Customizer (Single Port Block Memory) ΗΜΥ408 Δ09 FPGA IP Cores & Video.63 Θεοχαρίδης, ΗΜΥ, 2018

64 Page 2 ΗΜΥ408 Δ09 FPGA IP Cores & Video.64 Θεοχαρίδης, ΗΜΥ, 2018

65 Page 3 ΗΜΥ408 Δ09 FPGA IP Cores & Video.65 Θεοχαρίδης, ΗΜΥ, 2018

66 Page 4 ΗΜΥ408 Δ09 FPGA IP Cores & Video.66 Θεοχαρίδης, ΗΜΥ, 2018

67 Memory Editor ΗΜΥ408 Δ09 FPGA IP Cores & Video.67 Θεοχαρίδης, ΗΜΥ, 2018

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71 ΗΜΥ408 Δ09 FPGA IP Cores & Video.71 Θεοχαρίδης, ΗΜΥ, 2018

72 Supplementary Lecture on Video Handling VGA Controller Basic Video Output Processing ΗΜΥ408 Δ09 FPGA IP Cores & Video.72 Θεοχαρίδης, ΗΜΥ, 2018

73 Dots to a Picture Brain can make this into something recognizable Images from howstuffworks.com ΗΜΥ408 Δ09 FPGA IP Cores & Video.73 Θεοχαρίδης, ΗΜΥ, 2018

74 Many Still Images Video (and movies) are a series of stills If it goes fast enough Hz or more to not see flicker Your brain interprets as moving imagery Electron beam scans across Turned off when Scanning back to the left (horizontal retrace) Scanning to the top (vertical retrace) ΗΜΥ408 Δ09 FPGA IP Cores & Video.74 Θεοχαρίδης, ΗΜΥ, 2018

75 Simple Scanning TV ΗΜΥ408 Δ09 FPGA IP Cores & Video.75 Θεοχαρίδης, ΗΜΥ, 2018

76 Scanning TVs use interlacing Every other scan line is swept per field Two fields per frame (30Hz) Way to make movement less disturbing Computers use progressive scan Whole frame refreshed at once 60Hz or more, 72Hz looks better ΗΜΥ408 Δ09 FPGA IP Cores & Video.76 Θεοχαρίδης, ΗΜΥ, 2018

77 VGA Timing You supply two pulses, hsync and vsync, that let the monitor lock onto timing One hsync per scan line One vsync per frame Image from dell.com ΗΜΥ408 Δ09 FPGA IP Cores & Video.77 Θεοχαρίδης, ΗΜΥ, 2018

78 Horizontal Timing Terms hsync pulse Back porch (left side of display) Active Video Video should be blanked (not sent) at other times Front porch (right side) ΗΜΥ408 Δ09 FPGA IP Cores & Video.78 Θεοχαρίδης, ΗΜΥ, 2018

79 Standards 640 x 480 (60Hz) is VGA You can also try for 800x600 at 60 Hz (40 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly) ΗΜΥ408 Δ09 FPGA IP Cores & Video.79 Θεοχαρίδης, ΗΜΥ, 2018

80 Color Depth Example with Spartan-II Voltage of each of RGB determines color 2-bit color here (4 shades) Turn all on for white ΗΜΥ408 Δ09 FPGA IP Cores & Video.80 Θεοχαρίδης, ΗΜΥ, 2018

81 PC Display Standards Monochrome Display Adapter (MDA) Earliest display system for IBM PCs Text-only 80x25 characters, each character is 9x14 pixels Effective resolution 50 Hz, but pixels not individually addressable IBM provided extra characters in its character set that allowed primitive graphics (boxes, lines, etc.) to be drawn in MDA Hercules Graphics Card Third-party system, adds monochrome graphics to MDA text Color Graphics Adapter (CGA) First mainstream color system for IBM PC Text up to 80x25, graphics range from 640x200 in monochrome to 160x200 in 16 colors Text displayed with lower quality than MDA (8x8 pixels/char) ΗΜΥ408 Δ09 FPGA IP Cores & Video.81 Θεοχαρίδης, ΗΜΥ, 2018

82 PC Display Standards Enhanced Graphics Adapter (EGA) 16 colors out of palette of 64 at 640x350, 80x25 text at 60 Hz Minimum requirement for Windows 3.x Video Graphics Adapter (VGA) Last really accepted standard defined by IBM (consequence of IBM losing control of the PC ) 256 colors at 320x200, 16 colors at 640x480 Not 256 colors at 640x480, even though that s what most people accept when they say VGA Resolution Super VGA and other formats Much less well-defined VESA standards developed for software compatibility between different cards ΗΜΥ408 Δ09 FPGA IP Cores & Video.82 Θεοχαρίδης, ΗΜΥ, 2018

83 ΗΜΥ408 Δ09 FPGA IP Cores & Video.83 Θεοχαρίδης, ΗΜΥ, 2018

84 ΗΜΥ408 Δ09 FPGA IP Cores & Video.84 Θεοχαρίδης, ΗΜΥ, 2018

85 Back porch Front porch Back porch ΗΜΥ408 Δ09 FPGA IP Cores & Video.85 Θεοχαρίδης, ΗΜΥ, 2018

86 Horizontal Timing HS Horizontal Video BP FP SP Horizontal Scan Lines Pixel clock = 25 MHz Pixel time = 0.04 µs Horizontal video = 640 pixels x 0.04 µs = µs Back porch, BP = 16 pixels x 0.04 µs = 0.64 µs Front porch, FP = 16 pixels x 0.04 µs = 0.64 µs Sync pulse, SP = 128 pixels x 0.04 µs = 5.12.µs Horizontal Scan Lines = SP + BP + HV + FP = = 800 pixels x 0.04 µs = 32 µs 1/60 Hz = ms / 32 µs = 521 horizontal scan lines per frame ΗΜΥ408 Δ09 FPGA IP Cores & Video.86 Θεοχαρίδης, ΗΜΥ, 2018

87 Vertical Timing Vertical Video BP FP VS SP Vertical Scan Lines Pixel clock = 25 MHz Horizontal scan time = 32 µs Vertical video = 480 lines x 32 µs = ms Back porch, BP = 29 lines x 32 µs = ms Front porch, FP = 10 lines x 32 µs = ms Sync pulse, SP = 2 lines x 32 µs = ms Vertical Scan Lines = SP + BP + VV + FP = = 521 lines x 32 µs = ms 1/60 Hz = ms ΗΜΥ408 Δ09 FPGA IP Cores & Video.87 Θεοχαρίδης, ΗΜΥ, 2018

88 How to Make the VGA Work! Basically, driving a VGA display involves doing the video decoder operation in reverse. Start with a digital representation of the image Hardware (video DAC) converts digital pixels into analog voltages used by the monitor Different display standards have used either analog or digital signals in the past Your hardware has to drive the control signals to the display and provide pixel values at the right rate DAC just does conversion ΗΜΥ408 Δ09 FPGA IP Cores & Video.88 Θεοχαρίδης, ΗΜΥ, 2018

89 VGA Timing ΗΜΥ408 Δ09 FPGA IP Cores & Video.89 Θεοχαρίδης, ΗΜΥ, 2018

90 VGA Triple DAC Converts digital pixel data to VGA outputs ΗΜΥ408 Δ09 FPGA IP Cores & Video.90 Θεοχαρίδης, ΗΜΥ, 2018

91 XSGA Video DAC ΗΜΥ408 Δ09 FPGA IP Cores & Video.91 Θεοχαρίδης, ΗΜΥ, 2018

92 General Operation Operation See datasheet and XUP manual* for supported modes You are responsible for managing the timing of the VGA signal Clock rate/time per line will give you the max number of pixels/line you can drive Number of lines on the screen determined by ratio of time/frame and time/screen FPGA has to drive HSYNC and VSYNC signals directly ΗΜΥ408 Δ09 FPGA IP Cores & Video.92 Θεοχαρίδης, ΗΜΥ, 2018

93 Driving the VGA Chip CLK used to latch input registers 24-bit pixel input bus carries color of each pixel BLANK* signal specifies blanking interval Assert this, don t just drive a color that should be black SYNC* inserts sync pulse on I OG output Does not override any other data Use only during blanking interval ΗΜΥ408 Δ09 FPGA IP Cores & Video.93 Θεοχαρίδης, ΗΜΥ, 2018

94 Making VGA Work 1. You may start with say an 8 bit per pixel image (see below). 2. Generate an image in the appropriate 8-bit format For video capture, you could use an 8-bit RGB spectrum, with 3 bits of red, 3 of green, and 2 of blue (human eyes are less sensitive to blue) Previously, students reported they d found routines to convert an RGB image into 8-bit format and generate the optimal palette for that image 3. Drive the image pixels to the triple DAC with appropriate timing signals ΗΜΥ408 Δ09 FPGA IP Cores & Video.94 Θεοχαρίδης, ΗΜΥ, 2018

95 Advice / Experience A number of course projects had working 640x480 video in 256 colors working for their final project, so that path seems pretty stable Would recommend against going to higher resolutions/color depths for your projects You only have ~250KB of memory available presently, and one frame of 640x480x256 video takes 300 KB Maximum clock rate for the FMS3818KRC is 180 MHz, which allows about 10x more pixels than 640x480, but handling that clock rate is out of our system Higher color depths not supported by this chip RAM not present on chip as in past semesters ΗΜΥ408 Δ09 FPGA IP Cores & Video.95 Θεοχαρίδης, ΗΜΥ, 2018

96 Reference Designs m SEARCH THE INTERNET GOOGLE IS YOUR FRIEND ΗΜΥ408 Δ09 FPGA IP Cores & Video.96 Θεοχαρίδης, ΗΜΥ, 2018

97 VGA UCF Files (MAY NOT BE THE SAME AS YOUR SPARTAN BOARD CHECK YOUR OWN UCF FILES) NET "VGA_COMP_SYNCH_N" LOC = "G12" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_HSYNCH" LOC = "B8" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLANK_N" LOC = "A8" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<0>" LOC = "D15" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<1>" LOC = "E15" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<2>" LOC = "H15" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<3>" LOC = "J15" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<4>" LOC = "C13" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<5>" LOC = "D13" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<6>" LOC = "D14" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_BLUE<7>" LOC = "E14" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<0>" LOC = "G10" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<1>" LOC = "E10" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<2>" LOC = "D10" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<3>" LOC = "D8" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<4>" LOC = "C8" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<5>" LOC = "H11" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<6>" LOC = "G11" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_GREEN<7>" LOC = "E11" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_PIXEL_CLOCK" LOC = "H12" IOSTANDARD = LVTTL DRIVE = 12 SLEW = FAST ; NET "VGA_OUT_RED<0>" LOC = "G8" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<1>" LOC = "H9" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<2>" LOC = "G9" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<3>" LOC = "F9" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<4>" LOC = "F10" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<5>" LOC = "D7" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<6>" LOC = "C7" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_OUT_RED<7>" LOC = "H10" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; NET "VGA_VSYNCH" LOC = "D11" IOSTANDARD = LVTTL DRIVE = 12 SLEW = SLOW ; ΗΜΥ408 Δ09 FPGA IP Cores & Video.97 Θεοχαρίδης, ΗΜΥ, 2018

98 VGA Timing ΗΜΥ408 Δ09 FPGA IP Cores & Video.98 Θεοχαρίδης, ΗΜΥ, 2018

99 VGA Generation ΗΜΥ408 Δ09 FPGA IP Cores & Video.99 Θεοχαρίδης, ΗΜΥ, 2018

100 Example ΗΜΥ408 Δ09 FPGA IP Cores & Video.100 Θεοχαρίδης, ΗΜΥ, 2018

101 Example ΗΜΥ408 Δ09 FPGA IP Cores & Video.101 Θεοχαρίδης, ΗΜΥ, 2018

102 Links VGA Timing Code (more complex than you want) Interesting Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press (Really Good VHDL) ΗΜΥ408 Δ09 FPGA IP Cores & Video.102 Θεοχαρίδης, ΗΜΥ, 2018