Improvement of Design Issues in Sequential Logic Circuit with Different CMOS Design Techniques

Transcription

1 Improvement of Deign Iue in Sequential Logic Circuit with Different CMOS Deign Technique Pradeep Kumar Sharma 1 *, Bhanupriya Bhargava1 and Shyam kahe 2 1 Reearch Scholar of Electronic & Communication Engineering Department 2 ociate Profeor of Electronic & Communication Engineering Department btract Thi paper preent the low power high performance D flip flop uing with gate diffuion input (GDI) technique. Here we alo implemented D flip flop uing different CMOS logic deign uch a tranmiion gate, pa tranitor logic (PTL) and gate diffuion input (GDI) logic and hown the comparable tudy on thee CMOS deign technique. Thee different CMOS logic deign technique are alo compared with repect to the layout area, number of tranitor, delay, and power conumption. ll the reult of thi paper i verified on cadence virtuoo tool uing pecter at 45nm technology with upply voltage 0.7V. Keyword CMOS logic tyle; Pa tranitor logic; tranmiion gate; Gate Diffuion input( GDI) 1. Introduction Hitorically, peed wa the performance metric parameter ued by the VLSI deigner. Integrated chip uch a digital proceor, microproceor, DSP (Digital Signal Proceor), SIC (pplication Specific IC), etc. thu ued high gain in term of performance and ilicon area. mall area and high performance are the main important factor which affect gain highly [1], [2] With the continuouly increaing chip complexity and number of tranitor in a chip, power conumption i growing a well. Higher power conumption, raie chip temperature and directly affect battery life in portable device a it caue more current to be withdrawn from the power upply. High temperature afflict circuit operation and reliability o require more complicated cooling and packaging technique [3] [4]. The wide ue of equential logic and memory torage ytem in modern electronic reult in the implementation of low power and high peed deign of baic memory element. One of the mot important baic memory element i the D flip-flop (DFF) [5]. Hence novel architecture uch a CMOS Tranmiion Gate (TG), Pa-Tranitor Logic (PTL), Complementary Pa-tranitor Logic (CPL) [6] and Gate Diffuion Input (GDI) [7] are propoed to meet the requirement. Each deign tyle of the propoed CMOS logic ha it fair advantage and diadvantage. Tranmiion gate i one of the mot important tructure in CMOS integrated circuit, upporting a logic reduction, witch function and efficient layout [8]. Gate Diffuion Input i a low power deign that reduce tranitor count. But the main problem with the GDI i that it require twin well CMOS or ilicon on inulator (SOI) proce for fabrication [9]. Thu GDI chip are cotlier comparatively. Thee logic along with their Hybrid are thu ued to deign D flip flop circuit [10]. 2. CMOS Deign Implementation of D Flip-Flop Three different deign of D flip-flop in CMOS logic are preented in thi ection. Here the propoed D flip-flop i combine a pair of mater and lave D latch. 2.1 Deign D Flip Flop baed on Pa Tranitor Technique IN Figure.1 Baic NMOS Pa Tranitor logic It ha been demontrated that CMOS patranitor baed logic can often reult in high-peed and high-denity circuit. It reduce the count of tranitor ued to create different logic gate, by eliminating extra tranitor. Tranitor are ued a witche to pa logic level between node of a circuit, rather than a witche connected on to provide voltage. B 87

2 Figure.2 D flip-flop uing Pa tranitor Thi reduce the amount of active device, but ha the diadvantage that the ditinction of the voltage between high and low logic level decreae at each tage [11]. Each of the witche can be implemented either by a ingle NMOS tranitor Fig.1 how the baic ymbol of pa tranitor. In Fig.2 ue pa tranitor logic (PTL) and inverter for the mater-lave latche [12]. The two chained inverter are in memory tate when the PMOS loop tranitor i on, that i when clk= 0. Other two chain inverter on the right hand ide act in the oppoite way. The flip-flop change it tate during the falling edge of the clock. 2.2 Deign D Flip Flop baed on Tranmiion Gate Technique IN Figure.3 Baic ymbol of Tranmiion gate OUT BR P1 P2 P3 P4 BR a PMOS tranitor and NMOS tranitor [13]. Each Tranitor turn on or off alternately with alternate biaing of the control gate. The Fig.3 how the baic ymbol of tranmiion gate. Fig.4 how the D flip flop uing tranmiion gate and inverter [14]. t the negative edge of the clock, tranmiion gate T1 and T4 are ON and tranmiion gate T2 and T3 are OFF. During now the lave maintain a loop through two inverter P3, P4 and T4. Thi time previou triggered value from Din i keep within the lave. t the ame time mater latche next tate however a T3 i OFF it not paed to lave. During the poitive clock edge T2 and T3 are turned ON and the new latched value pae to lave through the loop of two inverter P1, P2 and T Deign D Flip Flop baed on GDI Technique The GDI cell hown in Fig.5 wa propoed by Morgenhtein et. al. [15]. It a geniu deign which i very flexible for digital circuit. Thi technique optimize the power diipation and alo reduce tranitor count. The advantage of GDI technique two-tranitor implementation of advanced logic function and in-cell wing retoration under certain operational condition, are unique within exiting low-power deign technique. Fig.6 repreent the mater-lave connection of two GDI D-latche. During thi the body gate are reponible for the tate of the circuit. Thee gate are verified by the clock (clk) ignal and make two different path. One for tranparent tate of the latch,when the clock i low and the ignal are propagating through PMOS tranitor.the other one i for the holding tate of the latch,when the clock ignal i high and internal value are maintained due to conduction of the NMOS tranitor[16]. The inverter are reponible for maintaining the complementary value of the internal ignal and the circuit output. T1 T 3 T2 T4 Figure.4 D flip-flop uing tranmiion gate tranmiion gate i one of the mot important tructure in CMOS integrated circuit, upporting a witch function, logic reduction, and efficient layout. Thi olid-tate witch i compried of 88

3 P G OUT=G P+GN N Figure.5 Baic GDI cell Figure.7 Input Output waveform of D Flip Flop Figure.6 D flip-flop uing GDI gate 3. SIMULTION ND RESULTS In thi ection, the performance of the three different deign of D flip-flop have been implemented and imulated on cadence virtuoo tool on 45nm CMOS Technology. The table how the reult of three different deign tyle of CMOS technology and alo how the comparion between them. Thee comparion are baed on Delay, number of tranitor count, average power and leakage power of the different deign tyle. Table 1 how the imulation reult of the PTL, Tranmiion Gate, and GDI CMOS deign. BR Figure.8 ctive Power of PTL Baed D Flip-Flop Figure.9 ctive Power of Tranmiion Gate Baed D Flip-Flop 89

4 Figure.10 ctive Power of GDI Baed D Flip- Flop. Table 1 Comparion reult of propoed CMOS technique DFF Deign uing PSS Tranitor logic Tranmii on Gate Gate Diffuion Input (GDI) Comparion reult of propoed CMOS technique No. Of Tran itor count Concluion Delay 21.93n 20.51p 14.68n vg. Po wer nw nw nw Leak age Powe r nw pw 10.1p w In thi paper three CMOS implementation of DFF uing pa tranitor, tranmiion gate and GDI gate are propoed. Thi paper alo decribe the comparative analyi on pa tranitor logic, tranmiion gate and gate diffuion technique. oberved from the dicuion about the D Flip Flop that variou deign have their own advantage and diadvantage in term of area, delay and power conumption. Here the pa tranitor logic baed DFF required minimum tranitor (12) a compared to other CMOS tructure.the deign of DFF with tranmiion gate give the minimum delay (20.51p) with repect to PTL and GDI baed technique. The minimum average power i ued in GDI baed DFF approximate 37.56nw which i ued to deign low power circuit. ll the parameter tudied and verified on cadence virtuoo tool uing pecter imulator at 45nm CMOS technology with 0.7v. 5. cknowledgment Thi work wa upported by ITM Gwalior, with collaboration Cadence Deign Sytem, Bangalore. 6. Reference [1].Bazzazi and B. Ekafi, Deign and Implementation of Full dder Cell with the GDI Technique Baed on 0.18μm CMOS Technology international multiconference of engineer and computer cientit, Vol.2, march [2] Shyam kahe, Suhil Bhuhan, Sanjay Sharma, High Denity and Low Leakage Current Baed 5T SRM Cell Uing 45 nm Technology, Romanian journal of information cience and technology,vol.15,pp ,2012. [3] Manih Dev Singh, Shyam kahe,sanjay Sharma, Leakage power reduction technique of 45 nm tatic random acce memory (SRM) cell, International Journal of the Phyical Science,Vol. 6, pp , December [4] li Peiravi and2mohammad yaei, Novel Circuit Deign Technique to Minimize Sleep Mode Power Conumption due to Leakage Power in the Sub- 100nm Wide Gate in CMOS Technology journal of World pplied Science,pp , [5] S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuit: nalyi and Deign, Third Edition, Tata McGraw-Hill Edition, pp ,2003. [6] Farhad Moradi, Dag.T. Wiland, Hamid Mahmoodi,Snorre unet,tuan Vu Cao, li Peiravi, Ultra Low Power Full dder Topologie Circuit and Sytem,. ISCS IEEE conference,pp ,2009. [7] Bori D,ndreev,Edward Titlebaum, E,G.Friedman,E.G., Tapered Tranmiion Gate Chain for improved carry propagation, IEEE conference on circuit and ytem,mwscs,vol.3,pp [8] J. Wang, S. Fang, and W. Feng, New efficient deign for XOR and XNOR function on the tranitor level, IEEE J. Solid-State Circuit, vol. 29, pp ,Jul. 1994,. [9] Saradindu Panda,.Banerjee, B.Maji, Dr..K.Mukhopadhyay, Power and Delay Comparion in between Different type of Full dder Circuit International Journal of dvanced Reearch in Electrical, Electronic and Intrumentation Engineering, Vol. 1, September [10] lexander Chatzigeorgiou, Spiridon Nikolaidi and Ioanni Toukala, timing analyi of pa tranitor and CPL gate,

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