IN HIGH-SPEED digital systems, the high-speed digital

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1 908 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Spread Spectrum Clock Generator With Delay Cell Array to Reduce Electromagnetic Interference Jonghoon Kim, Dong Gun Kam, Pil Jung Jun, and Joungho Kim Abstract In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-µm CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz. Index Terms Electromagnetic interference (EMI), spread spectrum clock (SSC). I. INTRODUCTION IN HIGH-SPEED digital systems, the high-speed digital clock drivers and associated circuits generate most of the electromagnetic interference (EMI) problems in the system. This is because of the periodic nature of signal with the highest frequency and fast transition time. Its energy is concentrated in narrow bands near the harmonic frequencies [1]. To reduce the EMI from the system clock drivers and associated circuits, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been introduced [2] and [3]. More recently, the SSC techniques have been adapted to some commercial electronic products, such as a personal computer, offering considerable suppression of the EMI [4] and [5]. The conventional SSC is generated by adding intentional period jitter to a fixed period clock (FPC) within the timing margin of the system, as shown in Fig. 1(a). The shape of the imposed period jitter, as shown in Fig. 1(b), is defined as a modulation profile. Fig. 1(c) shows the attenuation (A db ) of spectrum, viz. Manuscript received March 12, 2004; revised August 1, J. Kim is with the Module Design Team, Memory Division, Device Solution Network, Samsung Electronics Company Ltd., Hwasung-city, Kyeonggi-do , Korea ( jh9.kim@samsung.com). D. G. Kam and J. Kim are with the Terahertz Interconnection and Package Laboratory, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Yuseong-gu, Daejeon , Korea ( teralab@ee.kaist.ac.kr). P. J. Jun is with the Computer System R&D Division, Samsung Electronics Company Ltd., Hwasung-city, Kyeonggi-do , Korea. Digital Object Identifier /TEMC the suppressed EMI by virtue of the SSC. There are various modulation profiles, including random pulses, sinusoidal, triangular, and SSC generator (SSCG) modulation profiles [2], [3], [6], [7]. Among the modulation profiles, we found that the triangular modulation profile [see Fig. 1(b)] has the maximum A db from numerical analysis. Therefore, our study is focused on the SSCG using the triangular modulation profile in this paper. When the triangular modulation profile is used, A db can be estimated by [6] ( ) δ n f0 Attenuation = A db 10 log 10. (1) In the region between the cut-off frequency (f m /δ) and the overlap frequency (f 0 /δ),a db is directly proportional to the peak deviation (δ) and the harmonic frequency (n f 0 ), and inversely proportional to the modulation frequency (f m ). The peak deviation (δ) is equal to the maximum period jitter ( T 0 ) divided by the fundamental period T 0, and the modulation frequency f m is the reciprocal of the modulation period (T m = K T 0 ). To achieve the maximum attenuation, the peak deviation (δ) should be increased, and the modulation frequency (f m ) should be decreased. However, (1) has a critical assumption that the resolution bandwidth (RBW) of the spectrum analyzer (EMC measurement receiver) is 0 Hz. Generally, the RBW of the EMC receiver is about 120 khz. Therefore, (1) is valid when the modulation frequency (f m ) is larger than the RBW of the EMC receiver. In the measured example, f m =50kHz was used, which is less than the 120-kHz RBW. The results show that reduction is possible even for f m < RBW as long as the majority of the FM spectrum is attenuated outside the receiver pass-band at any given tune frequency. If we consider the measurement bandwidth, the optimal modulation profile for SSC becomes the SSCG modulation profile instead of the triangular modulation profile [3]. The deviation from ideal timing of a clock is called jitter. It comprises both a deterministic and a random component. It can be classified into a period jitter or an edge jitter, depending on the timing reference from which it is defined. As shown in Fig. 2, the period jitter is defined as a deviation of a period at each clock cycle from an ideal fixed period. In contrast, the edge jitter is defined as a deviation of a transition edge at each clock cycle from an ideal fixed clock transition edge position. According to this definition, the period jitter is equal to the difference of successive edge jitters as shown in (2), and the edge jitter is equal to the summation of the period jitter as follows in (3): T PJ(k) = T EJ(k) T EJ(k 1) (2) T EJ(k) = f m k T PJ(n). (3) n= /$ IEEE

2 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 909 Fig. 1. Principle of SSC. (a) The SSC is generated by intentional period jitter while preserving the timing margin. Because the SSC has a triangular modulation profile. (b) The spectrum at the harmonics is attenuated as shown in (c). Fig. 2. Period jitter and edge jitter representation for SSC. The period jitter is the difference between the period of every clock cycle and the fundamental period (T 0 ). The edge jitter is the difference between the transition edge of every clock cycle and the ideal position. Fig. 3. Components of jitter. Period jitter and edge jitter are composed of deterministic jitter and random jitter. The deterministic jitter is composed of the SSC jitter and unintentional jitter. An SSCG is realized by adding either period jitter or random jitter to a FPC within the timing margin of the system. In addition to the intentionally added jitter, that is, the SSC jitter, there is also an unintentional jitter and a random jitter, as shown in Fig. 3. The unintentional jitter results from crosstalk, simultaneous switching noise (SSN), EMI, and design errors. If the SSCG is carefully designed, the unintentional jitter can be reduced to be negligible, but the random jitter still exists due to thermal noise, shot noise, and flicker noise. This random jitter poses critical limit on the performance of the conventional SSCG based on modulation of the period jitter of the PLL. Most conventional SSCGs have been implemented using a phase locked loop (PLL) controlling the period jitter rather than the edge jitter [4], [5], [8] [10]. As shown in Fig. 4, the SSC period jitter is intentionally added to a FPC by using a programmable counter and a voltage-controlled

3 910 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Fig. 4. Principle of SSCG with PLL. Using a programmable counter and a VCO, most of the SSCG is implemented [10]. Fig. 5. Decrement of attenuation due to random period jitter of SSCG with PLL. Due to random period jitter of SSCG with PLL, the attenuation of spectrum is decreased. Fig. 6. Proposed SSCG with DCA. The SSCG with DCA is composed of DCA and DCA controller. The DCA has N numbers of delay cell. The delay cell is composed of a latch and an inverter with controllable propagation delay. oscillator (VCO). However, the conventional SSCG with PLL has two critical problems, namely: 1) difficulty of implementation and 2) decrement of A db due to random period jitter. As clock frequency increases, the SSC period jitter must be more finely controlled. If the SSC period jitter to be controlled becomes smaller than the random period jitter, implementation of the SSCG with a PLL becomes difficult. Furthermore, in these circumstances, A db also decreases as shown in Fig. 5. In the SSCG, another alternative approach is controlling the edge jitter. In general, the maximum edge jitter is considerably larger than the fundamental period. A higher peak deviation and

4 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 911 Fig. 7. Operation of delay cell. Clock C n 1 is inverted and propagated to C n with some propagation delay shown as 1.IfQ n is low, Q n =0, the propagation delay between C n 1 and C n is D n shown as 2.IfQ n is high, Q n =1, the propagation delay is D n + D n shown as 3.IfC n is high shown as 4, Q n +1 is transferred to Q n shown as 5. The SSC is generated using the edge jitter resulting from the additional propagation delay D n. a lower modulation frequency achieve higher A db. However, in the previous study, the triangular modulation profile has not been used in controlling the edge jitter [11] [13]. Furthermore, the maximum edge jitter of the conventional SSCG has been smaller than the fundamental period. Therefore, the attenuation of the EMI has been inadequate. In this paper, an SSCG with a delay cell array (DCA) is proposed to control the edge jitter with a triangular modulation profile and maximize the attenuation of the EMI in the SSCG. The proposed SSCG with DCA is more robust in that it is less affected by the random jitter. It is clearly demonstrated by measurement and simulation that the proposed SSCG with DCA has a more effective attenuation of the EMI and can be more easily implemented than the conventional SSCG with PLL. Furthermore, because the proposed SSCG with DCA uses a triangular modulation profile, it has greater effective attenuation than a conventional SSCG with controlled edge jitter. The proposed SSCG with DCA was implemented on a chip using a 0.35-µm CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz. II. PROPOSED SSCG WITH DCA The proposed SSCG is composed of a DCA and a DCA controller, as shown in Fig. 6. The DCA has N delay cells, and each delay cell is composed of a latch and an inverter. The propagation delay at each cell is controlled by the latch output Q. Hence, depending on the status of QsontheN cells, the propagation delay of each clock transition will be different, resulting in the controlled edge jitter. Fig. 7 shows the operation of a delay cell. The clock signal is transferred to the next delay cell with a propagation delay dependent on the status of Q. The propagation delay at the nth delay cell, PD n is represented in (4). The additional propagation delay ( D n ) is the difference between two propagation delays according to the status of Q n and causes the edge jitter. The SSC is constructed using this edge jitter PD n = D n + Q n D n. (4) The total propagation delay through the DCA (PD DCA ), which is represented in (5), is composed of constant term, as given by (6), and edge jitter term, as given by (7). Because the constant term is always independent of the status of Q n, it does Fig. 8. SSC edge jitter and SSC period jitter of the proposed SSCG with DCA. The additional propagation delay ( D n ) of every delay cell is designed as shown in (a), the SSC edge jitter is determined as shown in (b), and the SSC period jitter is extracted as shown in (c). If the additional propagation delay has a triangular profile, the modulation profile of the SSCG with DCA is triangular. not affect the edge jitter. The SSC is created by the edge jitter that depends on Q n N N N PD DCA = PD n = (D n )+ (Q n D n ) (5) PD CONST = T EJ = n=1 n=1 n=1 N (D n ) (6) n=1 N (Q n D n ). (7) n=1

5 912 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Fig. 9. (a) Period jitter and the (b) edge jitter of SSC with triangular modulation profile. The maximum period jitter is δ T 0. The maximum edge jitter is δ T m /8. Generally, the maximum edge jitter is larger than the fundamental period and the maximum period jitter. Q n is transferred from a delay cell to the previous delay cell, as shown in Fig. 7. For normal operation, the status of all Q maintain 0 (low state), and in every clock transition edge, Q is charged with 1 (high state) one by one from a delay cell to the previous delay cell. After every cell is charged with 1 (high state), charging with 0 (low state) will be repeated again. The propagation delay of the kth transition edge of a FPC through the DCA is represented by equation (8) at the bottom of the page. Therefore, the edge jitter is as shown in (9) and the period jitter is as shown in (10) at the bottom of the page. If the additional propagation delay ( D n ) of each delay cell is designed as Fig. 8(a), the edge jitter is determined as shown in Fig. 8(b), and the period jitter is extracted as shown in Fig. 8(c) and has a triangular modulation profile. Therefore, for the implementation of an SSC with a triangular modulation profile using the proposed SSCG with DCA, the additional propagation delay ( D n ) should be designed as shown in Fig. 8(a). The proposed SSCG with the DCA with a triangular modulation profile can be implemented as shown in Fig. 8. The profile of the period jitter is called the modulation profile. For an SSC with a triangular modulation profile, the period jitter and the edge jitter are as represented in Fig. 9. The maximum period jitter is determined by (11) and the maximum edge jitter is determined by (12). For example, supposing the fundamental frequency (f 0 ) is 100 MHz, the modulation frequency (f m ) is 50 khz, and peak deviation (δ) is 0.01 (1%), the fundamental period (T 0 ) is 10 ns, the maximum period jitter is 100 ps, and the maximum edge jitter is 25 ns. The maximum edge jitter is larger than the fundamental period and the maximum period jitter (please see the equation at the bottom of the page) Maximum Period Jitter = max( T PJ(k) )= T 0 = δ T 0 Maximum Edge Jitter = max( T EJ(k) )= δ T m 8 (11). (12) PD DCA(k) = PD CONST + T EJ(k) T EJ(1) D N T EJ(2) D N 1 + D N T EJ(3) D N 2 + D N 1 + D N T EJ(N ) D 1 + D D N 2 + D N 1 + D N T EJ(k) = T EJ(N +1) = D 1 + D D N 2 + D N 1 T EJ(N +2) D 1 + D D N 2 T EJ(2N 2) D 1 + D 2 T EJ(2N 1) D 1 T EJ(2N ) 0 T PJ(1) D N T PJ(2) D N 1 T PJ(3) D N 2 T PJ(N ) D 1 T PJ(k) = T EJ(k) T EJ(k 1) = T PJ(N +1) = D N T PJ(N +2) D N 1 T PJ(2N 2) D 3 T PJ(2N 1) D 2 T PJ(2N ) D 1 (8) (9) (10)

6 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 913 Fig. 10. Principles of the conventional SSCG with PLL and the proposed SSCG with DCA. For the generation of SSC, both the edge jitter and the period jitter can be controlled. The conventional SSCG with PLL is implemented by the SSC period jitter ( T PJ(k ) ), as shown in (a). The proposed SSCG with DCA is implemented by the SSC edge jitter ( T EJ(k ) ), as shown in (b). The relation between the SSC period jitter and the SSC edge jitter is representated by (2) and (3). Fig. 11. Effects of the random period jitter in SSCG with PLL and the random edge jitter in SSCG with DCA. The random period jitter in the right figure and the random edge jitter in the left figure have Gaussian distribution. III. COMPARISON OF AN SSCG WITH DCA AND AN SSCG WITH PLL In this paper, the proposed SSCG with DCA is compared with the conventional SSCG with PLL. The conventional SSCG with PLL is implemented by controlling the SSC period jitter as shown in Fig. 10(a), and the proposed SSCG with DCA is implemented by controlling the SSC edge jitter as shown in Fig. 10(b). If random jitter does not exist, the operation and the SSC from the SSCG with DCA will be same as the SSC from the SSCG with PLL. However, because of the difference between the random period jitter in the SSCG with PLL and the random edge jitter in the SSCG with DCA, the SSC from the SSCG with DCA is quite different from the SSC from the SSCG with PLL. Effects of the random period jitter in the SSCG with PLL and the random edge jitter in the SSCG with DCA were demonstrated using the numerical simulation in terms of attenuation of the EMI. The period and edge jitter of the SSCG with PLL and the SSCG with DCA are shown in Fig. 11, respectively. The random period jitter of the SSCG with PLL is on the right of Fig. 11, and the random edge jitter of the SSCG with DCA is on the left of Fig. 11. We assumed that both random jitters with Gaussian distribution, as shown on center of Fig. 11, are the same. The level of the random jitter used for this simulation was determined by assumption, so the used random jitter can be different from the circuits currently in practice. The random period jitter that results in the random edge jitter of the SSCG with DCA is larger than the random period

7 914 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Fig. 12. Edge jitter and the period jitter from Fig. 11. (a) The edge jitter of the SSCG with DCA, including the SSC edge jitter and the random edge jitter. For (a), the period jitter of the SSCG with DCA is represented by (c). (d) The period jitter of the SSCG with PLL, including the SSC period jitter and the random period jitter. For (d), the edge jitter of the SSCG with PLL is represented by (b). Fig. 13. Attenuation from the SSCG with PLL and the SSCG with DCA. The attenuation from the SSCG with PLL is less than that from the SSCG without random jitter. However, the attenuation from the SSCG with DCA is larger than the attenuation from the SSCG with PLL and is similar to the attenuation from the SSCG without the random jitter. jitter of the SSCG with PLL. Because 25 ns of the maximum edge jitter in Fig. 12(c) is much larger than 10 ps of the maximum period jitter in Fig. 12(a), the proposed SSCG with DCA is easier to implement than the conventional SSCG with PLL. The A db of the SSCG with PLL decreased as shown Fig. 13. This problem is called the decrement of A db. However, the proposed SSCG with DCA has greater effective attenuation than the conventional SSCG with PLL. Although the SSCG with DCA has the larger period jitter, the A db of the SSCG with DCA is larger than the A db of the SSCG with PLL and is comparable to the A db of the SSCG without random jitter. The decreased A db is caused by the huge amount of random edge jitter in the SSCG with PLL. The crucial problematic jitters

8 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 915 Fig. 14. Random edge jitter, cause of decremented of attenuation. The random edge jitter that is the cumulative summation of the random period jitter of the SSCG with PLL is larger than the random edge jitter of the SSCG with DCA. Fig. 15. Block diagram of the implemented SSCG with DCA. The inverter with controllable propagation delay is designed as shown in (a). The number of delay cells is 200. The size of MOS transistor is not optimized. For more simplified circuit diagram, a multiplexer, instead of both a counter and a T flip-flop, isusedfor the DCA controller, as shown in Fig. 6. are random period jitter in the SSCG with PLL and random edge jitter in the SSCG with DCA. Because the random edge jitter is the cumulative summation of the random period jitter, the random edge jitter resulting from random period jitter of the SSCG with PLL is much larger than the random edge jitter of the SSCG with DCA, as shown in Fig. 14. Therefore, the proposed SSCG with DCA has more effective attenuation than the conventional SSCG with PLL. If the clock frequency is increased further, the maximum SSC period jitter of the SSCG with PLL becomes comparable

9 916 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Fig. 16. Implementation of integrated circuit (IC) chip for the proposed SSCG with DCA. Photograph of fabricated IC chip is shown in (a). The IC chip was fabricated using 1-poly, 3-metal, and 0.35-µm CMOS process, with 5 5 mm chip size. The IC chip was packaged (208 PQFP) as shown in (b). The architecture of the implemented SSCG is represented in (c). The size of the implemented SSCG with DCA is µm. The power consumption is approximately 120 mw for 200 delay cells at 100-MHz clock frequency. The total on-chip decoupling capacitance is approximately 1 nf. Fig. 17. Simulated edge jitter and simulated period jitter of the implemented SSCG with DCA. The (a) edge jitter and the (b) period jitter are extracted from simulated SSC waveform.

10 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 917 Fig. 18. Simulated spectra of the FPC and the SSC from the implemented SSCG with DCA. The voltage spectrum is attenuated approximately 10-dB from 120 to 110-dB µv at 500 MHz. This attenuation means a similar reduction of EMI. Fig. 19. Test PCB for measurements of jitter and EMI from the implemented SSCG with DCA. The FPC of approximately 100 MHz is generated using a VCO (Minicircuits POS-150). For the measurement of EMI, a microstrip line was used. is much larger than the random edge jitter of the SSCG with DCA, the proposed SSCG with DCA has more attenuation than the conventional SSCG with PLL. Fig. 20. Measurement set-up for jitter of the implemented SSCG with DCA. The power supply generates the 3 V for the implemented IC chip and the 12 V for the VCO. For inspection of the test PCB, an Agilent E7403A spectrum analyzer was used. The SSC waveform was measured using the single-shot technique of the Tektronix TDS7403 oscilloscope. This oscilloscope has 50-ps sampling time and 8-MB memory. Using the measured SSC waveform, the edge jitter and the period jitter were extracted. to its random period jitter. If the maximum SSC edge jitter is much larger than the SSC period jitter, as well as the random edge jitter, the proposed SSCG with DCA can be more easily implemented than the conventional SSCG with PLL. In addition, because the random edge jitter, which results from the accumulated random period jitters of the SSCG with PLL, IV. MEASUREMENT OF JITTER AND EMI The block diagram of the proposed SSCG with DCA is shown in Fig. 15. The fabricated IC chip, package, and architecture are shown in Fig. 16. The number of delay cells is 200. The operating fundamental frequency is approximately 100 MHz. The IC chip was fabricated using 1- poly, 3-metal, and 0.35-µm CMOS process, with 5 5mm die size. The size of the implemented SSCG with DCA is µm. The power consumption is approximately 120 mw for the 200 delay cells at 100-MHz clock frequency. For power integrity, a 1-nF on-chip decoupling capacitor was used [14] [16]. The simulated edge jitter is shown in Fig. 17(a). The maximum edge jitter is observed at 3600 ps. The simulated period jitter is shown in Fig. 17(b). The maximum period jitter is observed at 250 ps. The modulation profile is not an exact triangular modulation profile but an SSCG modulation profile [3]. The spectrum of clock waveform was evaluated using the fast Fourier transform as shown in Fig. 18. The voltage spectrum of the FPC is approximately 120 db µv at 500 MHz and that of the

11 918 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 Fig. 21. Measured edge jitter and measured period jitter of the implemented SSCG with DCA. Measured SSC waveform is shown in (a). The rising and the falling time are approximately 200 ps. The measured operating frequency is approximately 100 MHz. Using (a) the measured SSC waveform and MATLAB program, the edge jitter as (b) and the period jitter as (c) are extracted. The measured jitter profiles are similar to the simulated jitter profiles using the HSPICE as shownin Fig. 17. The measured modulation profile is the SSCG modulation profile. SSC is approximately 110-dB µv at 500 MHz. Therefore, an approximately 10-dB attenuation of the voltage spectrum was achieved. This 10-dB attenuation of voltage spectrum means a 10-dB reduction of EMI. To measure the jitter and EMI, a test print circuit board (PCB) was designed and assembled as shown in Fig. 19. The test PCB was fabricated on a two-layer FR-4 substrate. The size of the PCB is mm, and the height is 1 mm. To generate the FPC, a VCO was used. The operating frequency is approximately 100 MHz. To measure the EMI, an additional microstrip line was used. The length of interconnecting line is 150 mm. The load capacitor is a 2 pf ceramic chip capacitor. The EMI was measured in a 3-m anechoic chamber. Fig. 20 is the measurement setup for SSC waveform using the oscilloscope s single-shot technique. The oscilloscope used is Tektronix TDS7404 that has 50 ps sampling time and 8 MB memory. Using the measured SSC waveform and the MATLAB program, the edge and period jitter were extracted as shown in Fig. 21. The measured edge and period jitter are similar to the HSPICE simulation results. Fig. 22 is the measured EMI spectra of the FPC and the SSC from the implemented SSCG with DCA. The measured EMI for the FPC is approximately 74 db µv/m at 390 MHz, and

12 KIM et al.: SSC GENERATOR WITH DELAY CELL ARRAY TO REDUCE EMI 919 Fig. 22. Measured EMI spectra of the FPC and the SSC from the implemented SSCG with DCA. The measured EMI is attenuated approximately 9 db from 74 to 65 db µv/m at 390 MHz. The measured attenuation is different to the prediction of (1) because the measured SSC has the SSCG modulation profile and the RBW of spectrum analyzer used for EMC measurements is 120 khz. However, (1) assumes the triangular modulation profile and the 0 Hz of RBW of EMC receiver. the measured EMI for the SSC is approximately 65 db µv/m at 390 MHz. The measured EMI was reduced by approximately 9 db at 390 MHz using the proposed, and implemented SSCG with DCA. V. CONCLUSION In this paper, an SSCG with DCA is proposed to reduce EMI from high-speed digital systems. The edge jitter is controlled by implementing the SSC with a triangular modulation profile. The proposed SSCG with DCA has greater effective attenuation and can be more easily implemented than the conventional SSCG with PLL. In addition, because the conventional SSCG controlling the edge jitter cannot generate the triangular modulation profile with sufficient accuracy, the proposed SSCG with DCA has greater effective attenuation than the conventional SSCG. The proposed SSCG with DCA was implemented on an IC chip using a 0.35-µm CMOS process, and a 9 db attenuation of the EMI at 390 MHz was measured. ACKNOWLEDGMENT The authors would like to thank to T. H. Kim for his valuable comments with respect to circuit simulation. REFERENCES [1] H. Ott, Noise Reduction Techniques in Electronic Systems, 2nd ed. New York: Wiley, 1988, pp [2] F. Lin and D. Chen, Reduction of power supply EMI emission by switching frequency modulation, IEEE Trans. Power Electron., vol. 9, no. 1, pp , 1994.

13 920 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO. 4, NOVEMBER 2005 [3] K. Hardin, J. Fessler, and D. Bush, Spread spectrum clock generation for the reduction of radiated emissions, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, Feb. 1994, pp [4] Cypress Preliminary Datasheet, CY2220, 133-MHz spread spectrum clock synthesizer/driver with differential CPU outputs, [5] CK00 clock synthesizer/driver design guidelines, Intel, [6] J. Kim, P. Jun, J. Byun, and J. Kim, Design guidelines of spread spectrum clock for suppression of radiation and interference from high-speed interconnection line, in Proc. IEEE Workshop Signal Propag. Interconnects, 2002, pp [7] J. Kim, P. Jun, and J. Kim, Dithered timing spread spectrum clock generation for reduction of electromagnetic radiated emission from high-speed digital system, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 2002, pp [8] K. Hardin, J. Fessler, N. Webb, J. Berry, A. Cable, and M. Pulley, Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1997, pp [9] K. Hardin, J. Fessler, and D. Bush, A study of the interference potential of spread spectrum clock generation techniques, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1995, pp [10] Cypress Semiconductor Corporation, Clock terminology, revised Jul [11] R. Rust, P. Luque, and D. Knee, Digitally phase modulated clock inhibiting reduced RF emission, U.S. Patent , [12] I. Greiss, Digital modulated clock circuit for reducing EMI spectral density, U.S. Patent 5, vol. 731, no. 728, [13] Y. Moon, D. Jeong, and G. Kim, Clock dithering for electromagnetic compliance using spread spectrum phase modulation, in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp [14] J. Kim, H. Kim, W. Ryu, J. Kim, Y. Yun, S. Kim, S. Ham, H. An, and Y. Lee, Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission, in Proc 48th Electronic Components & Technology Conf., 1998, pp [15] H. Kim, J. Kim, W. Ryu, M. Sung, S. Ahn, and J. Kim, Suppression of radiated emission from an 8-bit micro-controller using gate oxide filtering capacitors, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1999, pp [16] J. Kim, B. Choi, H. Kim, W. Ryu, Y. Yun, S. Ham, S. Kim, Y. Lee, and J. Kim, Separated role of on-chip and on-pcb decoupling capacitors for reduction of radiated emission on printed circuit board, in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 2001, pp Jonghoon Kim received the B.S. degree in electronics from Yeungnam University, Daegu, Korea, in 1995, and the M.S. and the Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1998 and 2003, respectively. In 2003, he joined the Memory Division, Samsung Electronics Company Ltd., Hwasung, Korea, where he is currently a Senior Engineer. He is now working on memory module simulation. Dong Gun Kam received the B.S. degree in physics and the M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2000 and 2002, respectively, and is currently pursuing the Ph.D. degree at Korea Advanced Institute of Science and Technology, Daejeon, Korea. His research interests include signal integrity and power integrity issues in system-in-package design. Pil Jung Jun received the B.S. degree in electronics engineering from Inha University, Incheon, Korea, in After graduation, he joined the Computer System R&D Division, Samsung Electronics Company Ltd., Suwon, Korea, as a Computer Hardware Engineer, where he worked for more than seven years. He now works on the EMC design and analysis of computer systems. His practical experience lies in the areas of EMI design and debugging and ESD robust design. Currently, he is interested in increasing the correlation between the practical complicated products and the commercial software tools of EMI simulation and modeling. Joungho Kim received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree from the University of Michigan, Ann Arbor, in 1993, all in electrical engineering. During his graduate study, he was involved in femtosecond time-domain optical measurement technique for high-speed device and circuit testing. In 1993, he as a Research Engineer at Picometrix Inc., Ann Arbor, MI, where he was responsible for the development of picosecond sampling systems and 70-GHz photoreceivers. In 1994, he joined the Memory Division, Samsung Electronics, Kiheung, Korea, where he was engaged in gigabite-scale DRAM design. In 1996, he became an Associate Professor with the Electrical Engineering and Computer Science Department, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. Since joining KAIST, his research centers on modeling, design, and measurement of high-speed interconnection, package, and PCB. In particular, his research includes design issues of signal integrity, power/ground noise, and radiated emission in high-speed SerDes channel, system-on-package, and multilayer PCB. He was on sabbatical leave during the 2001/2002 academic year, during which time he worked as a Staff Engineer at Silicon Image Inc., Sunnyvale, CA. He was responsible for the low noise package design of SATA, FC, and Panel Link SerDes devices. Currently, he is working as a Technical Consultant in automobile EMI/EMC design at Hyundai Motors Inc. He has more than 180 publications in refereed journals and conferences. Dr. Kim has been the Chair or the Co-Chair of the EDAPS Workshop since He is also an Associate Editor of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY.