Data Sheet. MGA GHz WLAN Power Amplifier Module. Description. Features. Component Image. Applications. Pin Configuration

Transcription

1 MGA GHz WLAN Power Amplifier Module Data Sheet Description Avago Technologies MGA is a fully matched power amplifier for use in the WLAN band ( MHz). High linear output power at 5.0 V is achieved through the use of Avago s proprietary 0.25 µm GaAs Enhancement-mode phemt process. MGA is housed in a miniature 5.0 mm 5.0 mm molded-chip-on-board (MCOB) module package. A detector is also included on-chip. The compact footprint coupled with high gain, high linearity and good efficiency makes the MGA an ideal choice as a power amplifier for small cell enterprise WLAN PA applications. Component Image ( ) mm Package Outline AVAGO YYWW XXXX TOP VIEW Notes: Package marking provides orientation and identification = Device part number YYWW = Year and work week XXXX = Assembly lot number Features Linear P EVM =2.5% (802.11n): 27.8 dbm Linear P out with Restricted Band Emission (802.11n) of MHz: 22.2 dbm Linear P out with Restricted Band Emission (802.11n) of MHz: 22.2 dbm High gain : 40.5 db Fully matched input and output ports Built-in detector GaAs E-pHEMT Technology [1] Low-cost small package size: ( ) mm MSL3 Lead-free/Halogen-free/RoHS compliance Note: 1. Enhancement mode technology employs positive V GS, and so eliminates the need for negative gate voltage associated with conventional depletion mode devices. Applications Enterprise WLAN access points Small cell with embedded WLAN Pin Configuration 28 Vdd1 27 Gnd 26 Vdd2 25 Gnd 24 Vdd3 23 Vdd3 22 Vdd3 Gnd 1 Gnd 2 NC 3 RFin 4 NC 5 Gnd 6 NC 7 ( ) mm 21 Gnd 20 Gnd 19 RFout 18 RFout 17 RFout 16 Gnd 15 Gnd Functional Block Diagram RFin Vdd1 Vdd2 Vdd3 1 st Stage 2 nd Stage 3 rd Stage RFout Attention: Observe precautions for handling electrostatic-sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 400 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Vc1 8 Vc2 9 Vc3 10 Gnd 11 VddBias 12 Gnd 13 Vdet 14 Biasing Circuit Top View Vc1 Vc2 Vc3 VddBias Vdet

2 Absolute Maximum Rating [1] T A = 25 C Symbol Parameter Units Absolute Max. V dd, V ddbias Supply voltages, bias supply voltage V 5.5 V c Control voltage V (V dd ) P in,max CW RF Input Power dbm 20 P diss Total Power Dissipation [3] W 6.0 T j Junction Temperature C 150 T STG Storage Temperature C -65 to 150 Thermal Resistance [2,3] q JC = 13 C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra- Red Measurement Technique. 3. Board temperature (T C ) is 25 C, for T C > 72 C derate the device power at 77 mw per C rise in board (package belly) temperature. Electrical Specifications T A = 25 C, V dd = V ddbias =5.0 V, V c1 =2.0 V, V c2 =2.2 V, V c3 =2.0 V, RF performance at 2442 MHz, IEEE n 64-QAM, 20 MHz Bandwidth, MCS 7, 800 ns Guard Interval, unless otherwise stated. Symbol Parameter and Test Condition Units Min. Typ. Max. V dd Supply Voltage V 5.0 I dq Quiescent Supply Current ma I ddtotal Total Supply Current at linear output 21 dbm (2412 MHz) ma Total Supply Current at linear output 21 dbm (2462 MHz) ma Total Supply Current at linear output 27 dbm ma 700 S21 Small Signal Gain db 40.5 S11 Input Return Loss, 50 Ω source db 12.5 S22 Output Return Loss, 50 Ω source db 13.5 OP1dB Output Power at 1 db Gain Compression dbm 36 PAE Power Added Efficiency at linear output 21 dbm (2412 MHz) % 4.4 Power Added Efficiency at linear output 21 dbm (2462 MHz) % 5.2 Power Added Efficiency at linear output 27 dbm % fo 2nd Harmonic Distortion at 27 dbm dbc fo 3rd Harmonic Distortion at 27 dbm dbc Linear P out Restricted Band Emission 21 dbm at 2390 MHz (2412 MHz) dbm Restricted Band Emission 21 dbm at MHz (2462 MHz) dbm Error Vector Magnitude at 2.5% dbm

3 Product Consistency Distribution Charts [1] Figure 1. I dq Figure 2. I dd 21 dbm at 2412 MHz Figure 3. I dd 21 dbm at 2462 MHz Figure dbm at 2390 MHz Figure dbm at MHz Note: 1. Distribution data sample size is 1200 samples taken from three wafer lots. T A = 25 C, V dd = V ddbias = 5.0 V, V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V, RF input at 2412 MHz and 2462 MHz, unless otherwise stated. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 3

4 MGA typical small-signal over-temperature performance at V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V (V dd = V ddbias = 5.0 V) as per demonstration board in Figure 28, unless otherwise stated. S11 (db) C C 40 C C C 85 C Frequency (GHz) Figure 6. Over-temperature S11 vs. Frequency S22 (db) Frequency (GHz) Figure 7. Over-temperature S22 vs. Frequency S21 (db) C 40 C 85 C Frequency (GHz) Figure 8. Over-temperature S21 vs. Frequency 4

5 MGA typical over-temperature performance at V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V (V dd = V ddbias = 5.0 V) with IEEE n 64-QAM, 20 MHz Bandwidth, MCS 7, 800 ns Guard Interval as per demonstration board in Figure 28, unless otherwise stated. RBE (dbm) at 2390 MHz MHz Figure 9. Over-temperature RBE at 2390 MHz vs MHz P out RBE (dbm) at MHz MHz Figure 10. Over-temperature RBE at MHz vs MHz P out RBE (dbm) at 2390 MHz MHz Figure 11. Over-temperature RBE at 2390 MHz vs MHz P out RBE (dbm) at MHz MHz Figure 12. Over-temperature RBE at MHz vs MHz P out EVM (%) EVM (%) Figure13. Over-temperature EVM vs. P out at 2412 MHz Figure 14. Over-temperature EVM vs. P out at 2442 MHz 5

6 MGA typical over-temperature performance at V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V (V dd = V ddbias = 5.0 V) with IEEE n 64-QAM, 20 MHz Bandwidth, MCS 7, 800 ns Guard Interval as per demonstration board in Figure 28, unless otherwise stated. (con't) EVM (%) Figure 15. Over-temperature EVM vs. P out at 2462 MHz PAE (%) Figure 16. Over-temperature PAE vs. P out at 2442 MHz Itotal (A) Vdet(V) Figure 17. Over-temperature I total vs. P out at 2442 MHz Figure 18. Over-temperature V det vs. P out at 2442 MHz 2nd Harmonic (dbc) Figure19. Over-temperature 2nd Harmonic vs. P out at 2442 MHz 3rd Harmonic (dbc) Figure 20. Over-temperature 3rd Harmonic vs. P out at 2442 MHz 6

7 MGA typical over-temperature performance at V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V (V dd = V ddbias = 5.0 V) with IEEE n 64-QAM, 20 MHz Bandwidth, MCS 7, 800 ns Guard Interval as per demonstration board in Figure 28, unless otherwise stated. (con't) Gain (db) Gain I total C Figure 21. Over-temperature CW Gain, I total vs. P out at 2412 MHz Itotal (A) Gain (db) Gain I total Figure 22. Over-temperature CW Gain, I total vs. P out at 2442 MHz Itotal (A) Gain (db) Gain I 38.5 total Figure 23. Over-temperature CW Gain, I total vs. P out at 2462 MHz Itotal (A) 7

8 MGA typical over-temperature performance at V c1 = 2.0 V, V c2 = 2.2 V, V c3 = 2.0 V (V dd = V ddbias = 5.0 V) with IEEE n 64-QAM, 20 MHz Bandwidth, MCS 7, 800 ns Guard Interval as per demonstration board in Figure 28, unless otherwise stated. (con't) Spectrum Emission Mask (SEM) with n IEEE signal Power (db) Frequency Offset (MHz) Figure 24. Over-temperature SEM 22 dbm at 2442 MHz SEM Limit Power (db) Frequency Offset (MHz) Figure 25. Over-temperature SEM 29.5 dbm at 2442 MHz SEM Limit Spectrum Emission Mask (SEM) with b IEEE signal Power (db) SEM Limit Frequency Offset (MHz) Figure 26. Over-temperature SEM 22 dbm at 2442 MHz Power (db) SEM Limit Frequency Offset (MHz) Figure 27. Over-temperature SEM 32.5 dbm at 2442 MHz 8

9 S-Parameter [1] (V dd = V ddbias = 5.0 V, V c1 = 2.0 V, V c2 = 2.2 V, V c3 =2.0 V), T = 25 C, 50 Ω matched) Freq (GHz) 9 S11 (db) S11 (ang) S21 (db) S21 (ang) S22 (db) S22 (ang) S12 (db) S12 (ang)

10 S-Parameter [1] (V dd = V ddbias = 5.0 V, V c1 = 2.0 V, V c2 = 2.2 V, V c3 =2.0 V), T = 25 C, 50 Ω matched) Cont. Freq (GHz) S11 (db) S11 (ang) S21 (db) S21 (ang) S12 (db) Note: 1. S-parameter is measured with de-embedded reference plane at DUT RF in and RF out pins. S12 (ang) S22 (db) S22 (ang) 10

11 Test system setup Power Meter MXA Signal Analyzer Ext Trig 1 Event 1 Power Sensor MGA Power Sensor Signal Generator Coupler IEEE n 20 MHz (MCS 7) Signal Cavity Filter Isolator Attenuator Coupler Attenuator Power Supply Small-signal performance for Cavity Filter S11, S22, S21 (db) S(1,1) S(2,2) S(2,1) Frequency (GHz) freq S(1,1) S(2,1) S(2,2) S(1,2) GHz db ang db ang db ang db ang A cavity filter is used at the input of the DUT to ensure that a clean signal from the signal generator is presented to the DUT. 11

12 Demonstration Board Top View V dd1 (force) +5V V dd1s (sense) +5V V dd2 (force) +5V V dd2s (sense) +5V V dd3 (force) +5V V dd3s (sense) +5V Component Value Part Number Manufacturer Size C1, C2, C18, 7.5 pf GJM1555C1H7R5BB01D Murata 0402 C20, C22 C3, C7, C13, 0.1 µf GRM155R71C104KA88D Murata 0402 C25 C4, C8 8.2 pf GRM1555C1H8R2DZ01E Murata 0402 C µf GRM21BR71E225KA73L Murata 0805 C pf GJM1555C1H6R0CB01D Murata 0402 C26 22 nf CM05X7R223K16AHF AVX 0402 R1 0 Ω RMC1/10 JPTP Kamaya 0805 R2, R3, R4, R5 0 Ω RMC1/16S JPTH Kamaya 0402 V c1 =2.0 V V c2 =2.2 V V ddbias +5V V det Vc3=2.0 V (Output) V dd1s V dd2 V dd2s V dd3 V (sense) (force) (sense) (force) dd1 V (force) +5V +5V +5V +5V dd3s (sense) +5V +5V Pins pointing out of the page (unit is on top) Application board pin header assignments Pin 1 : V dd3 (Sense) Pin 2 : V dd3 (Force) Pin 3 : V dd2 (Sense) Pin 4 : V dd2 (Force) Pin 5 : V dd1 (Sense) Pin 6 : V dd1 (Force) Pin 13 : V c1 Pin 14 : V c2 Pin 15 : V c3 Pin 16 : V ddbias (Force) Pin 17 : V det All other pins are grounded V c1 =2.0 V V c2 =2.2 V V ddbias +5V V det Vc3=2.0 V (Output) Figure 28. Demonstration board application circuit for MGA module 12

13 Application Schematic C3 C4 Z = 50 Ω E = 8.3 deg F = GHz Vdd1 C8 Vdd2 Idq1 C7 Idq2 Idq3 Z = 50 Ω E = 7.0 deg F = GHz Z = 50 Ω E = 8.3 deg F = GHz Vdd3 C10 C13 1 RFin Z = 50 Ω F = GHz C1 Top View C2 RFout Z = 50 Ω F = GHz C18 C20 C22 C24 I_Vddbias C25 C26 Vc1 Vc2 Vc3 Vddbias Vdet Figure 29. Application circuit in demonstration board Notes: 1. All capacitors on supply lines are bypass capacitors. 2. C1/C2 are RF coupling capacitors. 3. For V dd = V ddbias = 5.0 V, I dq1 = 50 ma, I dq2 = 150 ma, I dq3 = 248 ma, I_V ddbias = 12 ma. These currents enable optimum bias conditions to be achieved for best linearity for n signal. 13

14 PCB Land Pattern and Stencil Outline Pin SolderMask Opening 0.50 (pitch) 0.25 PCB Land Pattern 0.50 Stencil Opening SolderMask Top Metal Notes: 1. Recommended Land Pattern and Stencil mils stencil thickness recommended. 3. All dimensions are in mm Combination of Land Pattern and Stencil Opening 14

15 MCOB (5.0 x 5.0 x 0.82) mm 28-Lead Package Dimensions PIN #1 Identification 5.00 ± ± PIN #1 Identification CHAMFER 0.43 x 45 AVAGO YYWW XXXX 5.00 ± Top View Side View Bottom View Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash and metal burr. Part Number Ordering Information Part Number Qty Container MGA BLKG 100 Antistatic Bag MGA TR1G Reel 15

16 Device Orientation REEL USER FEED DIRECTION CARRIER TAPE AVAGO YYWW XXXX AVAGO YYWW XXXX AVAGO YYWW XXXX USER FEED DIRECTION COVER TAPE TOP VIEW END VIEW Tape Dimensions 16

17 Reel Dimensions (7 reel) Flange Thickness : Min mm min max min. Hatched Area Indicates Thru Hole FRONT VIEW Note: Dimensions are in mm. 2.5±0.5 RECYCLE SYMBOL 12.8 min max min TOLERANCE.X = ±0.25.XX = ±0.13 BACK VIEW 17

18 For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV EN - October 8, 2014