Quad, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter AD9144

Transcription

1 FEATURES Supports input data rate >1 GSPS Proprietary low spurious and distortion design 6-carrier GSM IMD = 77 dbc at 75 MHz IF SFDR = 82 dbc at dc IF, 9 dbfs Flexible 8-lane JESD204B interface Support quad or dual DAC mode at 2.8 GSPS Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 2, 4, 8 interpolation filter Low power architecture Input signal power detection Emergency stop for downstream analog circuitry protection Transmit enable function allows extra power saving High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power 1.5 W at 1.0 GSPS, 1.7 W at 1.5 GSPS, full operating conditions 88-lead LFCSP with exposed pad APPLICATIONS Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point-to-point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment GENERAL DESCRIPTION The is a quad, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF672x analog quadrature modulators (AQMs) from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 14 ma to 26 ma. The is available in an 88-lead LFCSP. Quad, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter FUNCTIONAL BLOCK DIAGRAM QUAD MOD ADRF672x 0/90 PHASE SHIFTER LO_IN QUAD MOD ADRF67xx MOD_SPI 0/90 PHASE SHIFTER LPF LPF DAC DAC QUAD DAC DAC DAC LO_IN MOD_SPI DAC DAC CLOCK SPI Figure 1. JESD204B SYNC SYSREF JESD204B SYNC PRODUCT HIGHLIGHTS 1. Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. 2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. Very small inherent latency variation simplifies both software and hardware design in the system, allowing easy multichip synchronization for most applications. 4. Fewer pins for data interface width with serializer/ deserializer (SERDES) JESD204B eight-lane interface. 5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. 6. Small package size with 12 mm 12 mm footprint Rev. PrJ Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagram... 1 Product Highlights... 1 Detailed Functional Block Diagram... 4 Specifications... 5 DC Specifications... 5 Digital Specifications... 6 DAC Update Rate Speed Specifications By Supply... 7 JESD204B Serial Interface Speed Specifications... 7 SysRef to DAC clock timing specifications... 7 Digital Input Data Timing Specifications... 8 Latency Variation Specifications... 8 JESD204B Interface Electrical Specifications... 8 AC Specifications... 9 Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation Serial Port Operation Data Format Serial Port Pin Descriptions Serial Port Options JESD204B Serial Data Interface JESD204B Serial Link Establishment Deserializer Equalization Data Link Layer SYNCOUTX± and SYSREF± Signals Measuring Fixed and Variable Delays in the JESD204B Link Subclass 0 Operation Transport Layer JESD204B Test Modes Hardware Considerations Digital Datapath Preliminary Technical Data Interpolation Filters Digital Modulation Updating the Frequency Tuning Word Digital Quadrature Gain, Group Delay, and Phase Adjustment DC Offset Adjustment Inverse Sinc Filter Input Signal Power Detection and Protection Datapath Configuration Digital Function Configuration Interrupt Request Operation Interrupt Service Routine DAC Input Clock Configurations Driving the CLK± Inputs Clock Multiplication Starting the PLL Analog Outputs Transmit DAC Operation Device Power Dissipation Temperature Sensor Start-up Sequence Step 1: Power Up Step 2: Adjust Defaults Step 3: Configure the DAC PLL Step 4: Interpolation Step 5: JESD 204B Setup for Link Step 6: JESD 204B Setup for Link Step 7: Autotune Input Termination Resistance Step 8: Configure SERDES PLL Step 9: Set and Release CDRs Step 10: Update Deserializer SPI Synchronization Clock Step 11: LMFC For Debug Only Step 12: Sync Step 13: Enable Links Check Link 0 Status Step 14: Check for Code Group Sync (CGS) on Link Step 15: System Task at FPGA Step 16: Check Link Step 17: Access Link Step 18: Check for CGS on Link Step 19: System Task at FPGA Rev. PrJ Page 2 of 150

3 Step 20: Check Link Register Maps and Descriptions Device Configuration Register Map Device Configuration Register Descriptions Lookup Tables for Three Different DAC PLL Reference Frequencies Outline Dimensions Rev. PrJ Page 3 of 150

4 Preliminary Technical Data DETAILED FUNCTIONAL BLOCK DIAGRAM DIV DACCLK PLL (40 ) V TT PDP1 HB1 HB2 HB3 MODE CONTROL COMPLEX MODULATION NCO INV SINC Q-SCALE PHASE I-SCALE ADJUST Q-OFFSET I-OFFSET GAIN DACCLK OUT3+ OUT3 SERDIN7± SERDIN0± CLOCK DATA RECOVERY AND CLOCK FORMATTER PDP0 HB1 HB1 HB2 HB2 HB3 HB3 MODE CONTROL f DAC 4 COMPLEX MODULATION NCO INV SINC Q-SCALE PHASE I-SCALE ADJUST Q-OFFSET I-OFFSET PDP OUT0 PDP OUT1 SYNCOUT0+ SYNCOUT0 SYNCOUT1+ SYNCOUT1 SYNCHRONIZATION LOGIC CONFIG REGISTERS PLL_CTRL CLK_SEL SERIAL I/O PORT POWER-ON RESET CLOCK MULTIPLIER (50 TO 100 ) SDO SDIO SCLK CS RESET IRQ DAC ALIGN DETECT REF AND BIAS I120 SYSREF+ SYSREF DACCLK PLL_LOCK TXEN0 TXEN1 GAIN GAIN DACCLK OUT2+ OUT2 OUT1+ OUT1 HB1 HB2 HB3 f DAC 4 GAIN OUT0+ OUT0 CLOCK DISTRIBUTION AND CONTROL LOGIC SYSREF RCVR DIVIDER (1, 2, 4, 16, 32) CLK RCVR CLK+ CLK Figure 2. Rev. PrJ Page 4 of 150

5 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, SVDD12 = 1.2 V, TA = 25 C, IOUTFS = 20 ma, maximum sample rate, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ACCURACY With calibration Differential Nonlinearity (DNL) ±1.0 LSB Integral Nonlinearity (INL) ±2.0 LSB MAIN DAC OUTPUTS Offset Error % FSR Gain Error With internal reference % FSR I/Q Gain Mismatch % FSR Full-Scale Output Current Based on a 4 kω external resistor between I120 and ma GND Output Compliance Range mv Output Resistance 0.2 MΩ Output Capacitance 3.0 pf Gain DAC Monotonicity Guaranteed Settling Time To within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/ C Gain 32 ppm/ C Reference Voltage 16 ppm/ C REFERENCE Internal Reference Voltage 1.2 V ANALOG SUPPLY VOLTAGES AVDD V PVDD V CVDD V DIGITAL SUPPLY VOLTAGES SIOVDD V VTT V DVDD V V SVDD V V IOVDD V POWER CONSUMPTION 2 Mode fdac = 1.5 GSPS, IF = 10 MHz, PLL on, NCO off 1.7 W AVDD ma PVDD12 50 ma CVDD12 90 ma SVDD12 Includes VTT 665 ma DVDD ma OPERATING TEMPERATURE RANGE C Rev. PrJ Page 5 of 150

6 Preliminary Technical Data DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, SVDD12 = 1.2 V, T A = 25 C, IOUTFS = 20 ma, maximum sample rate, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 1.8 V IOVDD 3.3 V 0.7 IOVDD V Low 1.8 V IOVDD 3.3 V 0.3 IOVDD V CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High 1.8V IOVDD 3.3 V 0.7 IOVDD V Low 1.8V IOVDD 3.3 V 0.3 IOVDD V DAC UPDATE RATE 1 2 interpolation 2120 MSPS 4 interpolation 2800 MSPS 8 interpolation 2800 MSPS ADJUSTED DAC UPDATE RATE 2 interpolation 1060 MSPS 4 interpolation 700 MSPS 8 interpolation 350 MSPS INTERFACE 2 Number of JESD204B 8 Lanes Lanes JESD204B Serial Interface Speed Minimum Per lane 1.42 Gbps Maximum Per lane, SVDD12 = 1.3 V ± 2% 10.6 Gbps DAC CLOCK INPUT (CLK+, CLK ) Differential Peak-to-Peak Voltage mv Common-Mode Voltage Self biased input, ac-coupled 600 mv Maximum Clock Rate 2800 MHz REFCLK Frequency (PLL 6.0 GHz fvco 12.0 GHz MHz Mode) SYSTEM REFERENCE INPUT (SYSREF+, SYSREF ) Differential Peak-to-Peak mv Voltage Common-Mode Voltage mv SYSREF± Frequency 3 fdata/(k (F/S)) Hz SYSREF to DAC CLOCK 4 SysRef swing = 0.4 V, slew rate = 1.3 V/ns, common modes tested: ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V Setup Time tssd 131 ps Hold Time thsd 119 ps Keep Out Window KOW 20 ps SERIAL PORT INTERFACE Maximum Clock Rate SCLK IOVDD = 1.8 V 10 MHz Minimum Pulse Width High tpwh 8 ns Low tpwl 12 ns SDIO to SCLK Rev. PrJ Page 6 of 150

7 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Setup Time tds 5 ns Hold Time tdh 2 ns SDO to SCLK Data Valid tdv 25 ns CS to SCLK Setup Time tdcsb 5 ns Hold Time tdcsb 2 ns 1 See Table 3 for detailed specifications for DAC update rate conditions 2 See Table 4 for detailed specifications for JESD speed conditions 3 K, F, and S are JESD204B transport layer parameters. See Table 28 for the full definitions. 4 See Table 5 for detailed specifications for SysRef to DAC Clock timing conditions. TABLE 3DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DAC UPDATE RATE DVDD12, CVDD12 = 1.2 V ± 5% 2.23 GSPS DVDD12, CVDD12 = 1.2 V ± 2% 2.41 GSPS DVDD12, CVDD12 = 1.3 V ± 2% 2.80 GSPS JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS Table 4. Parameter Test Conditions/Comments Min Typ Max Unit HALF RATE SVDD12 = 1.2 V ± 5% Gbps SVDD12 = 1.2 V ±2% Gbps SVDD12 = 1.3 V ± 2% Gbps FULL RATE SVDD12 = 1.2 V ± 5% Gbps SVDD12 = 1.2 V ±2% Gbps SVDD12 = 1.3 V ± 2% Gbps OVERSAMPLING SVDD12 = 1.2 V ± 5% Gbps SVDD12 = 1.2 V ±2% Gbps SVDD12 = 1.3 V ± 2% Gbps SYSREF TO DAC CLOCK TIMING SPECIFICATIONS The following common-modes are tested = 0.0 V, 0.6 V, 1.25 V, and 2.0 V. Table 5. Parameter Test Conditions/Comments Min Unit SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns Setup Time AC-coupled 126 ps DC-coupled 131 ps Hold Time AC-coupled 92 ps DC-coupled 119 ps SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns Setup Time AC-coupled 96 ps DC-coupled 104 ps Hold Time AC-coupled 77 ps DC-coupled 95 ps SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns Setup Time AC-coupled 83 ps DC-coupled 90 ps Hold Time AC-coupled 68 ps DC-coupled 84 ps Rev. PrJ Page 7 of 150

8 Preliminary Technical Data DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY DACCLK Cycles Interface Link 0 17 PCLK Cycles Interpolation With or without modulation DAC Clock Cycles DAC Clock Cycles DAC Clock Cycles Inverse Sinc 17 DAC Clock Cycles Fine Modulation 20 DAC Clock Cycles Coarse Modulation fs/8 8 DAC Clock Cycles fs/4 4 DAC Clock Cycles Digital Phase Adjust 12 DAC Clock Cycles Digital Gain Adjust 12 DAC Clock Cycles Power-Up Time 350 ms LATENCY VARIATION SPECIFICATIONS Table 7. Parameter Min Typ Max Unit Test Conditions/Comments DAC LATENCY VARIATION SYNC Off Subclass 0 Mode 4 4 DACCLK cycles Given proper calibration of LMFC delay. SYNC On PLL Off 0 1 DACCLK cycles PLL On 1 +1 DACCLK cycles JESD204B INTERFACE ELECTRICAL SPECIFICATIONS Table 8. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B DATA INPUTS Input Leakage Current 25 C Logic High Input level = 1.2 V ±, 0.25 V, VTT = 1.2 V 10 µa Logic Low Input level = 0 V 4 µa Unit Interval UI ps Common-Mode Voltage VRCM AC-coupled V VTT = SVDD12 1 Differential Voltage R_VDIFF mv VTT Source Impedance ZTT At dc 30 Ω Differential Impedance ZRDIFF At dc Ω Differential Return Loss RLRDIF 8 db Common-Mode Return Loss RLRCM 6 db DIFFERENTIAL OUTPUTS (SYNCOUT±) Logic Compliance LVDS Differential Output Voltage 2 VOD 200 mv Output Offset Voltage VOS V DETERMINISTIC LATENCY Link 0 All modes Fixed 17 PCLKs 3 Variable 2 PCLKs Rev. PrJ Page 8 of 150

9 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Link 1 All modes Fixed 20 PCLKs Variable 3 PCLKs SYSREF-to-LMFC DELAY 4 DAC Clock Cycles 1 As measured on the input side of the ac coupling capacitor. 2 VOD can be increased to 370 mv by programming Register 0x2A5[0] to 1. 3 PCLK is the JESD204B byte clock and equals the lane rate 40. AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, SVDD12 = 1.2 V 1, TA = 25 C, IOUTFS = 20 ma, unless otherwise noted. Table 9. Parameter Test Conditions/Comments Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) 9 dbfs single tone fdac = MSPS fout = 20 MHz 82 dbc fdac = MSPS fout = 150 MHz 76 dbc fdac = MSPS fout = 20 MHz 81 dbc fdac = MSPS fout = 170 MHz 69 dbc TWO-TONE INTERMODULATION DISTORTION (IMD) 9 dbfs fdac = MSPS fout = 20 MHz 90 dbc fdac = MSPS fout = 150 MHz 82 dbc fdac = MSPS fout = 20 MHz 90 dbc fdac = MSPS fout = 170 MHz 81 dbc NOISE SPECTRAL DENSITY (NSD), SINGLE TONE 0 dbfs fdac = MSPS fout = 150 MHz 162 dbm/hz fdac = MSPS fout = 150 MHz 163 dbm/hz W-CDMA FIRST ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER 0 dbfs fdac = MSPS fout = 30 MHz 82 dbc fdac = MSPS fout = 150 MHz 80 dbc fdac = MSPS fout = 150 MHz 80 dbc W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER 0 dbfs fdac = MSPS fout = 30 MHz 84 dbc fdac = MSPS fout = 150 MHz 85 dbc fdac = MSPS fout = 150 MHz 85 dbc 1 SVDD12 = 1.3 V for all fdac = MSPS conditions in Table 9. Rev. PrJ Page 9 of 150

10 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter I120 to GND SERDINx±, VTT, SYNCOUT1±/ SYNCOUT0±, TXENx OUTx± SYSREF± CLK± to GND RESET, IRQ, CS, SCLK, SDIO, SDO, PDP OUTx to Ground LDO_BYP1 LDO_BYP2 LDO24 Rating 0.3 V to AVDD V 0.3 V to SIOVDD V 0.3 V to AVDD V GND 0.5 V to +2.5 V 0.3 V to PVDD V 0.3 V to IOVDD V 0.3 V to SVDD V 0.3 V to PVDD V 0.3 V to AVDD V PDP_Outx 0.3 V to IOVDD V Junction Temperature 125 C Storage Temperature Range 65 C to +150 C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE The exposed pad (EPAD) must be soldered to the ground plane for the 88-lead LFCSP. The EPAD provides an electrical, thermal, and mechanical connection to the board. Typical θja, θjb, and θjc values are specified for a 4 layer JESD51-7 high effective thermal conductivity test board for leaded Preliminary Technical Data surface-mount packages. θja is obtained in still air condition (JESD51-2). Airflow increases heat dissipation, effectively reducing θja. θjb is obtained following double-ring cold plate test conditions (JESD51-8). θjc is obtained with the test case temperature monitored at the bottom of the exposed pad. ΨJT and ΨJB are thermal characteristic parameters obtained with θja in still air test condition. Junction temperature Tj can be estimated using the following equations: TJ = TT + (ΨJT P), or TJ = TB + (ΨJB P) where: TT is the temperature measured at the top of the package. TB is the temperature measured at the board. P is the total device power dissipation. Table 11. Thermal Resistance Package θja θjb θjc ψjt ψjb Unit 88-Lead LFCSP C/W 1 The EPAD must be soldered to the ground plane. ESD CAUTION Rev. PrJ Page 10 of 150

11 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PVDD12 CLK+ CLK PVDD12 SYSREF+ SYSREF PVDD12 PVDD12 PVDD12 PVDD12 TXEN0 TXEN1 DVDD12 DVDD12 SERDIN0+ SERDIN SVDD12 17 SERDIN1+ 18 SERDIN1 19 SVDD12 20 V TT 21 SVDD IOVDD 65 CS 64 SCLK 63 SDIO 62 SDO 61 RESET 60 IRQ 59 PDP OUT0 PDP OUT PVDD12 PVDD12 GND GND DVDD12 SERDIN7+ SERDIN7 SVDD12 SERDIN6+ SERDIN6 SVDD12 V TT SVDD12 SYNCOUT0+ SYNCOUT0 V TT SERDIN2+ SERDIN2 SVDD12 SERDIN3+ SERDIN3 SVDD12 SVDD12 SVDD12 LDO_BYP1 SIOVDD33 SVDD12 SERDIN4 SERDIN4+ SVDD12 SERDIN5 SERDIN LDO_BYP2 87 CVDD12 86 I AVDD33 84 OUT0+ 83 OUT0 82 LDO24 81 CVDD12 80 LDO OUT1 OUT1+ AVDD33 CVDD12 AVDD33 OUT2+ OUT2 LDO24 CVDD12 LDO24 OUT3 OUT3+ AVDD33 TOP VIEW (Not to Scale) V TT 42 SYNCOUT1 43 SYNCOUT1+ 44 NOTES 1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE. Figure 3. Pin Configuration Table 12. Pin Function Descriptions Pin No. Mnemonic Description 1 PVDD V Supply. PVDD12 provides a clean supply. 2 CLK+ PLL Reference/Clock Input (Positive). When the PLL is used, this is the positive reference clock input. When the PLL is not used, this is the positive device clock input. This pin is self biased and should be ac-coupled. 3 CLK PLL Reference/Clock Input (Negative). When the PLL is used, this is the negative reference clock input. When the PLL is not used, this is the negative device clock input. This pin is self biased with and should be ac-coupled. 4 PVDD V Supply. PVDD12 provides a clean supply. 5 SYSREF+ Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It may be ac-coupled or dc-coupled. 6 SYSREF Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It may be ac-coupled or dc-coupled. 7 PVDD V Supply. PVDD12 provides a clean supply. 8 PVDD V Supply. PVDD12 provides a clean supply. 9 PVDD V Supply. PVDD12 provides a clean supply. 10 PVDD V Supply. PVDD12 provides a clean supply. 11 TXEN0 Transmit Enable for DAC0 and DAC1. The CMOS levels are determined with respect to IOVDD. 12 TXEN1 Transmit Enable for DAC2 and DAC3. The CMOS levels are determined with respect to IOVDD. 13 DVDD V Digital Supply. 14 DVDD V Digital Supply. 15 SERDIN0+ Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 16 SERDIN0 Serial Channel Input 0, Negative. CML compliant. SERDIN0 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 17 SVDD V JESD204B Receiver Supply. 18 SERDIN1+ Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 19 SERDIN1 Serial Channel Input 1, Negative. CML compliant. SERDIN1 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Rev. PrJ Page 11 of 150

12 Preliminary Technical Data Pin No. Mnemonic Description 20 SVDD V JESD204B Receiver Supply. 21 VTT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 22 SVDD V JESD204B Receiver Supply. 23 SYNCOUT0+ Positive LVDS Sync (Active Low) Output Signal Channel Link SYNCOUT0 Negative LVDS Sync (Active Low) Output Signal Channel Link VTT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 26 SERDIN2+ Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 27 SERDIN2 Serial Channel Input 2, Negative. CML compliant. SERDIN2 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 28 SVDD V JESD204B Receiver Supply. 29 SERDIN3+ Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 30 SERDIN3 Serial Channel Input 3, Negative. CML compliant. SERDIN3 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 31 SVDD V JESD204B Receiver Supply. 32 SVDD V JESD204B Receiver Supply. 33 SVDD V JESD204B Receiver Supply. 34 LDO_BYP1 LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µf capacitor to ground. 35 SIOVDD V Supply for SERDES. 36 SVDD V JESD204B Receiver Supply. 37 SERDIN4 Serial Channel Input 4, Negative. CML compliant. SERDIN4 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 38 SERDIN4+ Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 39 SVDD V JESD204B Receiver Supply. 40 SERDIN5 Serial Channel Input 5, Negative. CML compliant. SERDIN5 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 41 SERDIN5+ Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 42 VTT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 43 SYNCOUT1 Negative LVDS Sync (Active Low) Output Signal Channel Link SYNCOUT1+ Positive LVDS Sync (Active Low) Output Signal Channel Link SVDD V JESD204B Receiver Supply. 46 VTT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 47 SVDD V JESD204B Receiver Supply. 48 SERDIN6 Serial Channel Input 6, Negative. CML compliant. SERDIN6 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 49 SERDIN6+ Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 50 SVDD V JESD204B Receiver Supply. 51 SERDIN7 Serial Channel Input 7, Negative. CML compliant. SERDIN7 is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 52 SERDIN7+ Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 53 DVDD V Digital Supply. 54 GND Ground. Connect GND to the ground plane. 55 GND Ground. Connect GND to the ground plane. 56 PVDD V Supply. PVDD12 provides a clean supply. 57 PVDD V Supply. PVDD12 provides a clean supply. 58 PDP OUT1 Power Detection Protection Pin Output for DAC 2 and DAC 3. Pin 58 is high when power protection is in process. 59 PDP OUT0 Power Detection Protection Pin Output for DAC 0 and DAC 1. Pin 59 is high when power protection is in process. 60 IRQ Interrupt Request (Active Low, Open Drain). Rev. PrJ Page 12 of 150

13 Pin No. Mnemonic Description 61 RESET Reset. This pin is active low, CMOS levels are determined with respect to IOVDD. 62 SDO Serial Port Data Output. CMOS levels are determined with respect to IOVDD. 63 SDIO Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD. 64 SCLK Serial Port Clock Input. CMOS levels are determined with respect to IOVDD. 65 CS Serial Port Chip Select. This pin is active low, CMOS levels are determined with respect to IOVDD. 66 IOVDD IOVDD Supply for CMOS I/O and SPI. Operational for 1.8 V IOVDD 3.3 V. 67 AVDD V Analog Supply for DAC Cores. 68 OUT3+ DAC3 Positive Current Output. 69 OUT3 DAC3 Negative Current Output. 70 LDO V LDO. Requires 1 µf capacitor to ground. 71 CVDD V Clock Supply. Place bypass capacitors as near to Pin 71 as possible. 72 LDO V LDO. Requires 1 µf capacitor to ground. 73 OUT2 DAC2 Negative Current Output. 74 OUT2+ DAC2 Positive Current Output. 75 AVDD V Analog Supply for DAC Cores. 76 CVDD V Clock Supply. Place bypass capacitors as near as possible to Pin AVDD V Analog Supply for DAC Cores. 78 OUT1+ DAC1 Positive Current Output. 79 OUT1 DAC1 Negative Current Output. 80 LDO V LDO. Requires 1 µf capacitor to ground. 81 CVDD V Clock Supply. Place bypass capacitors as near as possible to Pin LDO V LDO. Requires 1 µf capacitor to ground. 83 OUT0 DAC0 Negative Current Output. 84 OUT0+ DAC0 Positive Current Output. 85 AVDD V Analog Supply for DAC Cores. 86 I120 Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kω resistor from this pin to ground. 87 CVDD V Clock Supply. Place bypass capacitors as near as possible to Pin LDO_BYP2 LDO Clock Bypass for DAC PLL. This pin requires a 1 Ω resistor in series with a 1 µf capacitor to ground. EPAD Exposed Pad. The exposed pad must be securely connected to the ground plane. Rev. PrJ Page 13 of 150

14 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error Offset error is the deviation of the output current from the ideal of 0 ma. For OUTx±, 0 ma output is expected when all inputs are set to 0. For OUTx±, 0 ma output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25 C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Preliminary Technical Data Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fdata (interpolation rate), a digital filter can be constructed that has a sharp transition band near fdata/2. Images that typically appear around fdac (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Adjusted DAC Update Rate The adjusted DAC update rate is defined as the DAC update rate divided by the smallest interpolating factor. For clarity on DACs with multiple interpolating factors, the adjusted DAC update rate for each interpolating factor may be given. Rev. PrJ Page 14 of 150

15 TYPICAL PERFORMANCE CHARACTERISTICS 0 20 f DAC = 983MHz f DAC = 1228MHz f DAC = 1474MHz dBFS 6dBFS 9dBFS 12dBFS SFDR (dbc) SFDR (dbc) f OUT (MHz) f OUT (MHz) Figure 4. Single Tone SFDR vs. fout in the First Nyquist Zone, fdac = 983 MHz,1228 MHz, and 1474 MHz Figure 7. Harmonic vs. fout in the First Nyquist Zone over Digital Back Off, fdac = 983 MHz 0 20 f DAC = 1966MHz f DAC = 2456MHz MEDIAN dBFS 6dBFS 9dBFS 12dBFS SFDR (dbc) SFDR (dbc) f OUT (MHz) f OUT (MHz) Figure 5. Single Tone SFDR vs. fout in the First Nyquist Zone, fdac = 1966 MHz and 2456 MHz Figure 8. Harmonic vs. fout in the First Nyquist Zone over Digital Back Off, fdac = 1966 MHz 0 20 IN-BAND SECOND HARMONIC IN-BAND THIRD HARMONIC MAX DIGITAL SPUR 0 20 f DAC = 983MHz f DAC = 1228MHz f DAC = 1474MHz SFDR (dbc) IMD3 (dbc) f OUT (MHz) f OUT (MHz) Figure 6. Second and Third Harmonics and Max Digital Spur in the First Nyquist Zone, fdac = 1966 MHz, 0 db Back Off Figure 9. Two Tone Third IMD vs. fout, fdac = 983 MHz, 1228 MHz, and 1474 MHz Rev. PrJ Page 15 of 150

16 0 f DAC = 1966MHz f DAC = 2456MHz 0 f DAC = 983MHz f DAC = 1966MHz MHz TONE SPACING 16MHz TONE SPACING 35MHz TONE SPACING IMD3 (dbc) IMD3 (dbc) f OUT (MHz) f OUT (MHz) Figure 10. Two Tone Third IMD vs. fout, fdac = 1966 MHz and 2456 MHz Figure 13. Two Tone Third IMD vs. fout, over Tone Spacing at 0dB Back Off, fdac = 983 MHz and 1966 MHz dBFS 6dBFS 9dBFS 12dBFS f DAC = 983MHz f DAC = 1228MHz f DAC = 1474MHz IMD3 (dbc) NSD (dbm/hz) f OUT (MHz) f OUT (MHz) Figure 11. Two Tone Third IMD vs. fout, over Digital Back Off, fdac = 983 MHz, Each Tone 6 dbfs Figure 14. Single Tone (0 dbfs) NSD vs. fout, fdac = 983 MHz, 1228 MHz, and 1474 MHz dBFS 6dBFS 9dBFS 12dBFS f DAC = 1966MHz f DAC = 2456MHz IMD3 (dbc) NSD (dbm/hz) f OUT (MHz) f OUT (MHz) Figure 12. Two Tone Third IMD vs. fout, over Digital Back Off, fdac = 1966 MHz, Each Tone 6 dbfs Figure 15. Single Tone (0 dbfs) NSD vs. fout, fdac = 1966 MHz and 2456 MHz Rev. PrJ Page 16 of 150

17 NSD (dbm/hz) dBFS 6dBFS 9dBFS 12dBFS PHASE NOISE (dbc/hz) f OUT = 30MHz f OUT = 200MHz f OUT = 400MHz PLL: OFF PLL: ON f OUT (MHz) k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) Figure 16. Single Tone NSD vs. fout over Digital Back Off, fdac = 983 MHz Figure 19. Single Tone Phase Noise vs. Offset Frequency over fout, fdac = 2.0 GHz, PLL On and Off dBFS 6dBFS 9dBFS 12dBFS 140 NSD (dbm/hz) f OUT (MHz) Figure 17. Single Tone NSD vs. fout over Digital Back Off, fdac = 1966 MHz Figure 20. 1C WCDMA ACLR, fout = 30 MHz, fdac = 983 MHz, 2 Interpolation, PLL Frequency = 122 MHz PLL OFF PLL ON f DAC = 983MHz f DAC = 1966MHz NSD (dbm/hz) f OUT (MHz) Figure 18. Single Tone NSD (0dBFS) vs. fout,fdac = 983 MHz and 1966 MHz, PLL On and Off Figure 21. 1C WCDMA ACLR, fout = 122 MHz, fdac = 983 MHz, 2 Interpolation, PLL Frequency = 122 MHz Rev. PrJ Page 17 of 150

18 Figure 22. 4C WCDMA ACLR, fout = 30 MHz, fdac = 983 MHz, 2 Interpolation, PLL Frequency = 122 MHz Figure 25. 4C WCDMA ACLR, fout = 245 MHz, fdac = 1966 MHz, 4 Interpolation, PLL Frequency = 245 MHz TOTAL POWER (mw) Figure 23. 4C WCDMA ACLR, fout = 122 MHz, fdac = 983 MHz, 2 Interpolation, PLL Frequency = 122 MHz f DAC (MHz) Figure 26. Total Power Consumption vs. fdac over Interpolation, 8 SERDES Lanes Enabled; NCO, Digital Gain, Inverse Sinc and DAC PLL Disabled NCO PLL (f DAC /f REF RATIO:4) DIGITAL GAIN INVERSE SINC POWER (mw) Figure 24. 4C WCDMA ACLR, fout = 30 MHz, fdac = 1966 MHz, 4 Interpolation, PLL Frequency = 245 MHz f DAC (MHz) Figure 27. Power Consumption vs. fdac over Digital Functions Rev. PrJ Page 18 of 150

19 LANES 4 LANES 8 LANES 1.2V SVDD SUPPLY 1.3V SVDD SUPPLY DVDD CVDD PVDD AVDD 1.2V SUPPLY 1.3V SUPPLY 3.3V SUPPLY SVDD CURRENT (ma) CURRENT SUPPLY (ma) LANE RATE (Gbps) f DAC (MHz) Figure 28. SVDD12 Current vs. fdac over Number of SERDES Lanes Figure 29. DVDD, CVDD, PVDD, and AVDD Current vs. fdac over Supply Voltage Setting Rev. PrJ Page 19 of 150

20 THEORY OF OPERATION The is a 16-bit, quad DAC with a SERDES interface. Figure 2 shows a detailed functional block diagram of the. Eight high speed serial lanes carry data at a maximum speed of 10.6 Gbps, and a 1.06 GSPS (maximum) input data rate to the DACs. Compared to either LVDS or CMOS interfaces, the SERDES interface simplifies pin count, board layout, and input clock requirements to the device. The clock for the input data is derived from the device clock (required by the JESD204B specification). This device clock can be a PLL reference clock or a direct DAC sampling clock. The device can be configured to operate in two-, four-, or eight-lane modes, depending on the required input data rate. To add application flexibility, the quad DAC can be configured as a dual link device with each JESD204B link providing data for a dual DAC pair. The digital datapath of the offers three interpolation modes (2, 4, and 8 ) through three half-band filters with a maximum DAC sample rate of 2.8 GSPS. Inverse sinc filters are also provided to compensate for sinc related roll-off. The DAC clock can be sourced through a high fidelity external clock source, or it can be generated internally through a dedicated PLL. The DAC cores provide a fully differential current output with a nominal full-scale current of 20 ma. The full-scale current is user adjustable to any value between 14 ma and 26 ma. The differential current outputs are complementary and are optimized for easy integration with the Analog Devices ADRF672x analog quadrature modulators (AQMs). The is capable of multichip synchronization that can both synchronize multiple DACs and establish a constant latency (latency locking) path for the DACs. The latency for each of the DACs remains constant from link establishment to link establishment. An external alignment (SYSREF±) signal makes the Subclass 1 compliant. Several modes of SYSREF± signal handling are available for use in the system. A serial port interface configures the various functional blocks and monitors their statuses. The various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the Start-up Sequence section). Simple SPI initialization routines set up the JESD204B link and are included in the evaluation board package. The following sections describe the various blocks of the in greater detail. Descriptions of the JESD204B interface, control parameters, and various registers to set up and monitor the device are provided. The recommended start-up routine reliably sets up the data link. Rev. PrJ Page 20 of 150

21 SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing with many industry-standard microcontrollers and microprocessors. The serial input/output (I/O) is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the. MSB first or LSB first transfer formats are supported. The serial port interface is a 4-wire interface. A 3-wire mode is supported in which the input and output share a single-pin I/O (SDIO). SDO 62 SDIO 63 SCLK 64 CS 65 SPI PORT Figure 30. Serial Port Interface Pins There are two phases to a communication cycle with the. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 SCLK rising edges. The instruction word provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the following data transfer. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next 16 rising SCLK edges represent the instruction bits of the current I/O operation. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Eight N SCLK cycles are needed to transfer N bytes during the transfer cycle. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word (FTW) and numerically controlled oscillator (NCO) phase offsets, which change only when the frequency tuning word FTW_UPDATE_REQ bit is set. DATA FORMAT The instruction byte contains the information shown in Table 13. Table 13. Serial Port Instruction Word I15 (MSB) I[14:0] R/W A[14:0] R/W, Bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction word write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation A14 to A0, Bit 14 to Bit 0 of the instruction word, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A[14:0] is the starting address. The remaining register addresses are generated by the device based on the ADDRINC bit. If ADDRINC is set high (Register 0x00, Bit 5 and Bit 2), multibyte SPI writes start on A[14:0] and increment by 1 every 8 bits sent/received. If ADDRINC is set to 0, then the address decrements by 1 every 8 bits. SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 10 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDIO pin goes to a high impedance state when this input is high. During the communication cycle, chip select must stay low. Serial Data I/O (SDIO) This pin is a bidirectional data line. In 4-wire mode this pin acts as the data input and SDO acts as the data output. SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x0, Bit 1 and Bit 6). The default is MSB first (LSBFIRST = 0). When LSBFIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. R/W is followed by A[14:0] as the instruction word, and D[7:0] is the data-word. When LSBFIRST = 1 (LSB first), the opposite is true. A[0:14] is followed by R/W, which is subsequently followed by D[0:7]. Multibyte data transfers can be performed as well. This is done by holding the CS pin low for multiple data transfer cycles (eight SCLKs) after the first data transfer word following the instruction cycle. The first eight SCLKs following the instruction cycle reads/writes the register provided in the instruction cycle. For each additional eight SCLK cycles, the address is either incremented or decremented and the read/write occurs on the new register. The direction of the address can be set using ADDRINC (Register 0x00 Bit 5 and Bit 2. When ADDRINC is 1, the multicycle addresses are incremented. When ADDRINC is 0, the addresses are decremented. A new write cycle can always be initiated by bringing CS high and then low again. Rev. PrJ Page 21 of 150

22 To prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. This is completed independently from the LSB first bit and ensures that there are extra clock cycles following the soft reset bit (Register 0x0, Bit 0). CS SCLK t DCSB t SCLK t PWH t PWL CS INSTRUCTION CYCLE DATA TRANSFER CYCLE SDIO t DS tdh INSTRUCTION BIT 15 INSTRUCTION BIT SCLK Figure 33. Timing Diagram for Serial Port Register Write SDIO R/W A14 A13 A3 A2 A1 A0 D7 N D6 N D5 N D3 0 D2 0 D1 0 D0 0 Figure 31. Serial Register Interface Timing, MSB First, ADDRINC = CS SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE t DV CS SDIO DATA BIT n DATA BIT n SCLK Figure 34. Timing Diagram for Serial Port Register Read SDIO A0 A1 A2 A12 A13 A14 R/W D0 0 D1 0 D2 0 D4 N D5 N D6 N D7 N Figure 32. Serial Register Interface Timing, LSB First, ADDRINC = Rev. PrJ Page 22 of 150

23 JESD204B SERIAL DATA INTERFACE The has eight JESD204B data ports that receive data for both transmit paths. The eight JESD204B ports can be configured as part of a single JESD204B link or as part of two separate JESD204B links (dual link mode) that share a single system reference (SYSREF) and device clock. Figure 35 shows the communication layers implemented in the serial data interface to recover the clock and deserialize, descramble, and deframe the data before it is sent to the digital signal processing section of the device. The JESD204B serial interface hardware consists of three layers: the physical layer (or PHY), the data link layer, and the transport layer. In addition to these three layers, the JESD204B includes a PLL and SPI interface. These sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. The maximum input data rate of the is directly linked to the number of lanes used. The relation between the lane rate, sample clock, and the JESD204B configuration parameters are given by: M DataRate LaneRate = 20 L where M is the number of converters in the link, and L is the number of lanes in the link. In total, there are 10 single link modes supported by the (see Table 14). In dual link mode, there are six supported modes, (see Table 15). Each of these tables shows the associated clock rates when the lane rate is 10 Gbps. Because the can operate with up to eight active high speed serial data lanes, both achieving and recovering synchronization of the lanes are very important. To simplify the interface to the companion digital chip, the designates one master signal per JESD204B link (SYNCOUT0± and SYNCOUT1±) to support synchronization for multiple lanes. SYNCOUT0± is used in single link mode as the master for all device lanes or in dual link mode for Link 0. SYNCOUT1± is used only in dual link mode as the master for Link 1. If one lane in a JESD204B link loses synchronization, a resynchronization request is sent via SYNCOUT1± / SYNCOUT0± to the transmitter. The transmitter stops sending data and instead sends synchronization characters to all lanes in that link until resynchronization has been achieved. SYNCOUT0± SYNCOUT1± SERDIN0± PHYSICAL LAYER DESERIALIZER DATA LINK LAYER TRANSPORT LAYER IDATA0[15:0] QDATA0[15:0] QBD/ DESCRAMBLER FRAME TO SAMPLES TO DAC SERDIN7± DESERIALIZER QDATA1[15:0] IDATA1[15:0] SYSREF± Figure 35. Functional Block Diagram of Serial Link Receiver Table 14. Single Link JESD204B Operating Modes Mode Parameter M (Converter Counts) Reserved 1 1 L (Lane Counts) Reserved 2 1 S (Samples per Converter per Frame) Reserved 1 1 F (Octets per Frame per Lane) Reserved 1 2 NP (Bits per Sample) Reserved Example Clocks for 10 Gbps Lane Rate PCLK (MHz) Reserved Frame Clock (MHz) Reserved Sample Clock (MHz) Reserved Rev. PrJ Page 23 of 150

24 Table 15. Dual Link JESD204B Operating Modes for Link 0 and Link 1 Mode Parameter M (Converter Counts) Reserved 1 1 L (Lane Counts) Reserved 2 1 S (Samples per Converter per Frame) Reserved 1 1 F (Octets per Frame per Lane) Reserved 1 2 NP (Bits per Sample) Reserved Example Clocks for 10 Gbps Lane Rate PCLK (MHz) Reserved Frame Clock (MHz) Reserved Sample Clock (MHz) Reserved JESD204B SERIAL LINK ESTABLISHMENT See the following steps for a brief summary of the high speed serial link establishment process for Subclass 1. See the JESD204B specifications document, Serial Interface for Data Converters, for complete details. Step 1: Code Group Synchronization Each receiver must locate K (K28.5) characters in its input data stream. After four consecutive K characters are detected on all link lanes, the receiver block deasserts the SYNCOUTx± signal to the transmitter block at the receiver local multiframe clock (LMFC) edge. The transmitter captures the change in the SYNCOUTx± signal, and at a future transmitter LMFC rising edge, starts the initial lane alignment sequence (ILAS). For additional information on software synchronization methodology, see the Input Signal Power Detection and Protection section. Step 2: Initial Lane Alignment Sequence The main purposes of this phase are to align all the lanes of the link and verify the parameters of the link. Before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. The ILAS consists of four or more multiframes. The last character of each multiframe is a multiframe alignment character, /A/. The first, third, and fourth multiframes are populated with predetermined data values. The deframer uses the final /A/ of each lane to align the ends of the multiframes within the receiver. The second multiframe contains an R (K.28.0), Q (K.28.4), and then data corresponding to the link parameters. Additional multiframes can be added to the ILAS if needed by the receiver. The uses four multiframes in its ILAS. After the last /A/ character of the last ILAS, multiframe data begins streaming. The receiver adjusts the position of the /A/ character such that it aligns with the internal LMFC of the receiver at this point. Step 3: Data Streaming In this phase, data streams from the transmitter block to the receiver block. Optionally, data can be scrambled. Scrambling does not start until the very first octet following the ILAS. The receiver block processes and monitors the data it receives for errors, including Bad running disparity (8-bit/10-bit error) Not in table (8-bit/10-bit error) Unexpected control character Bad ILAS Interlane skew error (through character replacement) If any of these errors exist, they are reported back to the transmitter in one of a few ways. SYNCOUTx± signal assertion: Resynchronization (SYNCOUTx± signal pulled low) is requested at each error. For the first three errors, the SYNCOUTx± signal is asserted after an error counter reaches a given error threshold. SYNCOUTx± signal reporting: SYNCOUTx± signal is pulsed low for a programmable number of frame clock (FCLK) periods at the end of an LMFC if an error occurs. Reporting can also be performed via an interrupt (not covered by the JESD204B specification). See the SYNCOUTx± signal assertion method for error thresholds. Rev. PrJ Page 24 of 150

25 DESERIALIZER Termination Calibration Settings Table 16 lists the registers that are related to the termination calibration settings. All registers are read/write access, unless otherwise indicated. Register 0x2AA, Register 0x2AB and Register 0x2B1 and Register 0x2B2 should be changed from default for best performance. See register descriptions in Table 16 for details. The physical layer of the JESD204B interface, hereafter referred to as the deserializer, has eight identical channels. Each channel consists of the terminators, an equalizer, a clock and data recovery (CDR) circuit, and the 1:40 demux function (see Figure 36). JESD204B data is input to the via the SERDINx± 1.2 V differential input pins compliant to the JESD204B specification. DESERIALIZER SERDINx± TERMINATION EQUALIZER CDR 1:40 SPI CONTROL FROM PLL Table 16. Termination Registers Register Address 0x2A7 0x2AA 0x2AB 0x2AE 0x2B1 0x2B2 Figure 36. Deserializer Block Diagram Register Name Bit No. Bit Name Settings Description Reset Access TERM_BLK1_ [7:6] RESERVED Reserved. 0x0 R CTRLREG0 [5:2] RESERVED Reserved. 0x0 R/W 1 RESERVED Reserved. 0x0 R/W TERM_BLK1_ CTRLREG3 TERM_BLK1_ CTRLREG4 TERM_BLK2_ CTRLREG0 TERM_BLK2_ CTRLREG3 TERM_BLK2_ CTRLREG4 0 SPI_I_TUNE_R_ CAL_TERMBLK1 [7:0] SPI_I_SLOW_ CONDUCTANCE_ TERMBLK1 [7:0] SPI_I_FAST_ CONDUCTANCE_ TERMBLK1 Termination Calibration. The rising edge of this bit starts a termination calibration routine. Termination Control for PHY 0, PHY 1, PHY 6, and PHY 7. Change from default to be 0xB7. Termination Control for PHY 0, PHY 1, PHY 6, and PHY 7. Change from default to be 0x87. [7:6] RESERVED Reserved. 0x0 R [5:2] RESERVED Reserved. 0x0 R/W 1 RESERVED Reserved. 0x0 R/W 0 SPI_I_TUNE_R_CAL_TERMBLK2 Terminal Calibration. The rising edge of this bit starts a termination calibration routine. 0x0 R/W [7:0] SPI_I_SLOW_ CONDUCTANCE_ TERMBLK2 [7:0] SPI_I_FAST_ CONDUCTANCE_ TERMBLK2 Termination Control for PHY 2, PHY 3, PHY 4, and PHY 5. Change from default to be 0xB7. Termination Control for PHY 2, PHY 3, PHY 4, and PHY 5. Change from default to be 0x87. 0x0 0xC3 0x93 0xC3 0x93 R/W R/W R/W R/W R/W Rev. PrJ Page 25 of 150