קורס Achieving Timing Closure in ALTERA FPGAs
|
|
- Alfred Patrick
- 6 years ago
- Views:
Transcription
1 קורס Achieving Timing Closure in ALTERA FPGAs תיאור הקורס קורסזהמספקאתכלהידע התיאורטיוהמעשילכתיבתאילוצימערכת לתכנוניםמגווניםברכיבי ALTERA עלמנתלעמודבדרישותהפרויקט. הקורס מעמיק מאוד ונוגע בכל אספקט של תדר, כניסות/יציאות של הרכיב, מקום, והספק, ניתוח ופתרון בעיות במסגרת הנושאים הנדרשים בפרויקטים בתעשייה. הקורס משדרג גם מהנדסים עם הרבה שנות ניסיון בתחום. הקורסמתחילבסקירתתהליךה-,STATIC TIMING ANALYSIS ממשיך בלימודמתודימעמיקשל כתיבת אילוציםלקובץ,SDC משלבכתיבהוהרצתתכניות בדיקהבכליסימולציהלאחר. P&R בנוסףהקורסמשלבדוגמאות שלתכנוניםמורכבים כמואילוציםמול רכיביזיכרוןמהירים ADC,DDR, SERDES, העברתשעוןו- DATA עםפאזהקבועהביניהם, אילוציםלמערכותמרובות שעונים, בעיות זמניםבשימוש. IP לסיום, הקורסמלמדכיצד להפיקדו"חותמתקדמים, כיצדלנתחבעיותמסוגים שוניםוכיצדלפתור אותןברמתקוד VHDL וברמתהכליםהמשולביםבתוכנת QUARTUS II הקורסמשלב 50% תיאוריהו- 50% עבודהמעשיתבכלמפגש. המעבדותמכסותאתכלהחומר התאורטיומשלבות חשיבהותכנוןדיגיטאלימעשי. אורך הקורס 4 ימים (אופציה ליום חמישי עם תרגול של פרויקט מורכב) בסיום הקורס מטרות שיושגו הכרתתהליךהתכנוןבעזרת TimeQuest.1 תפעולהכלי TimeQuest.2 יצירתקובץ SDC והפקתדו"חות 3. הכרתמושגייסודב- TimeQuest 4. כתיבתאילוציםלשעונים 5. כתיבתאילוציםל- I/O 6. כתיבת אילוציםלסיגנליםאסינכרוניים 7. כתיבתאילוצי False path ו- multicycle path.8 כתיבתאילוצים למעגליםמורכבים כתיבתאילוציםלמערכת המתממשקתלרכיביםבתדרגבוה 11. שימושמתקדםבכלי Quartus II לאופטימיזציהשלמקום, תדר וזמן 12. ניתוח בעיותופתרונןבעבודתצוות
2 מי צריך להירשם? מהנדסיFPGA בסביבתQUARTUS הרוציםלהתמקצעברמה גבוההבכתיבתאילוצים, ולנתחאת התכנוןברמההמעמיקהביותר. כלי פיתוח בקורס.1 סינטיסייזרו- route (Quartus II) Place & תכנית הלימוד Day #1 Introduction to Timing Analysis o TimeQuest tool overview o Basic steps to using TimeQuest (generate timing netlist, enter SDC constraints, update timing netlist, generate timing reports) o Using TimeQuest in Quartus II flow o Timing analysis basics (Launch Vs Latch edges, setup and hold times, data and clock arrival time, data required time, setup and hold slack analysis, I/O analysis, recovery and removal, timing models) Timing Reports o Reporting in Quartus II Vs reporting in TimeQuest o Custom, summary and diagnostic reports o Clock transfer, datasheet, Fmax reports o Slack histogram report o Detailed slack/path report, further path analysis Introduction to Timing Constraints o Importance of constraining o Enter constraints o SDC netlist terminology o Collections SDC Timing Constraints o Internal and virtual clocks o Generated clocks (inverted clocks, phase shifted clocks
3 o PLL clocks and derive_pll_clocks Altera SDC extension o Automatic clock detection and creation o Non ideal clock constraints (Jitter, latency on PCB) o Common clock path pessimism removal o Checking clock constraints o Report clocks Day #2 SDC Timing Constraints for I/O o Combinational I/O interface constraints (max & min delay constraints) o Synchronous inputs constraints (setup and hold time calculations, set_input_delay max & min, set_output_delay min& max, when to use each constraint, output pin load, signal integrity metrices) o Source synchronous interface constraints (SDR Source synchronous input center aligned, using SDC with source synchronous input, SDR source synchronous output center aligned, source synchronous edge aligned) o Checking I/O constraints (report SDC, report unconstrained path, report ignored constraint) Asynchronous Path Constraints o Asynchronous path definition o TimeQuest and asynchronous ports o Recovery and removal constraints o Externally registered asynchronous paths constraints o Internally registered asynchronous paths constraints o Checking and reporting asynchronous control constraints o Truly asynchronous control inputs o The problem with latches Timing exception o False path constraints (logic based, timing based, set_clock_groups and set_false_path commands, clock mux constraints, synchronizers constraints, FIFO constraints) o Verifying false paths and groups o Multicycle path constraints (multicycle types, multicycle setup and hold, multicycle with and without enable signal, positive clock phase shift or offset, source clock at higher frequency) o Reporting multicycles
4 o Absolute and annotated delays constraints Day #3 Application Constraints o DDR input constraints & reporting o Reset synchronizer constraints & reporting o Externally switched clocks constraints o PLL clock switchover constraints o Multiple virtual clocks in I/O constraints o I/O timing requirements Tsetup, Tco, Th o JTAG signals constraints o Tri-state outputs constraints o Input and output delays with multiple clocks o High performance FPGA PLL analysis with TimeQuest o LVDS SERDES constraints (TCCS and RSKM) o Design reuse with dynamic SDC constraints o Analyzing timing of external memory (DDR,DDR2,DDR3) o 10/100/1000 RGMII Ethernet constraints o QDRII+ SRAM constraints o ADC constraints
5 Day #4 Achieving Timing Closure o Frequency problems & solutions (long combinational path, fanout, place & route issues, global signals, synchronous vs asynchronous generated signals, pipeline) o Clock domain problems (where to place and constrain the synchronizers) o I/O problems (I/O registers, lock the delay chain settings for I/O cells, PLL shifting to meet I/O timing, slew rate) Achieving Timing Closure in Team Based Designs o Design partitioning with incremental compilation o Logic lock o Hierarchical design rules o Design space explorer o Floorplanning assignments o ECO (Engineering Change Order) o Missing timing constraints o Conflicting timing constraints o Overly restrictive location constraints Day #5 (optional) Putting All Together o During this day you will get a project with several design problems like area, timing, synchronization, power and others o Your task is to use all course material to achieve timing closure o The project makes use of the most topics discussed during the course o This is Hands On full day which gives you the confidence to analyze and solve area, timing, and power problems
Achieving Timing Closure in ALTERA FPGAs
Achieving Timing Closure in ALTERA FPGAs Course Description This course provides all necessary theoretical and practical know-how to write system timing constraints for variety designs in ALTERA FPGAs.
More informationTimeQuest User Guide
TimeQuest User Guide Wiki Release 1.1 December 9th 2010 By: Ryan Scoville Introduction: I have spent a good amount of time over the last few years helping designers with TimeQuest, and found myself writing
More informationIntel Quartus Prime Timing Analyzer Cookbook
2017.11.21 Intel Quartus Prime Timing Analyzer Cookbook MNL-01035 Subscribe This manual contains a collection of design scenarios, constraint guidelines, and recommendations. You must be familiar with
More informationStatic Timing Analysis for Nanometer Designs
J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach 4y Spri ringer Contents Preface xv CHAPTER 1: Introduction / 1.1 Nanometer Designs 1 1.2 What is Static Timing
More information9. Synopsys PrimeTime Support
9. Synopsys PrimeTime Support December 2010 QII53005-10.0.1 QII53005-10.0.1 PrimeTime is the Synopsys stand-alone full chip, gate-level static timing analyzer. The Quartus II software makes it easy for
More informationFPGA TechNote: Asynchronous signals and Metastability
FPGA TechNote: Asynchronous signals and Metastability This Doulos FPGA TechNote gives a brief overview of metastability as it applies to the design of FPGAs. The first section introduces metastability
More informationStatic Timing Analysis for Nanometer Designs. A Practical Approach
Static Timing Analysis for Nanometer Designs A Practical Approach J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach J. Bhasker Rakesh Chadha esilicon Corporation
More informationCHAPTER 3 EXPERIMENTAL SETUP
CHAPTER 3 EXPERIMENTAL SETUP In this project, the experimental setup comprised of both hardware and software. Hardware components comprised of Altera Education Kit, capacitor and speaker. While software
More informationUsing the Quartus II Chip Editor
Using the Quartus II Chip Editor June 2003, ver. 1.0 Application Note 310 Introduction Altera FPGAs have made tremendous advances in capacity and performance. Today, Altera Stratix and Stratix GX devices
More informationDEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING DIGITAL DESIGN
DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING DIGITAL DESIGN Assoc. Prof. Dr. Burak Kelleci Spring 2018 OUTLINE Synchronous Logic Circuits Latch Flip-Flop Timing Counters Shift Register Synchronous
More informationUsing SignalTap II in the Quartus II Software
White Paper Using SignalTap II in the Quartus II Software Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera Quartus II software version 2.1, helps reduce verification
More informationTKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
More informationLaboratory 4. Figure 1: Serdes Transceiver
Laboratory 4 The purpose of this laboratory exercise is to design a digital Serdes In the first part of the lab, you will design all the required subblocks for the digital Serdes and simulate them In part
More informationFPGA Design. Part I - Hardware Components. Thomas Lenzi
FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise
More informationDE2-115/FGPA README. 1. Running the DE2-115 for basic operation. 2. The code/project files. Project Files
DE2-115/FGPA README For questions email: jeff.nicholls.63@gmail.com (do not hesitate!) This document serves the purpose of providing additional information to anyone interested in operating the DE2-115
More informationCSCB58 - Lab 4. Prelab /3 Part I (in-lab) /1 Part II (in-lab) /1 Part III (in-lab) /2 TOTAL /8
CSCB58 - Lab 4 Clocks and Counters Learning Objectives The purpose of this lab is to learn how to create counters and to be able to control when operations occur when the actual clock rate is much faster.
More informationFPGA Development for Radar, Radio-Astronomy and Communications
John-Philip Taylor Room 7.03, Department of Electrical Engineering, Menzies Building, University of Cape Town Cape Town, South Africa 7701 Tel: +27 82 354 6741 email: tyljoh010@myuct.ac.za Internet: http://www.uct.ac.za
More informationImplementing Audio IP in SDI II on Arria V Development Board
Implementing Audio IP in SDI II on Arria V Development Board AN-697 Subscribe This document describes a reference design that uses the Audio Embed, Audio Extract, Clocked Audio Input and Clocked Audio
More informationFSM Cookbook. 1. Introduction. 2. What Functional Information Must be Modeled
FSM Cookbook 1. Introduction Tau models describe the timing and functional information of component interfaces. Timing information specifies the delay in placing values on output signals and the timing
More informationLevel and edge-sensitive behaviour
Level and edge-sensitive behaviour Asynchronous set/reset is level-sensitive Include set/reset in sensitivity list Put level-sensitive behaviour first: process (clock, reset) is begin if reset = '0' then
More informationEE 447/547 VLSI Design. Lecture 9: Sequential Circuits. VLSI Design EE 447/547 Sequential circuits 1
EE 447/547 VLSI esign Lecture 9: Sequential Circuits Sequential circuits 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking Sequential
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationCPE/EE 427, CPE 527 VLSI Design I Sequential Circuits. Sequencing
CPE/EE 427, CPE 527 VLSI esign I Sequential Circuits epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) Combinational
More informationSystem IC Design: Timing Issues and DFT. Hung-Chih Chiang
System IC esign: Timing Issues and FT Hung-Chih Chiang Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability
More informationMemory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George
Application Note: Virtex-4 Family R XAPP701 (v1.4) October 2, 2006 Memory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George Summary This application note describes the direct-clocking
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton*, Mark R. Greenstreet, Steven J.E. Wilton*, *Dept. of Electrical and Computer Engineering, Dept.
More informationLOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta
LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES Masum Hossain University of Alberta 0 Outline Why ADC-Based receiver? Challenges in ADC-based receiver ADC-DSP based Receiver Reducing impact of Quantization
More informationClocking Spring /18/05
ing L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle L06 s 2 igital Systems Timing Conventions All digital systems need a convention
More informationEN2911X: Reconfigurable Computing Topic 01: Programmable Logic. Prof. Sherief Reda School of Engineering, Brown University Fall 2014
EN2911X: Reconfigurable Computing Topic 01: Programmable Logic Prof. Sherief Reda School of Engineering, Brown University Fall 2014 1 Contents 1. Architecture of modern FPGAs Programmable interconnect
More informationDEDICATED TO EMBEDDED SOLUTIONS
DEDICATED TO EMBEDDED SOLUTIONS DESIGN SAFE FPGA INTERNAL CLOCK DOMAIN CROSSINGS ESPEN TALLAKSEN DATA RESPONS SCOPE Clock domain crossings (CDC) is probably the worst source for serious FPGA-bugs that
More informationMemory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George
Application Note: Virtex-4 Family XAPP701 (v1.3) September 13, 2005 Memory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George Summary This application note describes the direct-clocking
More informationDC Ultra. Concurrent Timing, Area, Power and Test Optimization. Overview
DATASHEET DC Ultra Concurrent Timing, Area, Power and Test Optimization DC Ultra RTL synthesis solution enables users to meet today s design challenges with concurrent optimization of timing, area, power
More informationPartial Reconfiguration IP Core User Guide
Partial Reconfiguration IP Core User Guide ug-partrecon 2016.10.31 Subscribe Send Feedback Contents Contents 1 Partial Reconfiguration IP Core... 3 1.1 Instantiating the Partial Reconfiguration IP Core
More informationSynchronization Issues During Encoder / Decoder Tests
OmniTek PQA Application Note: Synchronization Issues During Encoder / Decoder Tests Revision 1.0 www.omnitek.tv OmniTek Advanced Measurement Technology 1 INTRODUCTION The OmniTek PQA system is very well
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. CPU design and PLDs. Tajana Simunic Rosing. Source: Vahid, Katz
CSE140L: Components and Design Techniques for Digital Systems Lab CPU design and PLDs Tajana Simunic Rosing Source: Vahid, Katz 1 Lab #3 due Lab #4 CPU design Today: CPU design - lab overview PLDs Updates
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing q Two-Phase Clocking 2 Sequencing q Combinational logic output depends
More informationRemote Diagnostics and Upgrades
Remote Diagnostics and Upgrades Tim Pender -Eastman Kodak Company 10/03/03 About this Presentation Motivation for Remote Diagnostics Reduce Field Maintenance costs Product needed to support 100 JTAG chains
More informationLecture #4: Clocking in Synchronous Circuits
Lecture #4: Clocking in Synchronous Circuits Kunle Stanford EE183 January 15, 2003 Tutorial/Verilog Questions? Tutorial is done, right? Due at midnight (Fri 1/17/03) Turn in copies of all verilog, copy
More informationLaboratory Exercise 7
Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines. Part I We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied
More informationECEN454 Digital Integrated Circuit Design. Sequential Circuits. Sequencing. Output depends on current inputs
ECEN454 igital Integrated Circuit esign Sequential Circuits ECEN 454 Combinational logic Sequencing Output depends on current inputs Sequential logic Output depends on current and previous inputs Requires
More information2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family
December 2011 CIII51002-2.3 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family CIII51002-2.3 This chapter contains feature definitions for logic elements (LEs) and logic array blocks
More informationHDL & High Level Synthesize (EEET 2035) Laboratory II Sequential Circuits with VHDL: DFF, Counter, TFF and Timer
1 P a g e HDL & High Level Synthesize (EEET 2035) Laboratory II Sequential Circuits with VHDL: DFF, Counter, TFF and Timer Objectives: Develop the behavioural style VHDL code for D-Flip Flop using gated,
More informationPage 1 of 6 Follow these guidelines to design testable ASICs, boards, and systems. (includes related article on automatic testpattern generation basics) (Tutorial) From: EDN Date: August 19, 1993 Author:
More informationEE273 Lecture 11 Pipelined Timing Closed-Loop Timing November 2, Today s Assignment
EE273 Lecture 11 Pipelined Timing Closed-Loop Timing November 2, 1998 William J. ally Computer Systems Laboratory Stanford University billd@csl.stanford.edu Copyright (C) by William J. ally, All Rights
More informationScan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
More informationCyclone II EPC35. M4K = memory IOE = Input Output Elements PLL = Phase Locked Loop
FPGA Cyclone II EPC35 M4K = memory IOE = Input Output Elements PLL = Phase Locked Loop Cyclone II (LAB) Cyclone II Logic Element (LE) LAB = Logic Array Block = 16 LE s Logic Elements Another special packing
More informationEE141-Fall 2010 Digital Integrated Circuits. Announcements. Synchronous Timing. Latch Parameters. Class Material. Homework #8 due next Tuesday
EE-Fall 00 Digital tegrated Circuits Timing Lecture Timing Announcements Homework #8 due next Tuesday Synchronous Timing Project Phase plan due this Sat. Hanh-Phuc s extra office hours shifted next week
More informationAN-822 APPLICATION NOTE
APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com Synchronization of Multiple AD9779 Txs by Steve Reine and Gina Colangelo
More informationSignalTap Analysis in the Quartus II Software Version 2.0
SignalTap Analysis in the Quartus II Software Version 2.0 September 2002, ver. 2.1 Application Note 175 Introduction As design complexity for programmable logic devices (PLDs) increases, traditional methods
More informationLFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller
XAPP22 (v.) January, 2 R Application Note: Virtex Series, Virtex-II Series and Spartan-II family LFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller Summary Linear Feedback
More informationFPGA Laboratory Assignment 4. Due Date: 06/11/2012
FPGA Laboratory Assignment 4 Due Date: 06/11/2012 Aim The purpose of this lab is to help you understanding the fundamentals of designing and testing memory-based processing systems. In this lab, you will
More informationSynchronous Sequential Design
Synchronous Sequential Design SMD098 Computation Structures Lecture 4 1 Synchronous sequential systems Almost all digital systems have some concept of state the outputs of a system depends on the past
More informationClock - key to synchronous systems. Topic 7. Clocking Strategies in VLSI Systems. Latch vs Flip-Flop. Clock for timing synchronization
Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationClock - key to synchronous systems. Lecture 7. Clocking Strategies in VLSI Systems. Latch vs Flip-Flop. Clock for timing synchronization
Clock - key to synchronous systems Lecture 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationFeedback Sequential Circuits
Feedback Sequential Circuits sequential circuit output depends on 1. current inputs 2. past sequence of inputs current state feedback sequential circuit uses ordinary gates and feedback loops to create
More informationQuad ADC EV10AQ190A Synchronization of Multiple ADCs
Synchronization of Multiple ADCs Application Note Applies to EV10AQ190A 1. Introduction This application note provides some recommendations for the correct synchronization of multiple EV10AQ190A Quad 10-bit
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks core is a full function equivalent to the Motorola MC6845 device. The interfaces a microprocessor to a raster-scan CRT display. The
More informationVARIABLE FREQUENCY CLOCKING HARDWARE
VARIABLE FREQUENCY CLOCKING HARDWARE Variable-Frequency Clocking Hardware Many complex digital systems have components clocked at different frequencies Reason 1: to reduce power dissipation The active
More informationT1 Deframer. LogiCORE Facts. Features. Applications. General Description. Core Specifics
November 10, 2000 Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: support@xilinx.com URL: www.xilinx.com/ipcenter Features Supports T1-D4 and T1-ESF
More informationLast time, we saw how latches can be used as memory in a circuit
Flip-Flops Last time, we saw how latches can be used as memory in a circuit Latches introduce new problems: We need to know when to enable a latch We also need to quickly disable a latch In other words,
More informationGood afternoon! My name is Swetha Mettala Gilla you can call me Swetha.
Good afternoon! My name is Swetha Mettala Gilla you can call me Swetha. I m a student at the Electrical and Computer Engineering Department and at the Asynchronous Research Center. This talk is about the
More informationEE178 Spring 2018 Lecture Module 5. Eric Crabill
EE178 Spring 2018 Lecture Module 5 Eric Crabill Goals Considerations for synchronizing signals Clocks Resets Considerations for asynchronous inputs Methods for crossing clock domains Clocks The academic
More informationInnovative Fast Timing Design
Innovative Fast Timing Design Solution through Simultaneous Processing of Logic Synthesis and Placement A new design methodology is now available that offers the advantages of enhanced logical design efficiency
More information3. Configuration and Testing
3. Configuration and Testing C51003-1.4 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan
More information4 or 8 channel 24-bit audio A/D converter with analog and AES/EBU inputs COPYRIGHT 2017 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED
ADC44 ADC48 4 or 8 channel 24-bit audio converter with analog and AES/EBU inputs A Synapse product COPYRIGHT 2017 AXON DIGITAL DESIGN BV ALL RIGHTS RESERVED NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN
More informationLaboratory Exercise 7
Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines. Part I We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x576 (625/50 Video System)
More informationEECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review. Announcements
EECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review September 1, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150
More informationAltera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
2015.12.18 Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report AN-749 Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B
More informationSub-LVDS-to-Parallel Sensor Bridge
January 2015 Introduction Reference Design RD1122 Sony introduced the IMX036 and IMX136 sensors to support resolutions up to 1080P60 and 1080p120 respectively. A traditional CMOS parallel interface could
More informationSystem-Level Timing Closure Using IBIS Models
System-Level Timing Closure Using IBIS Models Barry Katz President/CTO, SiSoft Asian IBIS Summit Asian IBIS Summit Tokyo, Japan - October 31, 2006 Signal Integrity Software, Inc. Agenda High Speed System
More informationEE178 Lecture Module 4. Eric Crabill SJSU / Xilinx Fall 2005
EE178 Lecture Module 4 Eric Crabill SJSU / Xilinx Fall 2005 Lecture #9 Agenda Considerations for synchronizing signals. Clocks. Resets. Considerations for asynchronous inputs. Methods for crossing clock
More informationAt-speed Testing of SOC ICs
At-speed Testing of SOC ICs Vlado Vorisek, Thomas Koch, Hermann Fischer Multimedia Design Center, Semiconductor Products Sector Motorola Munich, Germany Abstract This paper discusses the aspects and associated
More informationSequential Circuit Design: Part 1
Sequential ircuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking locked inverters Krish hakrabarty 1 Sequential Logic FFs
More informationBlock Diagram. 16/24/32 etc. pixin pixin_sof pixin_val. Supports 300 MHz+ operation on basic FPGA devices 2 Memory Read/Write Arbiter SYSTEM SIGNALS
Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC or SoC Supplied as human readable VHDL (or Verilog) source code Output supports full flow control permitting
More informationAgilent Technologies. N5106A PXB MIMO Receiver Tester. Error Messages. Agilent Technologies
Agilent Technologies N5106A PXB MIMO Receiver Tester Messages Agilent Technologies Notices Agilent Technologies, Inc. 2008 2009 No part of this manual may be reproduced in any form or by any means (including
More informationSoC Design Flow from DFT Engineers angle
SoC Design Flow from DFT Engineers angle Kang, Yong-Seok DIS Gr. / System IC Business Team Agenda General SoC Design Flow and Guide DFT & Design Flow DFT Flow Conclusion SoC Design Flow N MRD Architecture
More informationAN 848: Implementing Intel Cyclone 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design
AN 848: Implementing Intel Cyclone 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on
More informationDigital System Design
Digital System Design by Dr. Lesley Shannon Email: lshannon@ensc.sfu.ca Course Website: http://www.ensc.sfu.ca/~lshannon/courses/ensc350 Simon Fraser University Slide Set: 8 Date: February 9, 2009 Timing
More informationTSIU03: Lab 3 - VGA. Petter Källström, Mario Garrido. September 10, 2018
Petter Källström, Mario Garrido September 10, 2018 Abstract In the initialization of the DE2-115 (after you restart it), an image is copied into the SRAM memory. What you have to do in this lab is to read
More informationSerial Digital Interface Reference Design for Stratix IV Devices
Serial Digital Interface Reference Design for Stratix IV Devices AN-600-1.2 Application Note The Serial Digital Interface (SDI) reference design shows how you can transmit and receive video data using
More informationCalifornia State University, Bakersfield Computer & Electrical Engineering & Computer Science ECE 3220: Digital Design with VHDL Laboratory 7
California State University, Bakersfield Computer & Electrical Engineering & Computer Science ECE 322: Digital Design with VHDL Laboratory 7 Rational: The purpose of this lab is to become familiar in using
More informationGlobal Trigger Trigger meeting 27.Sept 00 A.Taurok
Global Trigger Trigger meeting 27.Sept 00 A.Taurok Global Trigger Crate GT crate VME 9U Backplane 4 MUONS parallel CLOCK, BC_Reset... READOUT _links PSB 12 PSB 12 24 4 6 GT MU 6 GT MU PSB 12 PSB 12 PSB
More informationEE141-Fall 2010 Digital Integrated Circuits. Announcements. Homework #8 due next Tuesday. Project Phase 3 plan due this Sat.
EE141-Fall 2010 Digital Integrated Circuits Lecture 24 Timing 1 1 Announcements Homework #8 due next Tuesday Project Phase 3 plan due this Sat. Hanh-Phuc s extra office hours shifted next week Tues. 3-4pm
More informationFPGA Design with VHDL
FPGA Design with VHDL Justus-Liebig-Universität Gießen, II. Physikalisches Institut Ming Liu Dr. Sören Lange Prof. Dr. Wolfgang Kühn ming.liu@physik.uni-giessen.de Lecture Digital design basics Basic logic
More informationAsynchronous inputs. 9 - Metastability and Clock Recovery. A simple synchronizer. Only one synchronizer per input
9 - Metastability and Clock Recovery Asynchronous inputs We will consider a number of issues related to asynchronous inputs, multiple clock domains, clock synchronisation and clock distribution. Useful
More informationDesign of Vision Embedded Platform with AVR
Design of Vision Embedded Platform with AVR 1 In-Kyu Jang, 2 Dai-Tchul Moon, 3 Hyoung-Kie Yoon, 4 Jae-Min Jang, 5 Jeong-Seop Seo 1 Dept. of Information & Communication Engineering, Hoseo University, Republic
More informationChapter 6. sequential logic design. This is the beginning of the second part of this course, sequential logic.
Chapter 6. sequential logic design This is the beginning of the second part of this course, sequential logic. equential logic equential circuits simple circuits with feedback latches edge-triggered flip-flops
More informationDigilent Nexys-3 Cellular RAM Controller Reference Design Overview
Digilent Nexys-3 Cellular RAM Controller Reference Design Overview General Overview This document describes a reference design of the Cellular RAM (or PSRAM Pseudo Static RAM) controller for the Digilent
More informationPrototyping an ASIC with FPGAs. By Rafey Mahmud, FAE at Synplicity.
Prototyping an ASIC with FPGAs By Rafey Mahmud, FAE at Synplicity. With increased capacity of FPGAs and readily available off-the-shelf prototyping boards sporting multiple FPGAs, it has become feasible
More informationIBIS4.2 and VHDL-AMS for SERDES and DDR2 Analysis
IBIS4.2 and VHDL-AMS for SERDES and DDR2 Analysis Ian Dodd Architect, High Speed Tools Ian_dodd@mentor.com Gary Pratt Manager, High Speed Partnerships gary_pratt@mentor.com 31 st October 2006 Mentor Graphics
More informationCDA 4253 FPGA System Design FPGA Architectures. Hao Zheng Dept of Comp Sci & Eng U of South Florida
CDA 4253 FPGA System Design FPGA Architectures Hao Zheng Dept of Comp Sci & Eng U of South Florida FPGAs Generic Architecture Also include common fixed logic blocks for higher performance: On-chip mem.
More informationSingle Channel LVDS Tx
April 2013 Introduction Reference esign R1162 Low Voltage ifferential Signaling (LVS) is an electrical signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It
More informationMetastability Analysis of Synchronizer
Forn International Journal of Scientific Research in Computer Science and Engineering Research Paper Vol-1, Issue-3 ISSN: 2320 7639 Metastability Analysis of Synchronizer Ankush S. Patharkar *1 and V.
More informationEEM Digital Systems II
ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM 334 - Digital Systems II LAB 3 FPGA HARDWARE IMPLEMENTATION Purpose In the first experiment, four bit adder design was prepared
More informationSequential Circuit Design: Part 1
Sequential Circuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking Clocked inverters James Morizio 1 Sequential Logic FFs
More informationUnit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
More informationSingMai Electronics SM06. Advanced Composite Video Interface: HD-SDI to acvi converter module. User Manual. Revision 0.
SM06 Advanced Composite Video Interface: HD-SDI to acvi converter module User Manual Revision 0.4 1 st May 2017 Page 1 of 26 Revision History Date Revisions Version 17-07-2016 First Draft. 0.1 28-08-2016
More informationLaboratory Exercise 4
Laboratory Exercise 4 Polling and Interrupts The purpose of this exercise is to learn how to send and receive data to/from I/O devices. There are two methods used to indicate whether or not data can be
More information