ELEN Electronique numérique

Transcription

1 ELEN Electronique numérique Patricia ROUSSEAUX Année académique

2 CHAPITRE 6 Registers and Counters ELEN

3 Design of a modulo-8 binary counter using JK Flip-flops 3 bits are required = 3 flip-flops State table Present State Next State Flip-flop inputs Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 J 2 K 2 J 1 K 1 J 0 K X 0 X 1 X X 1 X X X X 0 1 X X X 1 X X 0 0 X 1 X X 0 1 X X X 0 X 0 1 X X 1 X 1 X 1 Flip-flop inputs are derived from the excitation table Q(t) Q(t + 1) J K X X 1 0 X X 0 ELEN

4 Flip-flop input equations J 2 = Q 1 Q 0 J 1 = Q 0 J 0 = 1 K i = J i, i = 0, 1, 2 ELEN

5 Initialization The counter has to be initialized This has to be done synchronously A general counter can be used, using the Load mode For incomplete state sequence (e.g. BCD counter), the system has to be initialized at a valid state Never use the asynchronous flip-flop inputs to initialize the counter in normal operation This should be done only at power-up or reset conditions ELEN

6 A very bad practice We want to build a modulo-7 counter We use a general 4-bit counter : detect state 7 : 0111 and after detection use the clear input of the counter to go back to state 0000 But, the clear input acts directly on the asynchronous reset inputs of the flip-flops state 7 is transitory and the transition to 0000 will not happen at a clock edge Existence of state 7 may not be long enough to reliably reset all flip-flops to 0. Referred to as a suicide counter! ELEN

7 A better solution Detect state 6 : 0110 with Q 2 Q 1 This set load to 1 The 0000 present on the inputs D 3 to D 1 are loaded The counter switches synchronously to state 0000 as required ELEN

8 1 Registers 1.1 Storage registers 1.2 Shift registers 1.3 General purpose register 2 Counters 2.1 Asynchronous counter 2.2 Synchronous counter 2.3 Serial and parallel counters 3 Register transfers 3.1 Datapath, control unit and microoperations 3.2 Register transfer operations and RTL language 3.3 Microoperations 3.4 Register transfers design 3.5 Bus-based transfers 3.6 Serial operations ELEN

9 Datapath, control unit and microoperations The information stored in a digital system can be classified as data or control information The system is accordingly split into two parts : the datapath which performs data processing operations the control unit which determines the sequence of operations The datapath is defined by its registers and the operations performed on the data stored in the registers An elementary operation is called a microoperation : e.g. loading of data into one register, transferring data between two registers, adding the contents of two registers,... ELEN

10 Datapath and control unit communication Control and status signals allow the communication between the two parts : the control unit feeds the datapath with the control signals that characterize the operation to be performed the control unit receives status signals from the datapath the status signals inform the control unit about the state of the datapath this information is used by the control unit to determine the values of the control signals Additional signals, control inputs and control outputs, interact with other parts of the whole system Data can also be interchanged through data inputs and data outputs ELEN

11 Microoperations A microoperation is an elementary operation acting identically on all bits of the register and lasting a clock cycle at most. Microoperations can be classified into 4 categories : transfer : copy the data from one register to another arithmetic : perform arithmetic operation on data in registers (+,-,1 s complement,...) logic : manipulate data or use bitwise operation (and,or,...) shift : shift data in registers ELEN

12 Transfer operation and Register Transfer Language (RTL) Manipulation of registers use a particular notation denoted by Register Transfer Language letters and numbers denote a register : R2, PC,... parentheses are used to limit a range of register bits : R1(3), R2(1 : 4), PC(L) A data transfer is denoted by an arrow : R2 R1 : the contents of R1 is copied into R2 the contents of R1 is unchanged the transfer should be done in one clock cycle (microoperation) A transfer assumes that datapath circuits from outputs to inputs of registers are available (see bus) ELEN

13 Conditional transfer A conditional transfer occurs when a given condition is satisfied This is denoted by : if (K 1 = 1) then (R2 R1) K 1 : (R2 R1) K 1 is a control variable which acts on the load input of the register signal K 1 has to be synchronized to the clock ELEN

14 Arithmetic microoperations Example : RTL microoperation R0 R1 + R2 R0 R1 R0 R1 + 1 R0 R2 + R1 + 1 R0 R1 + 1 R0 R1 1 X K 1 : Description addition 1 s complement 2 s complement subtraction (2 s compl.) increment decrement R1 R1 + R2 XK 1 : R1 R1 + R2 + 1 in the transfer operation, R1 R1 + R2, + means arithmetic addition the variable K 1 enables the operation when K 1 = 1 the result is placed in R1 and replace the previous contents when K 1 = 0 no operation occurs, the contents of R1 is unchanged the variable X selects between addition and subtraction ELEN

15 Logical microoperations RTL microoperation R0 R1 R0 R1 R2 R0 R1 R2 R0 R1 R2 Description bitwise NOT bitwise OR (set bits) bitwise AND (clear bits) bitwise XOR (complement bits) Example : (K 1 + K 2 ) : R1 R1 R3 in the expression K 1 + K 2, + means logical OR in the transfer operation R1 R1 R3, means bitwise logical OR ELEN

16 Logical microoperations (continued) Let R1 = The OR microoperation can be used to set bits to 1 in the destination register when an appropriate mask is applied : for example, set 4 most significant bits to R1 (data) R2 (mask) R1 R1 R2 The AND microoperation is used to reset bits to 0 : R1 (data) R2 (mask) R1 R1 R2 the XOR microoperation can be used to complement bits : R1 (data) R2 (mask) R1 R1 R2 ELEN

17 Shift microoperations Registers can be shifted to the left or to the right, let R2 = left shift : R1 sl R2 R1 = a zero is entered at the least significant bit right shift : R1 sr R2 R1 = a zero is entered at the most significant bit sometimes, a separate flip-flop is used to provide the data shifted in or to memorize the data shifted out other shifts may be considered (rotate bits,...) ELEN

18 Microoperations on a single register Using control signals, several microoperations can be associated to a register. Examples : 1. general register with shift, parallel load and hold modes 2. K 1 : R0 R1, K 1K 2 : R0 R2 3. CX : A B, CY : A B These operations correspond to register transfers The source register or/and the microoperation has to be selected through a combinational circuit As already seen for example 1, the selection can be made using a multiplexer An alternative approach consists in designing the n-bit register with its combinational logic as the association of n identical register cells. A conventional approach is used for the design of the register cell If the same logic is used for each operation and/or source = dedicated logic If the combinational circuit can be shared by several sources or microoperations : shared logic The case of possible multiple destination registers will be considered later ELEN

19 Register transfers : selection through a multiplexer Consider example 2, where the source register has to be selected according to control variables K 1, K 2 A n-bit 2-to-1 multiplexer is used The selection input S is simply given by K 1 When : K1 = 1, the value in register R1 is transferred into register R0 K1 = 0 and K 2 = 1, the value in register R2 is transferred into register R0 in both cases, the Load input of the register is high and transfer is activated otherwise (K 1 = 0, K 2 = 0) : the Load input of the register is low the previous value in register R0 remains unchanged (hold mode) ELEN

20 Register transfers : Selection through a multiplexer The procedure can be generalized to n sources : outputs of dedicated logic blocks, registers or shared logic blocks the control signals are K 0,, K n 1 only one control signal is equal to one at any time the control signals are encoded to provide the selection inputs of the multiplexer ELEN

21 Register transfers design Specifications : one has to define for example 3 the destination register the data inputs to the register the control inputs and their useful combinations the set of register functions, i.e. the register transfers the hold mode : hold the current register state Design procedure : using a multiplexer using an individual cell design A B (CX, CY ), with combinations (0,0),(0,1),(1,0) CX : A B, (1,0) CY : A B, (0,1) (0,0) ELEN

22 Example 3, selection through a multiplexer The register transfers to be implemented are : CX : A B, CY : A B when CX = 0, CY = 0 : hold mode an encoder is not required, CX, CY are directly applied to the selecting inputs of the multiplexer ELEN

23 Example 3, selection through a multiplexer (continued) Consider the circuit cell for one bit of the register the decoder can be shared by all cells gate input cost : decoder : 8 non-shared logic : 2+8+9=19, for each bit for the whole circuit : n + 2 (shared logic, non-shared logic, one 2-OR gate) ELEN

24 Example 3, individual cell design Use the procedure defined in Chapter 5 for cell i State table Present state Next state A i (t) A i (t + 1) for CX CY B i (t) = flip-flop input equation : gate input cost : A i (t + 1) = CX B i + Āi(CY B i ) + A i CY + A i Bi = CX B i + Ā i (CY B i ) + A i (CY + B i ) = CX B i + Āi(CY.B i ) + A i CY.B i = CX B i + A i CY B i for one cell : 2 (CX.Bi ) + 2 (CY.B i ) + 8(XOR) + 2(OR) = 14 for the whole circuit = 14n! ELEN

25 Register transfers with multiple destination registers Digital systems have many registers Paths must be provided to transfer data from one register to the other A particular destination register has to be selected for each microoperation A possible solution is to use a multiplexer dedicated to each destination register Better solution : use a bus, i.e. a communication path shared by all register, and a single multiplexer to select the source Buses can be implemented using : multiplexers three state buffers ELEN

26 Dedicated MUX-Based transfers A very flexible transfer structure selection signals S i select the source register(s) control signals L i select the destination register(s) Possible transfers Select Load Register transfer S 2 S 1 S 0 L 2 L 1 L 0 R0 R R0 R1, R2 R R0 R1, R1 R ELEN

27 Multiplexer Bus The multiplexer selects the source register The control signals L i select the destination register(s) Possible transfers Select Load Register transfer S 1 S 0 L 2 L 1 L 0 R0 R R0 R1, R2 R R0 R1, R1 R0 impossible... A single bus driven by a multiplexer lowers the cost (less communication links, a single multiplexer) but limits the available transfers Simultaneous transfers with different sources in a single clock cycle are impossible ELEN

28 Buffer and Three-state buffer A buffer : simply copies the input variable : F = X is used to improve circuit voltage levels and increase the speed A three-state buffer presents a high-impedance output, giving three states : 0, 1 and High-Z the High-Z value behaves as an open circuit X is the data input and E is a control input Outputs of several 3-state buffers can be connected together provided that all outputs but one are in High-Z state ELEN

29 Selection circuit using 3-state logic Performing data selection with 3-state buffers 2 buffer outputs are connected together Data Selection Function : if S = 0, OL = IN0, else OL = IN1 Since EN0 = S and EN1 = S, one of the two buffer outputs is always High-Z ELEN

30 Three-state bus The multiplexer is replaced by 3-state buffers A three-state buffer is connected at the output of each flip-flop composing the register The enable signal EN is identical for all bits The inputs of the flip-flops are connected to the bus, most generally through a buffer (not represented in the figure) This provides a bi-directional bus The transfer capabilities are identical to those of the multiplexer-bus 3-state register with bidirectional lines 3-state bus ELEN

31 Serial transfers A system operates in serial mode if the information is transferred or manipulated (microoperation) one bit at a time The bits are shifted out of one register and into a second register This is done with shift registers, the serial output of the first register is connected to the serial input of the second register Example : the transfer of one binary word of 4 bits takes 4 clock cycles The operation is controlled by the clock-gated Shift variable ELEN

32 Serial microoperation example : 4bit-addition Two shift registers with parallel load capability are used for operands of the operation : A, B The two operands are loaded in parallel in the registers The operands are shifted at each clock cycle A full adder is used to compute the sum One additional flip-flop is used to store the carry Register A is also used to store the final result which is entered serially The final carry is stored in the flip-flop ELEN

33 Références Logic and Computer Design Fundamentals, 4/E, M. Morris Mano Charles Kime, Course material http ://writphotec.com/mano4/ Cours d électronique numérique, Aurélie Gensbittel, Bertrand Granado, Université Pierre et Marie Curie http ://bertrand.granado.free.fr/licence/ue201/ coursbeameranime.pdf Lecture notes, Course CSE370 - Introduction to Digital Design, Spring 2006, University of Washington, https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/ ELEN

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