Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Transcription

1 1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date: Friday, March 2, 2012 Time: 11:35 12:25 Student Name: McGill ID: Signature: INSTRUCTIONS: This is a CLOSED BOOK EXAM. FACULTY STANDARD CALCULATOR permitted ONLY. Read through ALL of the questions before beginning. Print your name legibly at the top of this page, fill in your student ID number and sign on the line below. Initial each page of the exam paper (nine pages in total) in case the sheets should get separated. The exam consists of Part 1 consisting of 10 multiple choice questions and Part 2 consisting of 4 problems. The multiple choice questions are equally weighted. You must encircle your answer. You can use the space provided to help yourself finding the answers. In Part 1, 2 marks for each correct answer, and 0.5 marks deducted for each wrong answer. Blank entries are not penalized. The 4 problems to be answered in the space provided on the examination sheet. You must encircle your final answer. The exam has a total of 30 marks.

2 2 Part 1 Multiple Choice (2 pts for correct answer) Question 1: What is the value represented by in a two s complement system? (Assume a 6 bit register) a) -11 b) 53 c) -53 d) 11 e) 21 Answer: a Question 2: What is the logical expression of the following circuit? a) b) c) d) e) Answer: a

3 3 Question 3: How many 2-input MUX, how many stages, and what is the total delay for a 32 bit multiplexer? (Do not count delay of inverters) a) 30 MUX, 5 stages, 15 units of gate delay b) 30 MUX, 4 stages, 10 units of gate delay c) 15 MUX, 4 stages, 10 units of gate delay d) 15 MUX, 5 stages, 30 units of gate delay e) 30 MUX, 5 stages, 10 units of gate delay Answer: e (30 was replaced by 31) Question 4: What is the base-8 representation of 4A7 12? a) 417 b) 703 c) 1607 d) 1277 e) 407 Answer: d Question 5: In the Flip Flop shown below, what is the next state of the output state variable if D(t) = 1? a) Undefined b) 0 c) Toggle d) 1 e) None of the above Answer: d Question 6: What is the minimum logic function of the following Karnaugh map?

4 4 (a) (b) (c) (d) (e) Answer: a Question 7: You are designing a modulo-8 counter using the following 7 segment display and a 3-to-8 decoder: Answer: e 7 Segment Display 3-to-8 Decoder A 3-to-8 decoder is used to assert each octal code (0 to 7). The inputs of the decoder represent the octal code in binary. Each segment of the display (a to g) combines 1 s (OR) or 0 s (NOR), depending on which are fewer in the truth table. What is the logic equation for segment b? (a) a = OR (5,6) (b) a = OR (1,2,5,6) (c) a = NOR(1,4) (d) a = XOR(2,3,5,6,7,8) (e) a = NOR (5,6)

5 5 Question 8: What is the main difference between The J-K master-slave flip-flop and the RISING edge-triggered flip-flop? a) Toggle mode is undefined for the J-K master-slave flip-flop but is defined for the edge triggered flip flop. b) The edge triggered flip flop is not susceptible to 1 s and 0 s catching whereas the J-K masterslave flip-flop is. c) RACE condition occurs in the J-K master-slave flip-flop but does not occur for the edge triggered flip flop. a) Preset and Clear allow the flip-flop to be forced into an initial state in the The J-K master-slave flip-flop but not in the edge triggered flip flop b) None of the above Answer: b Question 9: How is not a number represented using IEEE-754 format? a) Mantissa = 0, exponent = 0 b) Mantissa = non-zero, exponent = 0 c) Mantissa = 0, exponent = 255 d) Mantissa = 1, exponent = 0 e) Mantissa = non-zero, exponent = 255 Answer: e Question 10: In what mode is the Master-Slave SR latch at t = 87 units (red dash line)? a) Set Mode b) Reset Mode c) Toggle Mode d) Memory Mode

6 6 Answer: a Part 2 Problem 1 (5 pts): Encode the number x using the IEEE 754 format and express your result as a 8-digit hexadecimal number. Determine the mantissa to equivalent precision pts for not getting the right number of significant digits -2 pts for bad exponent -2 pts for bad mantissa Sign = 1 log( x 10 13) /log(2) = = x x x2 47 = x10 14 x ( x ) x = ( x x 2 47 ) / x x = ( x 2 47 ) / = x 2 47 = x 2 46 # of significant bits : 4/log (2) = > round up = 14 1 for the hidden bit normalization = 13 Mantissa:.2183 x 16 = x 16 = x 16 = x 16 = Exponent = = 173 Answer : D69BF200

7 7 Problem 2 (5 pts): Write out the algorithm for binary multiplication. Use the algorithm to perform the multiplication of and Assuming 5-bit registers, indicate whether overflow occurred. Soln: Set I = M; set P = 0. For j = 0, 1, 2,, n-1 do the following: 1. If digit j of N is 1 then set P = P + I Else if digit j of N is 0, do nothing; 2. Shift I left one place * * Overflow occurred. Things to remove points for: - shift left after each digit of N - do nothing if digit is 0 and add I if digit is 1 - the actual multiplication: 1 point - overflow detection: ½ a point Problem 3 (5 points) Derive the minimal Sum of Product and Product of Sum for the following function: F 1,4,5,6,9,12,13,14 A, B, C, D Show the corresponding NAND-NAND and NOR-NOR implementations and draw the circuit diagram using simple gates for the NAND and for NOR points for each map 1.25 points for each circuit

8 8 Problem 4 (5 points) Fill in the following state transition tables for the clocked S-R latch and the J-K Flip-flop. Indicate the mode for each input combination. What is the main difference between a clocked S-R latch and a J-K Flip-flop? 1 point for difference 2 points for each truth table J K Q Q Mode S R Q Q Mode Memory Memory Memory Memory Reset Reset Reset Reset Set Set Set Set toggle Not defined toggle Not defined Main difference: J=1 K=1 defined for JK flip flop. S=1, R=s not defined for SR latch