Digitally Assisted Analog Circuits. Boris Murmann Stanford University Department of Electrical Engineering

Transcription

1 Digitally Assisted Analog Circuits Boris Murmann Stanford University Department of Electrical Engineering

2 Motivation Outline Progress in digital circuits has outpaced performance growth in analog circuits by a large margin Digitally Assisted A/D Converters Using digital computing capabilities as a new driver to improve A/D converter energy efficiency Examples Experimental proof-of-concept result Next generation designs Conclusions Digitally Assisted Analog C ircuits B. Murmann 2

3 Modern Electronic Circuits Trend towards ubiquitous sensing, communication and computing "Ambient Intelligence" Signal processing predominantly done in digital domain Rapidly improving digital capabilities, fueled by "Moore's Law" Irreplaceable "bottleneck" - analog circuits Analog-Digital Converters (ADCs) Digital-Analog Converters (DACs) Filters and amplifiers (Anti-aliasing, RF power amplification, ) Focus of this talk: ADCs Digitally Assisted Analog C ircuits B. Murmann 3

4 Issue 1: Throughput Relative Performance µp MIPS (2x / 1.5 years) ADC* (2x / 4.7 years) 150x years * Performance measure: Bandwidth x Number of quantization levels Digitally Assisted Analog C ircuits B. Murmann 4

5 Issue 2: Power and Energy Example: Cell phone Battery has roughly 3Wh of Energy For a talk time of 12 hours, can draw no more than 250mW Only a fraction of that power available for ADC In an increasing number of applications, key issue is how much performance you can squeeze into a fraction of 0.1 1Watt What is the trend in ADC versus digital power/energy consumption? Digitally Assisted Analog C ircuits B. Murmann 5

6 ADC Energy versus Digital Energy Interesting metric to look at How many digital gates can you toggle for the energy needed in one A/D conversion? Example Standard digital gates (NAND2) in 0.13mm CMOS consume about 6nW/Gate/MHz Energy/Gate = 6fJ State-of-the-art 10-bit ADC consumes 1mW/MSample/sec Energy/Conversion = 1nJ Energy equivalent number of gates 1nJ/6fJ= 166,666 Digitally Assisted Analog C ircuits B. Murmann 6

7 Impact of Technology Scaling ADC Resolution: 6bits 8bits 10bits 12bits 14bits 16bits 500, , , , ,000 0 Energy Equivalent # of Gates Feature Size [ µ m] Digitally Assisted Analog C ircuits B. Murmann 7

8 Observations Energy equivalent number of gates per A/D conversion has gone through the roof Reason Digital circuits have scaled well with technology Analog doesn't benefit quite as much from smaller features Key idea Issues: Low supply voltage, low device gain, Build "digitally assisted analog circuits" Find a way to leverage digital processing capabilities to improve performance and lower power of analog circuits Digitally Assisted Analog C ircuits B. Murmann 8

9 Analog Circuit Challenges Speed Precision Matching and linearity constraints are not fundamental Noise Matching Linearity Power Dissipation Digitally Assisted Analog C ircuits B. Murmann 9

10 A New Generation of ADCs Conventional ADC Precisely linear mapping from input to output Relies on highly linear and well matched analog components V in Accurate ADC D accurate Digitally assisted ADC D sloppy D accurate A "sloppy" one-to-one mapper V in Low Complexity Sloppy ADC Digital Postprocessor Digital postprocessor estimates ADC errors and applies corrections Digitally Assisted Analog C ircuits B. Murmann 10

11 Examples Digitally assisted pipeline ADC Murmann & Boser, ISSCC 2003 Minimum complexity, ultra low energy pipeline ADC Under development in my research group ADC with embedded calibration for OFDM systems Under development in my research group Digitally Assisted Analog C ircuits B. Murmann 11

12 Pipeline ADC V in S/H STAGE 1 STAGE N-1 STAGE N R bits (e.g. R=1) V in A/D D/A - 2 R V res V D D=0 D=1 V in Bottleneck: Highly linear gain element Digitally Assisted Analog C ircuits B. Murmann 12

13 Open-Loop Gain Element Conventional Precision Amplifier Open-Loop Amplifier + Lower Noise + Increased Signal Range + Lower Power + Faster Nonlinear Use DSP to linearize! Digitally Assisted Analog C ircuits B. Murmann 13

14 Digital Nonlinearity Correction Analog Nonlinearity Digital Inverse Vin Dout Dout,corr Parameters Modulation System ID Use digital system identification techniques to determine optimum post distortion function Possible (and often necessary) to track correction parameters without interrupting normal ADC operation Digitally Assisted Analog C ircuits B. Murmann 14

15 Experimental Verification LOGIC REFERENCE AND BIAS PIPELINE BACKEND STAGE1 SHA CLK 12bit, 75MSamples/sec, 0.35µm, post-processor off chip Based on commercial part (Analog Devices AD9235) Digitally Assisted Analog C ircuits B. Murmann 15

16 Block Diagram ~8400 Gates (0.042mm 2 in 0.13µm) Proof of concept design Open-loop amplifier only in first, most critical stage Judicious analog/digital co-design Only two corretion parameters (linear and cubic amplifier error) Digitally Assisted Analog C ircuits B. Murmann 16

17 Linearity Improvement Post-Proc. OFF Post-Proc. ON Code Digitally Assisted Analog C ircuits B. Murmann 17

18 Amplifier Power Power [mw] % (33mW) 0 Commercial Part (Precision Amplifier) This Work (Simple Amplifier) Digitally Assisted Analog C ircuits B. Murmann 18

19 Digital Post-Processor 8400 Gates, 64 bytes RAM, 64kBit ROM Place & Route in 0.35µm technology Area=1.4mm 2 (18%) Power=10.5mW (3.6%) 40 Pipelined ADC (7.9 mm 2 ) Power [mw] Post-Processor 0 Amplifier Savings Post- Processor Digitally Assisted Analog C ircuits B. Murmann 19

20 Going Beyond a Proof of Concept Proof-of-concept design showed that the idea of digital assistance works, but power savings were not "revolutionary" As a more aggressive step, it is now interesting to explore the question: How many "analog" transistors do we really need? Digitally Assisted Analog C ircuits B. Murmann 20

21 Minimalistic Pipeline ADC Stage 2 V in 1 1 C DAC 2 V res C L (next stage) V REFN,P V DAC Use a single active device, operated like a charge pump to implement gain element Highly energy efficient, low noise, Gain is imprecise and nonlinear, but post-processor can take care of that Digitally Assisted Analog C ircuits B. Murmann 21

22 Simulated Energy/Conversion 1.E+06 1.E+05 Energy/Conversion [pj] 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 Minimalistic Pipeline ISSCC Expon. (ISSCC ) SN(D)R [db] 9-bit, "minimalistic" pipeline ADC prototype in 90nm technology Roughly 20,000 gates used for digital post-processing Only 7pJ per conversion, ~50x below state-of the art Digitally Assisted Analog C ircuits B. Murmann 22

23 Attributes (1) At 10MSamples/s (~video-rate), this ADC consumes only 70µW Can be powered from a 1cm 3 size battery for more than 1 year! A state-of the art ADC will drain the battery within a few days Digitally Assisted Analog C ircuits B. Murmann 23

24 Attributes (2) Analog Operations (2pJ) Digital Postprocessing (5pJ) 29% 71% Energy/conversion is dominated by digital postprocessing Great news! Energy efficiency will improve further when design is scaled to 65nm, 45nm, Digitally Assisted Analog C ircuits B. Murmann 24

25 The Calibration Problem The "sloppier" we make the analog portion of the ADC, the more parameters we need to estimate and track Can become quite complex or even impossible without disturbing normal ADC operation Idea: "System Embedded" postprocessing and calibration of ADC Leverage redundancy and knowledge of certain input signal properties to estimate ADC errors Re-use existing system resources for ADC calibration Example: ADC for OFDM receivers Digitally Assisted Analog C ircuits B. Murmann 25

26 Embedded ADC Calibration for OFDM pilot error f IFFT DAC Channel ADC DSP FFT pilot f Communications protocol uses "pilot tones" to measure and equalize RF channel nonidealities Why not use these pilots to "equalize" ADC? Errors in pilot signals can be used to estimate correction parameters for sloppy ADC Digitally Assisted Analog C ircuits B. Murmann 26

27 Typical Learning Curve ~100ms Digitally Assisted Analog C ircuits B. Murmann 27

28 Conclusions (1) Analog circuit improvements lag progress of digital functions Technology scaling only conditionally benefits analog circuit performance Digitally assisted analog circuits offload accuracy constraints to digital processor ADCs are obvious candidates for "digital assistance" The benefits of digital pre/postprocessing are also being investigated for several other analog circuit blocks Signal pre-distortion in RF power amplifiers Signal pre-distortion in DACs High-speed wireline interfaces Digitally Assisted Analog C ircuits B. Murmann 28

29 Key benefits Conclusions (2) Lower power and potentially higher speed Up to 100x reduction in ADC energy/conversion Digitally assisted ADCs will benefit from future technology scaling "Sloppy" circuits will be compatible with low voltage, low gain, ultimately scaled CMOS Key challenges Interdisciplinary nature of design problem Device modeling, circuit design Math, signal processing algorithms Inclusion of application layer Design complexity and turnaround time Digitally Assisted Analog C ircuits B. Murmann 29