VLSI Digital Signal Processing

Transcription

1 VLSI Digital Signal Processing EEC 28 Lecture Bevan M. Baas Tuesday, January 8, 29

2 Today Administrative items Syllabus and course overview My background Digital signal processing overview Read Programmable DSP Architectures, Part I by E. A. Lee 3

3 Course Communication Urgent announcements Web page Office hours After lecture Tuesday After lecture Thursday Tentatively Friday :3 2:3 4

4 Course Workload 4 unit graduate course This course requires significant effort and time Multi-disciplinary field coverage DSP algorithms Digital processor architectures Arithmetic Utilizes robust industry-standard CAD tools (but we will make use of only the core essential features) Verilog Synthesis tool Matlab EEC 28, 5

5 Course Readings No required textbook Over 8 slides posted as handouts on the course web page You should fully understand all material in these handouts A few required papers Several posted tutorials with example code You should fully understand these Several optional textbook references EEC 28, 6

6 Main Course Material The main body of material is presented in the lectures, readings, and handouts Generally speaking, the hwk/projets complement the main material They go into a much greater depth on specific topics They give design experience They give significant practical application of theory The Quizzes generally focus on the main body of material EEC 8B, 7

7 Breadth and Depth Breadth and Depth LECTURES HANDOUTS READINGS H W K P R O J P R O J EEC 8B, 8

8 Course Overview EEC 28 web page contents Reading materials and references Hwk/Project descriptions Handouts EEC 28, 9

9 Course Overview Canvas Grades posted here Let me know if you ever see a score different than you expect Upload electronic portions of hwk/projects here Syllabus Posted on course web page EEC 28,

10 Lectures Ask questions at any time Please hold conversations outside of class Please silence phones I will be out on travel Thursday, January 7 Guest lecture or possibly a special make-up lecture Integrated Solid-State Circuits Conference (ISSCC) February 8 2 Quiz and guest lecture on Tue, Feb 9; or possibly a special make-up lecture EEC 28,

11 Letter Grade Assignments I assign a letter grade only for the final course grade I look at the final exams and course record of the class and assign two key dividing points: the A/A+ and (probably B/B+) boundaries, and assign course grades from there using equallysized intervals No required numbers of any particular letter grades Absolute scores are not important; the boundaries shift according to the difficulty of the exams in any quarter Ignore any letter grades you might see on smartsite A/A+ Example with hypothetical data: B/B+ B B+ A A+ 2

12 Working With Others Collaboration Asking questions and explaining principles produces better work and dramatically increases learning Working with others Do homework and prelabs with classmates nearby Ask each other questions, help each other regarding principles, and approaches to solving only See Course Collaboration Policy on web page Dishonesty Copying produces similar work, stunts learning, is not fair to honest students, and is not allowed in this course Students engaged in dishonest work will be referred to Student Judicial Affairs I will try to keep in-class exams honest Steps will be taken to keep out of class work honest EEC 8B, 3

13 Penalties for Violating the Policy on Student Conduct and Discipline Penalties Minimum penalty: meetings with SJA officer, zero grade on work, record with SJA One to three quarter suspension from the university Permanent dismissal from all ten campuses of the University of California. Permanent notation on your transcript. The purpose of the penalties and me mentioning them is so that no one will get a penalty!!! Don t do anything that violates the Policy on Student Conduct! EEC 8B, 4

14 Penalties for Violating the Policy on Student Conduct and Discipline Typical scenario: Someone shares code/design with another They get caught The Copier feels terrible guilt for causing a friend to get a zero as well as getting their own work marked zero The Sharer deeply regrets sharing resulting in a zero when he/she should have had a full score EEC 8B, 5

15 Exam and Quiz Regrades Some number of exams and quizzes will be scanned before being returned Key take-away messages: Do not change anything on your work if you request a regrade One student did last quarter and got in big BIG trouble!!! EEC 8B, 6

16 Cheating Websites chegg, coursehero, etc. Key take-away messages: Do not post assignments Of course do not use any unpermitted outside material in work you submit Of course do not post solutions Two students did last quarter and got caught!!! EEC 8B, 7

17 Critical Challenges Facing Industry Energy Efficiency Performance Software development cost and time Hardware development cost and time Opportunity: Critical workloads sometimes/frequently have relatively simple tasks as critical kernels (e.g., machine learning, digital signal processing, multimedia, data record processing, pattern matching, etc.) Embedded (e.g., IoT) Mobile Datacenter 27

18 Number of Processors on a Single Die vs. Year Academic Industry Note: Each processor capable of independent program execution 3

19 Processor Eras Transistor Era: the Intel 44 was the first commercial single-chip microprocessor and it contained 23 hand-drawn transistors Single/Multi-Processor Era: focus on components of single processors and multi-processors, which generally scale well to only small numbers of processors -Processor Era: focus on making systems scalable and working with processors as building blocks. The 32 nm -processor KiloCore chip would contain approximately processors if its area were the same as a 32 nm Intel Core i7 processor, or, processors if its area were the same as an Nvidia GP 32

20 Future Fabrication Technologies Basic trends Number of available devices: continually increasing Energy dissipation per operation: decreasing too slowly VDD2 VDD3 VDD There are a lot of ways to place and connect a billion transistors The most efficient implementations (throughput, energy, area) will have: Processor sizes that capture computational kernels with few excess circuits Optimized clock frequencies and supply voltages matched to dynamic workloads 33

21 Optimal Computational Tile Size The most efficient implementations (energy, throughput, chip area) have: Processor sizes that capture computational kernels with few excess circuits ~ ~~ ~ ~~ Interprocessor interconnect Unused or low benefit-per-cost circuits Energy Effic. Clock rate Area Effic. Tile Size 34

22 Advancing CMOS Technologies Moore s Law (Observation) was made in 965 and notes that transistor density ~doubles every year (every.5 years now) "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 9,

23 Transistors (thousands) Number of Logical Cores Original data up to the year 2 collected and plotted by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. Batten New plot and data collected for 2-25 by K. Rupp New data added by 4

24 Digital Signal Processing Digital Discrete time Discrete valued Signal, 2, 3, dimensional Processing Analysis Synthesis Enhancement 4

25 DSP Workloads Often real-time Data producer and consumer can not be paused or held up Examples: antenna, controller, camera, video monitor, Very strict minimum performance levels Performance above that minimum is often of little value Data producer DSP system Data consumer 42

26 DSP Workloads Analysis. Ex: anti-lock brakes Data producer Maybe MSamples/sec DSP system Maybe Sample/sec Synthesis. Ex: music keyboard DSP system Data consumer 43

27 DSP Workloads Data stream can be considered infinite duration Length of data stream >> any buffering Ex: high-pass filter, automotive collision-detection radar distance measurement system DSP system 44

28 DSP Workloads Digital signal processing Typically very numerically intensive Lots of +, -, x DSP system 45

29 DSP Compared with Analog Processing Digital signal processing Compare with analog signal processing If possible in analog domain (at required precision), analog processing will likely require far fewer devices If possible in analog domain, either domain may produce the most energy-efficient solution Many algorithms are possible only with DSP (arbitrarily high precision, non-causal, ) DSP arithmetic is completely stable over process, temperature, and voltage variations Ex: = 5. will always be true as long as the circuit is functioning correctly 46

30 Digital signal processing DSP Compared with Analog Processing Compare with analog signal processing DSP energy-efficiencies are rapidly increasing Once a DSP processor has been designed in a portable format (gate netlist, HDL, software), very little effort is required to port (re-target) the design to a different processing technology. Analog circuits typically require a nearly-complete re-design. DSP capabilities are rapidly increasing Analog A/D speed x resolution product doubles every 5 years Digital processing performance doubles every 8-24 months (6x to x every 5 years) 47

31 Common DSP Applications Early applications Instrumentation Radar Communication Imaging Current applications Consumer audio, video Networking Telecommunications Machine learning Imaging Many many more 48

32 Consumer Products Trends Analog based Digital based Music records, tapes CDs, MP3s Video VHS, 8mm DVD, Blu-ray, H.264, H.265 Telephony analog mobile (G) digital (4G, LTE, ) Television NTSC/PAL digital (DVB, ATSC, ISDB, ) Many products use digital data and speak digital: computers, networks, digital appliances Impacts Processing Transmission Storage etc. EEC 28, 49

33 Consumer Products Trends Analog based vs. Digital based iphone apps??? EEC 28, 5

34 Future Applications Very limited power budgets Require significant digital signal processing 5

35 Key Design Metrics ) Performance a) Throughput (high); e.g., 25 MSamples/sec b) Latency (low); e.g., 2.7 µsec from first sample in -> first out c) Numerical precision 2) Chip area (cost); e.g., mm 2 die area, area of standard cell netlist 3) Energy dissipation per workload, e.g., Joules per JPEG image 4) Design complexity Design time = lower performance Software more important as systems become more complex 5) Suitability for future fabrication technologies Many transistors Faulty devices i) During manufacturing process ii) device wear out due to effects such as NBTI EEC 28, 52