REPEAT EXAMINATIONS 2002

Transcription

1 REPEAT EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An engine has 4 fail-safe sensors. The engine should keep running unless any of the following conditions arise: o If sensor 2 is activated. o If sensor 1 and sensor 3 are activated at the same time. o If sensor 2 and sensor 3 are activated at the same time. o If sensors 1, 3, 4 are activated at the same time. (a)derive the truth table for this system. A = Sensor1 B=Sensor2 C=Sensor3 D=Sensor4 sensor activated = 1 F=Engine Shutdown=1 A B C D F [4 marks for correct table] Page 1 of 1.

2 (a) Design, using Karnaugh Map techniques, a minimum AND-OR gate network for this system. Draw the resulting digital circuit diagram. Calculate Karnaugh Map: Resulting expression is : F = B + AC [4 marks for map] [4 marks for expression & diagram] (b) Design, a digital circuit that will implement the minimal AND-OR gate network found in (b) using both (i) NAND gates only and (ii) NOR gates only. Assume that each logic gate can have any number of inputs and that inverted inputs are available. Use DeMorgan s theorem to convert to NAND/NOR gates. The student must use the theorem and cannot simply substitute the gates as this does not result in the minimal solution. (i) NAND F = B + AC = B? AC? B. AC [3 marks] (ii) NOR Page 2 of 2.

3 F? B? AC F? B? AC F? B? ( A? C) F? F? B? ( A? C) [3 marks] (d) If the time delay experienced by a NAND gate is 10ns and the time delay experienced in a NOR gate is 8ns. Which implementation of (c) is faster? By how long? For the NAND gates the total delay is 2 x 10ns = 20ns For the NOR gates the total delay is 3 x 8ns = 24ns NAND gate implementation is faster by 4ns [3 marks] (e) Prove the rule of Boolean algebra: A? AB? A? B A? AB? A. A? AB? AA? AB? ( A? A)( A? B)? 1.( A? B)? A? B [4 marks] Page 3 of 3.

4 Question 2. (a) Explain the operation of an exclusive OR gate. Draw the symbol. Calculate the truth table for its operation.?? Describes events which are true if and only if one of the motivating events are true.?? Abbreviated XOR, EXOR Symbol is: Truth table: A B F [2 marks desc+symbol] [2 marks truth table] (b) Give 2 ways of expressing an exclusive OR gate using AND, OR and NOT gates. Draw the two expressions as circuits that are equivalent for implementing this operation using AND, OR and NOT gates.?? From the truth table in (a) we can say F=1 if A=1 or B=1 but not if A and B = 1?? (i)=> F? ( A? B)( AB)?? From this table we can also say (ii) F? AB? AB [4 marks each diagram (8 total)] Page 4 of 4.

5 (c) Explain the operation of NAND and NOR gates using figures and truth-tables. Why are these gates important in digital electronics? Explain and prove DeMorgan s Theorem.?? DeMorgan s Theorem means that any Boolean operation can be performed by a combination of AND and NOT operations, hence any digital circuit can be implemented using NAND or NOR gates only.?? A NAND operation is an AND operation followed by an inversion.?? Truth table for NAND A B F ?? A NOR operation is an OR operation followed by an inversion.?? Truth table for NOR A B F DeMorgan s Theorem can be proven from the truth table where [8 marks (4 each section)] AB? A? B and A? B? A. B A B AB A+B AB\ A\ B\ A\+B\ A+B\ A\B\ X X Y Y As X = X and Y=Y the two expressions are true [5 marks] Question 3. (a) Explain the operation of a half-adder. What are the logic equations? Draw the logic diagram for a half-adder.?? To add 2 least significant bits (the LSB) we do not need a carry input from a previous stage. Therefore we only need a half adder. A B S C Page 5 of 5.

6 Where S is the sum and C is the carry. The logic equations are: S? C? AB? AB? AB A? B The logic diagram can be drawn as: [ truth table + Desc. 5marks] [ logic +diagram 8marks] (b) Describe the operation of a full-adder. How is a full adder constructed from two half-adders? In what situation would a half-adder not be sufficient, meaning that a full-adder would be required??? For all other bits a half adder will not suffice as there may be a carry input from a previous stage.?? A full adder has 3 inputs A(k) B(k) C(k-1) and 2 outputs S(k) and C(k) A full adder may be constructed from two half adders using additional logic. One half adder adds A(k) to B(k) to give and intermediate sum S (k) and carry C (k). Another half adder then adds S (k) and C(k-1) to give the final sum S(k) and another intermediate carry C (k) [12 marks] Page 6 of 6.

7 Question 4. (a) Explain the operation of a right/left shift register. Draw the logic diagram to help explain its operation. [5 marks for diagram]?? Shift registers can be used to transfer data from right to left, shift left by connecting the output of a flip-flop back to the input of the flip-flop on its left.?? A shift from left to right, shift right, can be carried out during normal operation of the shift register?? A shift right and shift left register can be combined by suitable gating and control signals.?? In the operation above R / L? 0 => shift right?? In the operation above R / L? 1 => shift left?? Explain the operation of the logic gates simply an and gate with a value of 0 has an output of zero and an AND gate with one input of 1.A will have the output A. In effect the R/L line turns either the Right or Left AND gate on or off. The OR gate simply combines the output of the two AND gates to bring forward the correct output. [5 marks for description] [5 marks for diagram] (b) Develop a base 7 asynchronous binary counter. Page 7 of 7.

8 ?? Should count from 0 to 6 so 000 to 110?? 2 2 < 7 < 2 3 so we need 3 flip-flops, with max count 110?? When count goes to 111 the flip-flops must reset. Therefore a NAND gate is perfect for this.?? When Q(0), Q(1) and Q(2) go high R\ goes low and the counters are reset. [10 marks for diagram] [5 marks for text/derivation] Question 5. (a) Explain the operation of a JK flip-flop. How does it differ from an RS flip-flop? What are the limitations of a JK flip-flop??? A JK flip flop eliminates the undefined state (not allowed state) that occurred in the RS flipflop i.e. R=S=1.?? It is the most versatile and widely used flip-flop?? It differs from the RS flop-flop by using additional feedback. The truth table is: J K Q(n+1) 0 0 Q(n) Q(n)\?? It operates the same as the RS flip-flop except when J=K=1 where it now provides the additional functionality of a Toggle state. Page 8 of 8.

9 (b) How can a JK flip-flop be used as a 1-bit memory storage device? Use this configuration to build a 4-bit parallel data storage device. [6 marks for description] [6 marks for diagram] [3 marks for truth table]?? A JK flip flop can be used as a 1-bit memory (D flip-flop) by applying the bit to be stored (D) to J and its inverse (D\) to K. An n-bit binary word can be stored by n such flip-flops; called an n-bit register.?? It has parallel storage in that several bits on parallel lines stored simultaneously.?? Data bits D3 to D0 are stored on the receipt of a clock pulse [6 marks for figure] [4 marks for description] Page 9 of 9.