Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis

Transcription

1 October 11, 2005 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis Table of Contents Introduction...Page 1 List of Figures...Page 4 Device Summary Sheet...Page 7 Schematics... Tab 1 Symbol and Signal Name Conventions... Tab 2 Signal Cross-Reference List... Tab 3 Report Evaluation... Tab 4 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. Rev. F4.0

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3 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page 4 List of Figures Package Markings Package X-Ray Die Markings 0.1.4a FESEM Image Poly 0.1.4b FESEM Image (High Magnification) Poly Die Photograph Annotated Die Photograph Die Architecture Buffer 1 Definition Buffer 2 Definition Buffer 3 Definition Buffer 4 Definition Buffer 5 Definition DFF 1 Definition DFF 2 Definition DFF 3 Definition DFF 4 Definition DFF 5 Definition DFF 6 Definition DFF 7 Definition DFF 8 Definition DFF 9 Definition Latch1 Definition Latch2 Definition Multiplexer 1 Definition Multiplexer 2 Definition Multiplexer 3 Definition Multiplexer 4 Definition XOR Definition Rev /11/05 9:40 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR \Rev_3.0\Report\figlist.doc

4 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page Base Oscillator Clock Selection (Partial) MHz APLL Clock Input Control Circuit Phase Detector Charge Pump Low-pass Filter Voltage Control Oscillator Clock Divider with Output Signal Drivers Output Stage Bias Current Generator Clock Distribution Reset Management Circuitry (Partial) Input Buffer Partial MPU_RST Input Circuitry Partial Test Scan Chain Circuitry I Output Buffer Level Shifter Partial RST_OUT Circuitry Partial Test Circuitry Partial Test Scan Chain Circuitry II All-digital PLLs and Clock Management Modules Input Circuit Delay Loop Logic Delay Controller Delay String Registers Delay String Decoder IC Decoder Rev /11/05 9:40 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR \Rev_3.0\Report\figlist.doc

5 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page IC Registers Epsilon Controller Variable Delay Stage Delay Cell Delay Line Switch Variable Delay Line Commutator Preset Counter Phase Detector Main Clock Controller Clock Logic I Clock Logic II Clock Logic III Clock Logic IV Clock Logic V Clock Management Clock Processing I Clock Processing II Clock Processing III Clock Processing IV A.1.0 Symbol Conventions A.2.0 Symbol Definitions 1 A.2.1 Symbol Definitions 2 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation A.6.0 Resistor Size Notation Rev /11/05 10:52 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR \Report\figlist.doc

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