STMicroelectronics S550B1A CMOS Image Sensor Imager Process Report

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1 October 13, 2006 STMicroelectronics S550B1A CMOS Image Sensor Imager Process Report For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Imager Process Report Table of Contents 1 Overview 1.1 List of Figures and Tables 1.2 Introduction 1.3 Major Findings 2 Package and Die 2.1 Package and Die 2.2 Die Features 3 Process 3.1 Bond Pads 3.2 Passivation 3.3 Inter-metal Dielectrics (IMD) and Pre-metal Dielectric (PMD) 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Pixel Array Analysis 4.1 Plan View Analysis 4.2 Pixel Cross-Sectional Analysis (x-direction) 4.3 Pixel Cross-Sectional Analysis (y-direction) 5 Critical Dimensions Report Evaluation

3 Overview Overview 1.1 List of Figures and Tables 2 Package and Die Top and Bottom Views of the Camera Assembly 2.1.2a Top View Package X-Rays 2.1.2b Side View Package X-Rays Top Package Photograph Bottom Package Photograph Die with Color Filters and Lenses Die with Color Filters and Lenses Removed Die Markings Die Corner Die Corner and Bond Pad Minimum Pitch Bond Pads 3 Process General View of the STMicroelectronics S550B1A CMOS Imager Die Edge Seal Bond Pad Ball Bond Intermetallic Bond Pad Window Passivation IMD 1 and IMD IMD IMD Pre-metal Dielectric Metallization Vertical Dimensions Table Metallization Horizontal Dimensions Table Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Via and Contact Dimensions Minimum Pitch Via 2 s Minimum Pitch Via 1 s Minimum Pitch Contacts to Diffusion Contact to Polycide

4 Overview Stacked Vias and Contacts Stacked Via 1 s and Contacts Peripheral NMOS Transistor Minimum Pitch NMOS Transistors Peripheral PMOS Transistor Minimum Pitch Polycide Over Isolation LOCOS Isolation Minimum Width Isolation P-epi Layer and Substrate Periphery N-well SRP Plot SRP Plot for the P-epi Near the Pixel Array 4 Pixel Array Analysis Corner of Pixel Array Pixel Array at Metal Pixel Array at Metal Pixel Delayered to Polycide Higher Magnification View of the Pixel at Polycide Transistor and Photodiode Dimensions Table Pixel Schematic Annotated Plan-View Image of the Pixel at Polycide Column Output Stacked Vias Photodiode and Column Output Contacts Anti-Reflection Layers Over the Photodiode Gate Width of Transistor T Gate Length of Transistor T Transistors T2 and T Transistor T1 Gate Width Series of Photodiodes Higher Magnification View of a Photodiode 5 Critical Dimensions

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