LED BASED SNAKE GAME

Size: px
Start display at page:

Download "LED BASED SNAKE GAME"

Transcription

1 LED BASED SNAKE GAME Group 14 1 NAME ROLL NO MAJOR Muhammad Shoaib Hassan Electrical Engineering Syed Muhammad Ali Electrical Engineering Muhammad Ali Gulzar Computer Science Hassan Shabbir Electrical Engineering PROJECT INTRODUCTION AND OBJECTIVES Led based snake game is primarily a hardware implementation of the classic NOKIA snake game on the Led Matrix. The execution and implementation of the game employs diverse skills learned at the class from the very first day and covers a wide spectrum of topics. The project appreciates the way in which different topics and techniques learnt in this course are put to practice, simultaneously, to perform a specific task. This project capitalizes on the fundamental concepts of combinational logic and incorporates other pertinent techniques such as, data storage, counter and clock. By the end of this project, we had successfully implemented the entire game along with pattern generation, food generation and scoring system. PROJECT HIERARCHY SNAKE GAME Snake's Movement Snake's Body Snake's Speed Regeneration LED Patterns Food Generation User Interface Fixed Initital Length Variable Speed Re-Entry From the Opposite Side At the Start of the Game Movement of food at the walls of the LED Scoring System Turn Left/Right Smooth Increment At the End of the game Score Automatically restarts at 30 pts Turn Up/Down Legal Moves Smooth Turning

2 Group 14 2 PROJECT SPECIFICATIONS 74LS08 74LS37 74LS HCT LS LED Matrix Resistors Switches Voltage Source Capacitor Tri State Buffer Decoders AND Gates NAND Gates NOR Gates /Oscillator 8-Bit Edge D-Flip Flops Inverter Bit Magnitude Comparartor 1 to 8 Data Selectors/Multiplexers Common anode Food Controls +5V DC Supply Variable speed Octal Bus Transceivers 3-to-8 line decoder, and 2-to-4 line decoder Bi-Directional Shift Register EPROM 4-Bit Binary Counter BCD to Seven Segment Equipment Name IC Number No. Used LED Matrix 8x8 Bi-Colour 6 7-Segment Display Common Anode 2 EPROM's Quad Mux's to 8 Multiplexer Octal Bus Transceivers Bi-Direction Shift register Bit Comparators Binary Counter BCD to Seven Segment /Oscillators Bit Edge D-Flip Flops Line Decoder Line Decoder 74HC139 1 AND NOT XOR Resistors 100/220/7000 Ω 40 Capacitors 10/5/20 µf 5

3 PROJECT DELIVERABLES (WHICH WERE ACCOMPLISHED) Group 14 3 By the end of this project, we had successfully implemented these features: 1. Movement of the snake on the LED Matrix. 2. Increment in its position with the help of a user control system only in the legal directions. 3. Variable speed of the movement of the snake as a functional feature. 4. Keeping track of the snake and regeneration of the snake once it leaves from the one side of matrix. 5. Led pattern generation at the start and end of game as an additional feature using multiplexing with the help of which the SNAKE letters were generated. MODULE COMPOSITION SNAKE GAME User Interface Snake's Length Snake's Speed Regeneration LED Pattren Food Snake Turning Smooth Turning Fixed Length Smooth Increment Variable Speed Counter LED Matrix At walls SR Latches Tristate Buffer n to 1 Mux D Flip Flops n to 1 Mux D Flip Flops Capacitor D Flip Flop n to 1 Mux Tri State bufer D- Latches ROM Counters 7-Seg Display WEEKLY BREAKDOWN WEEK 1: During the first week, we exercised our knowledge to go about this problem on the proteus software. We tackled the problems faced during the simulation process and tried to find their solution. Moreover, we learnt how to use a led matrix because it was a fundamental component of our project. WEEK 2: After having a fair idea about the proceedings, we had a go at the hardware implementation of our simulated circuit. Our main focus was to have a firm control over the functioning of counters, clocks, latches and flip flops. We strived to use these components with the led matrix such that we could build foundation for the later events. WEEK 3: Having our structure ready in the previous week, we went a step ahead in this week by implementing the incremental motion of the snake. Once this function was implemented, we finalized the length of the snake and will work on its movements on the led matrix. The functionality of the variable speed with which a snake moves on a led matrix also got implemented by the end of this week.

4 Group 14 4 WEEK 4: During this week, the additional features such as led pattern generation at the start and the end of the game were considered. We figured out a way to crack it through multiplexing and by using the effective ROM writing technique learnt in the lab, we accomplished this task. WEEK 5: Utilizing this time we winded up the project by giving it finishing touch. But we went a step ahead in the final week to implement, if time permits suggestion which we proposed according to which the snake eats the food and there is a proper scoring system to recognize this action. We successfully implemented and demonstrated all the deliverables along with bonus part on the day of demonstration. Week 1 Proteous Simlutaion Debugging Undetrstanding of LED Matrix Week 2 Hardware Implementaion Use of Flips Flops, Counters, Clocks and Latches Synicrnoization between LED Matrix and other componants. Week 3 Implementation of incremental motions of snake Length of the snake Variable speed Week 4 Additional feature like LED Pattrens at the start and end using multiplexing. Smooth movement by avoiding abrupt turns Week 5 Food generation. Scoring system of the food. Neatness of the project. TECHNICAL ISSUES FACED Firstly, the most disturbing issue faced by our group was that we had extensively large circuit and it was breathtaking to debug it if the desired result was not obtained during the testing phase. We cracked this problem with the help of colour coding and using labelled wires. Most importantly, we had a working Proteus simulation in front of us, so wherever lost, we grasped help from that. Secondly, the design of the controller was not an easy task. The design was intriguing since there were five controlling variables and we had to cut that down to two variables. Along with that we had to take care of the legality of the moves from the user side. This task employed some critical thinking and in the end our group was able to overcome the problem by using a 2-to-4 line decoder, couple of OR gates and couple of SR latches. Thirdly, when we tried to implement the time permits module, we were not sure how to add food generation logic in the circuit and the execution of this step was pertinent problem because our circuit had little space for anything else. We dominated this issue by using a separate logic to implement this task, i.e. rotation with the help of Shift registers through which were successfully able to generate food. Finally, we added a counter and testing unit to detect the food eating condition of the snake to accomplish the implementation of our scoring problem. Fourthly, we had to incorporate multiplexing in our project to generate the LED patterns. We learnt the ROM writing and using technique taught in the lab with a little help from the supervisor, we were able to overcome this hurdle.

5 Group 14 5 PROTEUS SCREENSHOTS Figure 1: Schematic for snake game circuit Figure 2: Schematic for multiplexing circuit

6 Group 14 6 TRUTH TABLES FOR CONTROLLER S OPERATIONS Controller using 2-to-4 line decoder Input Output Lines Lines I 2 I 1 Switch A Switch B Vertically Upwards Move to the left (horizontally) Move to the right (horizontally) Vertically Downwards SR latch for column operations Input Output Lines Lines I 2 I 1 R S SR latch for row operations Input Output Lines Lines I 2 I 1 R S

EE Chip list. Page 1

EE Chip list. Page 1 Chip # Description 7400 Quadruple 2-Input Positive NANDS 7401 Quadruple 2-Input Positive NAND with Open-Collector Outputs 7402 Quadruple 2-input Positive NOR 7403 Quadruple 2-Intput Positive NAND with

More information

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.

More information

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:

More information

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL 1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click

More information

Final Project [Tic-Tac-Toe]

Final Project [Tic-Tac-Toe] Final Project [Tic-Tac-Toe] (In 2 dimension) ECE 249 Session: 3-6pm TA: Jill Cannon Joseph S Kim Ghazy Mahub Introduction As a final project for ECE 249, we will develop a multi-player tic-tac-toe game

More information

SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series. Supply Current/typmA Delay/typns Quad 2-Input NAND Gate 54LS00/C,D

SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series. Supply Current/typmA Delay/typns Quad 2-Input NAND Gate 54LS00/C,D SIGNETICS INTEGRATED CIRCUITS Low Power Schottky TTL 54LS00-74LS00 Series Rating Value Unit Voltage - V CC +7.0 V Input Voltage Range - V I -0.5 to +7.0 V Output Voltage - V out +5.5 V Operating Temperature

More information

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate List of the CMOS 4000 series 4000 - Dual tri-input NOR Gate and Inverter 4001 - Quad 2-input NOR gate 4002 - Dual 4-input NOR gate 4006-18 stage Shift register 4007 - Dual Complementary Pair Plus Inverter

More information

Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)

Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit) Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics

More information

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No. 6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Project Resources Project resources are allocated on a per

More information

Chapter 9 MSI Logic Circuits

Chapter 9 MSI Logic Circuits Chapter 9 MSI Logic Circuits Chapter 9 Objectives Selected areas covered in this chapter: Analyzing/using decoders & encoders in circuits. Advantages and disadvantages of LEDs and LCDs. Observation/analysis

More information

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division Objectives In this lab, you will see two types of sequential circuits: latches and flip-flops. Latches and flip-flops can be used

More information

Assignment 2b. ASSIGNMENT 2b. due at the start of class, Wednesday Sept 25.

Assignment 2b. ASSIGNMENT 2b. due at the start of class, Wednesday Sept 25. ASSIGNMENT 2b due at the start of class, Wednesday Sept 25. For each section of the assignment, the work that you are supposed to turn in is indicated in italics at the end of each problem or sub-problem.

More information

North Shore Community College

North Shore Community College North Shore Community College Course Number: IEL217 Section: MAL Course Name: Digital Electronics 1 Semester: Credit: 4 Hours: Three hours of Lecture, Two hours Laboratory per week Thursdays 8:00am (See

More information

Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010

Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010 Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010 Andrew C. and Julia A. DLD Final Project Spring 2010 Abstract For our final project, we created a game on a grid of 72 LED s (9 rows

More information

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH CPE 200L LABORATORY 3: SEUENTIAL LOGIC CIRCUITS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Learn to use Function Generator and Oscilloscope on the breadboard.

More information

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division Objectives In this lab, we will see the sequential circuits latches and flip-flops. Latches and flip-flops can be used to build

More information

MODULE 3. Combinational & Sequential logic

MODULE 3. Combinational & Sequential logic MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational

More information

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Course Title: Digital Logic Full Marks: 60 + 0 + 0 Course No.: CSC Pass Marks:

More information

LAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display

LAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display LAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display LAB OBJECTIVES 1. Design a more complex state machine 2. Design a larger combination logic solution on a PLD 3. Integrate two designs

More information

Laboratory 8. Digital Circuits - Counter and LED Display

Laboratory 8. Digital Circuits - Counter and LED Display Laboratory 8 Digital Circuits - Counter and Display Required Components: 2 1k resistors 1 10M resistor 3 0.1 F capacitor 1 555 timer 1 7490 decade counter 1 7447 BCD to decoder 1 MAN 6910 or LTD-482EC

More information

Combinational Logic Design

Combinational Logic Design Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where

More information

Step 1 - shaft decoder to generate clockwise/anticlockwise signals

Step 1 - shaft decoder to generate clockwise/anticlockwise signals Workshop Two Shaft Position Encoder Introduction Some industrial automation applications require control systems which know the rotational position of a shaft. Similar devices are also used for digital

More information

55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009.

55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009. 55:131 Introduction to VLSI Design Project #1 -- Fall 2009 Counter built from NAND gates, timing Due Date: Friday October 9, 2009 Introduction In this project we will create a transistor-level model of

More information

FUNCTIONS OF COMBINATIONAL LOGIC

FUNCTIONS OF COMBINATIONAL LOGIC FUNCTIONS OF COMBINATIONAL LOGIC Agenda Adders Comparators Decoders Encoders Multiplexers Demultiplexers Adders Basic Adders Adders are important in computers other types of digital systems in which numerical

More information

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Nate Pihlstrom, npihlstr@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement

More information

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

More information

Chapter 2. Digital Circuits

Chapter 2. Digital Circuits Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217

More information

Part IA Computer Science Tripos. Hardware Practical Classes

Part IA Computer Science Tripos. Hardware Practical Classes Part IA Computer Science Tripos Hardware Practical Classes Year: 2014 2015 Dr. I. J. Wassell, Mr. N. Batterham. 1 2 Digital Hardware Labs - Introduction Many materials are available on which to build prototype

More information

Lab #12: 4-Bit Arithmetic Logic Unit (ALU)

Lab #12: 4-Bit Arithmetic Logic Unit (ALU) Lab #12: 4-Bit Arithmetic Logic Unit (ALU) ECE/COE 0501 Date of Experiment: 4/3/2017 Report Written: 4/5/2017 Submission Date: 4/10/2017 Nicholas Haver nicholas.haver@pitt.edu 1 H a v e r PURPOSE The purpose

More information

Design of a Binary Number Lock (using schematic entry method) 1. Synopsis: 2. Description of the Circuit:

Design of a Binary Number Lock (using schematic entry method) 1. Synopsis: 2. Description of the Circuit: Design of a Binary Number Lock (using schematic entry method) 1. Synopsis: This lab gives you more exercise in schematic entry, state machine design using the one-hot state method, further understanding

More information

Spring 2011 Microprocessors B Course Project (30% of your course Grade)

Spring 2011 Microprocessors B Course Project (30% of your course Grade) Course Project guidelines Spring 2011 Microprocessors B 17.384 Course Project (30% of your course Grade) Overall Guidelines Design a fairly complex system that contains at least one microcontroller (the

More information

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade

More information

16 Stage Bi-Directional LED Sequencer

16 Stage Bi-Directional LED Sequencer 16 Stage Bi-Directional LED Sequencer The bi-directional sequencer uses a 4 bit binary up/down counter (CD4516) and two "1 of 8 line decoders" (74HC138 or 74HCT138) to generate the popular "Night Rider"

More information

Review : 2 Release Date : 2019 Last Amendment : 2013 Course Code : SKEE 2742 Procedure Number : PK-UTM-FKE-(0)-10

Review : 2 Release Date : 2019 Last Amendment : 2013 Course Code : SKEE 2742 Procedure Number : PK-UTM-FKE-(0)-10 School Course Name : : ELECTRICAL ENGINEERING 2 ND YEAR ELECTRONIC DESIGN LAB Review : 2 Release Date : 2019 Last Amendment : 2013 Course Code : SKEE 2742 Procedure Number : PK-UTM-FKE-(0)-10 School of

More information

University of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual

University of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual University of Victoria Department of Electrical and Computer Engineering CENG 290 Digital Design I Lab Manual INDEX Introduction to the labs Lab1: Digital Instrumentation Lab2: Basic Digital Components

More information

Rensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory

Rensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory RPI Rensselaer Polytechnic Institute Computer Hardware Design ECSE 4770 Report Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory Name: Walter Dearing Group: Brad Stephenson David Bang

More information

Copyright 2011 by Enoch Hwang, Ph.D. and Global Specialties. All rights reserved. Printed in Taiwan.

Copyright 2011 by Enoch Hwang, Ph.D. and Global Specialties. All rights reserved. Printed in Taiwan. Copyright 2011 by Enoch Hwang, Ph.D. and Global Specialties All rights reserved. Printed in Taiwan. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form

More information

Integrated Circuits 7

Integrated Circuits 7 7 IC Test Clip Series For temporary connections to DIP package components Heavy-duty spring loaded hinge provides positive contact 20 AWG insulated gold contacts Color: white 22103 Part No. Product No.

More information

Laboratory 11. Required Components: Objectives. Introduction. Digital Displays and Logic (modified from lab text by Alciatore)

Laboratory 11. Required Components: Objectives. Introduction. Digital Displays and Logic (modified from lab text by Alciatore) Laboratory 11 Digital Displays and Logic (modified from lab text by Alciatore) Required Components: 2x lk resistors 1x 10M resistor 3x 0.1 F capacitor 1x 555 timer 1x 7490 decade counter 1x 7447 BCD to

More information

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state

More information

University of Illinois at Urbana-Champaign

University of Illinois at Urbana-Champaign University of Illinois at Urbana-Champaign Digital Electronics Laboratory Physics Department Physics 40 Laboratory Experiment 3: CMOS Digital Logic. Introduction The purpose of this lab is to continue

More information

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic COURSE TITLE : DIGITAL INSTRUMENTS PRINCIPLE COURSE CODE : 3075 COURSE CATEGORY : B PERIODS/WEEK : 4 PERIODS/SEMESTER : 72 CREDITS : 4 TIME SCHEDULE MODULE TOPICS PERIODS 1 Number system & Boolean algebra

More information

Analogue Versus Digital [5 M]

Analogue Versus Digital [5 M] Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,

More information

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

Computer Systems Architecture

Computer Systems Architecture Computer Systems Architecture Fundamentals Of Digital Logic 1 Our Goal Understand Fundamentals and basics Concepts How computers work at the lowest level Avoid whenever possible Complexity Implementation

More information

DIGITAL FUNDAMENTALS

DIGITAL FUNDAMENTALS DIGITAL FUNDAMENTALS A SYSTEMS APPROACH THOMAS L. FLOYD PEARSON Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal

More information

IS1500 (not part of IS1200) Logic Design Lab (LD-Lab)

IS1500 (not part of IS1200) Logic Design Lab (LD-Lab) Introduction IS1500 (not part of IS1200) Logic Design Lab (LD-Lab) 2017-10-26 The purpose of this lab is to give a hands-on experience of using gates and digital building blocks. These build blocks are

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in

More information

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE NORTHWESTERN UNIVERSITY TECHNOLOGICL INSTITUTE ECE 270 Experiment #8 DIGITL CIRCUITS Prelab 1. Draw the truth table for the S-R Flip-Flop as shown in the textbook. Draw the truth table for Figure 7. 2.

More information

EECS 270 Final Exam Spring 2012

EECS 270 Final Exam Spring 2012 EECS 270 Final Exam Spring 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /20 3 /12 4 /10 5 /15

More information

Part IA Computer Science Tripos. Hardware Practical Classes

Part IA Computer Science Tripos. Hardware Practical Classes Part IA Computer Science Tripos Hardware Practical Classes Year: 2013 2014 Dr. I. J. Wassell, Mr. N. Batterham. 1 2 Digital Hardware Labs - Introduction Many materials are available on which to build prototype

More information

Physics 323. Experiment # 10 - Digital Circuits

Physics 323. Experiment # 10 - Digital Circuits Physics 323 Experiment # 10 - Digital Circuits Purpose This is a brief introduction to digital (logic) circuits using both combinational and sequential logic. The basic building blocks will be the Transistor

More information

Digital Logic. ECE 206, Fall 2001: Lab 1. Learning Objectives. The Logic Simulator

Digital Logic. ECE 206, Fall 2001: Lab 1. Learning Objectives. The Logic Simulator Learning Objectives ECE 206, : Lab 1 Digital Logic This lab will give you practice in building and analyzing digital logic circuits. You will use a logic simulator to implement circuits and see how they

More information

Electromania Problem statement discussion

Electromania Problem statement discussion Electromania Problem statement discussion A Competition Basic Circuiting What is Electromania? Debuggin g Innovation Let s recall the previous lecture..!! Electronics Digital Analog Analog Digital Digital

More information

VU Mobile Powered by S NO Group

VU Mobile Powered by S NO Group Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.

More information

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS One common requirement in digital circuits is counting, both forward and backward. Digital clocks and

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

1. Synopsis: 2. Description of the Circuit:

1. Synopsis: 2. Description of the Circuit: Design of a Binary Number Lock (using schematic entry method) 1. Synopsis: This lab gives you more exercise in schematic entry, state machine design using the one-hot state method, further understanding

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203

More information

Combinational vs Sequential

Combinational vs Sequential Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs

More information

Microprocessor Design

Microprocessor Design Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview

More information

Engineering College. Electrical Engineering Department. Digital Electronics Lab

Engineering College. Electrical Engineering Department. Digital Electronics Lab Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/2010-1 - CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates

More information

ELEN Electronique numérique

ELEN Electronique numérique ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 6 Registers and Counters ELEN0040 6-277 Design of a modulo-8 binary counter using JK Flip-flops 3 bits are required

More information

Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

More information

LED Array Tutorial. This guide explains how to set up and operate the LED arrays that can be used for your. Internal Structure of LED Array

LED Array Tutorial. This guide explains how to set up and operate the LED arrays that can be used for your. Internal Structure of LED Array LED Array Tutorial This guide explains how to set up and operate the LED arrays that can be used for your final EE 271 project. This tutorial is directed towards the FYM12882AEG 8x8 LED array, but these

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error

More information

Experiment # 4 Counters and Logic Analyzer

Experiment # 4 Counters and Logic Analyzer EE20L - Introduction to Digital Circuits Experiment # 4. Synopsis: Experiment # 4 Counters and Logic Analyzer In this lab we will build an up-counter and a down-counter using 74LS76A - Flip Flops. The

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters

More information

Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis

Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis October 11, 2005 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis Table of Contents Introduction...Page 1 List of Figures...Page 4 Device Summary Sheet...Page 7 Schematics...

More information

[2 credit course- 3 hours per week]

[2 credit course- 3 hours per week] Syllabus of Applied Electronics for F Y B Sc Semester- 1 (With effect from June 2012) PAPER I: Components and Devices [2 credit course- 3 hours per week] Unit- I : CIRCUIT THEORY [10 Hrs] Introduction;

More information

ENGG2410: Digital Design Lab 5: Modular Designs and Hierarchy Using VHDL

ENGG2410: Digital Design Lab 5: Modular Designs and Hierarchy Using VHDL ENGG2410: Digital Design Lab 5: Modular Designs and Hierarchy Using VHDL School of Engineering, University of Guelph Fall 2017 1 Objectives: Start Date: Week #7 2017 Report Due Date: Week #8 2017, in the

More information

Serial In/Serial Left/Serial Out Operation

Serial In/Serial Left/Serial Out Operation Shift Registers The need to storage binary data was discussed earlier. In digital circuits multi-bit data has to be stored temporarily until it is processed. A flip-flop is able to store a single binary

More information

Integration of Virtual Instrumentation into a Compressed Electricity and Electronic Curriculum

Integration of Virtual Instrumentation into a Compressed Electricity and Electronic Curriculum Integration of Virtual Instrumentation into a Compressed Electricity and Electronic Curriculum Arif Sirinterlikci Ohio Northern University Background Ohio Northern University Technological Studies Department

More information

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering BCN1043 By Dr. Mritha Ramalingam Faculty of Computer Systems & Software Engineering mritha@ump.edu.my http://ocw.ump.edu.my/ authors Dr. Mohd Nizam Mohmad Kahar (mnizam@ump.edu.my) Jamaludin Sallim (jamal@ump.edu.my)

More information

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function

More information

Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM

Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM

More information

0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format

0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format Applications of Shift Registers The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. The two applications of the

More information

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit.

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit. 6.1 Objectives To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit. 6.2 Sequential Logic So far we have implemented digital circuits whose outputs depend only on its

More information

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true. EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting

More information

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course Session Number 1532 Adding Analog and Mixed Signal Concerns to a Digital VLSI Course John A. Nestor and David A. Rich Department of Electrical and Computer Engineering Lafayette College Abstract This paper

More information

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20 Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.

More information

MUX AND FLIPFLOPS/LATCHES

MUX AND FLIPFLOPS/LATCHES MUX AN FLIPFLOPS/LATCHES BY: SURESH BALPANE Multiplexers 2:1 multiplexer chooses between two inputs S 1 0 Y 0 X 0 0 0 0 0 X 1 1 1 0 X 0 1 1 X 1 1 1 S Y @BALPANECircuits and Slide 2 Gate-Level Mux esign

More information

University of Pennsylvania Department of Electrical and Systems Engineering. Digital Design Laboratory. Lab8 Calculator

University of Pennsylvania Department of Electrical and Systems Engineering. Digital Design Laboratory. Lab8 Calculator University of Pennsylvania Department of Electrical and Systems Engineering Digital Design Laboratory Purpose Lab Calculator The purpose of this lab is: 1. To get familiar with the use of shift registers

More information

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab VeriLab An introductory lab for using Verilog in digital design (first draft) VeriLab An introductory lab for using Verilog in digital design Verilog is a hardware description language useful for designing

More information

Digital Circuits I and II Nov. 17, 1999

Digital Circuits I and II Nov. 17, 1999 Physics 623 Digital Circuits I and II Nov. 17, 1999 Digital Circuits I 1 Purpose To introduce the basic principles of digital circuitry. To understand the small signal response of various gates and circuits

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009

12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the

More information

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date: Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science SOLUTIONS

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science SOLUTIONS University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 5 Fall 25 R. H. Katz SOLUTIONS Problem Set #3: Combinational and Sequential Logic

More information

FPGA Design. Part I - Hardware Components. Thomas Lenzi

FPGA Design. Part I - Hardware Components. Thomas Lenzi FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise

More information

EECS 270 Midterm 2 Exam Closed book portion Fall 2014

EECS 270 Midterm 2 Exam Closed book portion Fall 2014 EECS 270 Midterm 2 Exam Closed book portion Fall 2014 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points

More information

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

AIM: To study and verify the truth table of logic gates

AIM: To study and verify the truth table of logic gates EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main

More information

A Combined Combinational-Sequential System

A Combined Combinational-Sequential System A Combined Combinational-Sequential System Object To construct a serial transmission circuit with a comparator to check the output. Parts () 7485 4-bit magnitude comparators (1) 74177 4-bit binary counter

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) Subject Code: 17320 Model Answer Page 1 of 32 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the Model answer scheme. 2) The model

More information

DIGITAL ELECTRONICS MCQs

DIGITAL ELECTRONICS MCQs DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8

More information