B3ZS Encoder/Decoder Reference Design APPLICATION NOTE OCTOBER 2001 APPLICABLE TDK DEVICES 78P P7200L 78P7202L 78P7203L 78P7204L

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Jeremy Reed
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1 B3ZS Encoder/Decoder Reference Design APPLICATION E INTRODUCTION In DS3 applications, Binary Three Zero Suppression (BZ3S) coding is required when transmitting a sequence of three zeros or more. Often times, this encoding/decoding is implemented in the digital framer or mapper. TDK Semiconductor also offers LIUs or transceivers with integrated BZ3S encoders/decoders in the 78P224x series and 78P234x series. As such, this application note only applies to applications which do not already have a BZ3S encoder/decoder in the system. APPLICABLE TDK DEVICES 78P P7200L 78P7202L 78P7203L 78P7204L OCTOBER 200 DESCRIPTION The DS3 specification calls for B3ZS (Binary Three Zero Suppression) coding in addition to AMI (Alternative Mark Inversion) coding for transmission over the line. AMI is a balanced code that will encode consecutive ones into either a positive or negative pulse in an alternating pattern; zeros will generate no pulses. For the receiver s phase lock loop to maintain lock with the input data from the line a minimum number of pulses are required. The B3ZS encoding insures that no more than two consecutive zeros will be transmitted on the line while the AMI encoding provides a change of polarity for every one transmitted. The implementation of BPV (Bipolar Polarity Violation) inserts a one, at the position of any third zero, of the same polarity as the preceding one thus causing a BPV. This allows the receiver to recognize the BPV and delete the inserted ones from the received data stream. An additional function of B3ZS encoding is to eliminate DC offset on the transmission line, indeed BPV s of the same polarity will create a DC offset. Therefore every BPV needs to be of the opposite polarity from the previous BPV. To realize this, an additional one needs to be inserted if the previous BPV polarity is the same as the BPV polarity to be inserted. This additional one is inserted at the position of the first zero in the three zero sequence. B3ZS ENCODING. Two cases must be considered when three zeros are detected (see Table ): In the first case, assume the previous BPV is of the opposite polarity from the BPV to be sent. Then the first and second zero bit positions will be zero and the third zero bit position will have an inserted one of the same polarity as the preceding one. In the second case, assume the previous BPV is of the same polarity as the BPV to be sent. Then the first zero bit position will be a normal AMI coded one followed by a zero and finally a BPV. To represent graphically the two cases a positive one is called P a negative one is called N and a positive BPV will be called PB, a negative BPV will be called NB. First case Second case Binary data Ternary code P 0 0 PB N 0 NB P Table : B3ZS code rules representation B3ZS DECODING For the receiver it is easy to decode the B3ZS encoding. When a BPV is detected and it is preceded by a zero, then the BPV and the two preceding bits will be set to zero. B3ZS ENCODER IMPLEMENTATION Figure shows an implementation of a B3ZS encoder. The NRZ (Non Return to Zero) data is presented at the input and shifted into S, S2 and S3. The four input NOR gate can detect the presence of three zeros and that a BPV sequence is not currently in progress. If these conditions are met, depending on the polarity of the last BPV, BPVPOL and the current state of the line polarity flip flop (POLP), one of two sequence will be initiated: ) If they are in the same state, then the one insertion logic will be enabled and the next bit transmitted to the line will be a one. 2) Otherwise the next bit transmitted will be a zero. - -

2 BZ3S Encoder/Decoder Reference Design At the time of three zero detection, the shift registers BPVM and BPVM2 are started. The two input OR gate prevents the BPV sequence from starting again before the next two clock pulses. This is done in case there are more than three zeros in the input stream. When BPVM2 is set, then the BPV will be sent through the logic BPV. The two flip flops at the TPOS and TNEG outputs are not needed if the logic behind them is clocked. B3ZS DECODER IMPLEMENTATION Figure 2 shows an implementation of a B3ZS decoder. The decoder is composed of two four-bit shift registers, one for the positive pulses and one for the negative pulses. The two four-input AND gates will decode a pattern of 0 (second case) in either the positive shift register or the negative shift register. In the event the sequence is found on the next clock pulse the pattern will be changed to This is done with the two AND gates in the shift register. The two six-input AND gates will detect the pattern 0 0 (first case) in either the positive shift register or the negative shift register. In the event the pattern is found on the next clock pulse the sequence will be changed to This is done with the two AND gates in the shift register. The last flip-flops of both shift registers are combined with the two-input OR gate. This will provide the NRZ output

3 RPOS RCLK RNEG 29 RESETN 24 BZ3S Encoder/Decoder Reference Design Positive Negative AND AND 3 28 NRZ FIGURE B3ZS ENCODER - 3 -

4 NRZ TCLK Reset S S2 S3 B BPVM2 JKFF 20 J Q K JKFF 9 J Q BPVPOL 7 POLP BPV AND AND3 4 AND3 3 9 Normal One injection TPOS TNEG BZ3S Encoder/Decoder Reference Design FIGURE 2 B3ZS Decoder - 4 -

5 BZ3S Encoder/Decoder Reference Design No responsibility is assumed by TDK SEMICONDUCTOR CORPORATION for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, visit our web site or contact your local TDK Semiconductor representative. TDK Semiconductor Corp., 242 Michelle Dr., Tustin, CA TEL (74) , FAX (74) , TDK Semiconductor Corporation 0/0/200 rev

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DS V T3 / E3 / STS-1 Line Interface www.dalsemi.com PRELIMINARY 3.3V T3 / E3 / STS-1 Line Interface FEATURES Integrated transmit and receive for T3, E3 and STS-1 line interfaces Performs clock/data recovery and wave shaping Requires no special