2 Sequential Circuits
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1 2 2.1 State Diagrams and General Form 0/0 1/0 Start State 0 /0 1/1 State 1 /1 0/1 State Diagram of a Change Detector ( Mealy-machine). The output Y assumes 1 whenever the input X has changed. Otherwise Y assumes 0. University College Cork Dept of Computer Science 1
2 General Form We assume the presence of a central clock. A general form is: t is the discrete time. x, y and z are numbers. z(t + 1) = f ( z(t), x(t) ) y(t) = g ( z(t), x(t) ) The state Z is encoded as a binary pattern. This leads to the description: Q(t + 1) = f ( Q(t), X(t) ) Y (t) = g ( Q(t), X(t) ) Q is the binary state Q 1, Q 2, Q 3,... X is the input vector X 1, X 2, X 3,... Y is the output vector Y 1, Y 2, Y 3,... University College Cork Dept of Computer Science 2
3 General Design Problem 1. Develop the State Diagram (Problem A). 2. Assign a bit patterns Q 1, Q 2, Q 3,... to each state (Problem B). 3. Minimize the switching functions f and g. Problem A The number of states can sometimes be reduced by elimination of equivalent states. Problem B Known as secondary state assignment. Becomes really relevant for 5 or more states. University College Cork Dept of Computer Science 3
4 2.2 Mealy and Moore Machine The general finite state machine (FSM) is called a Mealy-machine: z(t + 1) = f ( z(t), x(t) ) y(t) = g ( z(t), x(t) ) A special case is called Moore-machine: z(t + 1) = f ( z(t), x(t) ) y(t) = g ( z(t) ) The output y of a Moore-machine is only a function of the state. University College Cork Dept of Computer Science 4
5 Differences Between Mealy and Moore Machine Timing of output The output y of a Mealy-machine can change whenever the input x changes and whenver a clock step occurs. The output y of a Moore-machine can only change when a clock step occurs. It is synchronized with the time grid. State diagram In the state diagram of a Mealy-machine, the output values are associated with the transistion arcs. In the state diagram of a Moore-machine, the output values are associated with the state nodes. A Mealy-machine may perform the same task as a certain Moore-machine with more states. University College Cork Dept of Computer Science 5
6 Example: Traffic Lights Start green new Y=0 X=0 any green red again Y=0 X=0 X=1 again Y=1 any X=1 red new Y=1 State Diagram of a traffic light control cicuit ( Moore-machine). University College Cork Dept of Computer Science 6
7 Input States x=0 x=1 green new green again red new green again red new red new red new green new red again red again green new green new Transition table. x(t) z(t) Transition table with numbered states. University College Cork Dept of Computer Science 7
8 z Q 1 Q A secondary state assignment. The resulting set of equations: Q 1 = Q 1 Q 2 + Q 2 X Q 2 = Q 1 Q 2 X + Q 1 Q 2 X Y = Q 1 (11 literals) University College Cork Dept of Computer Science 8
9 z Q 1 Q A better secondary state assignment. The resulting set of equations: Q 1 = Q 1 Q 2 + Q 1 X + Q 2 X Q 2 = Q 1 Y = Q 1 (8 literals) University College Cork Dept of Computer Science 9
10 2.3 Latches and Flip-Flops The SR Latch - A Basic Building Block R Q S NOT(Q) An SR latch made of two NOR-gates. Mode S R Q Q hold hold reset set forbidden I/O behaviour of the SR latch. University College Cork Dept of Computer Science 10
11 Interpretation of the I/O Behaviour: In reset mode, the outputs are forced to QQ = 01. In set mode, the outputs are forced to QQ = 10. In hold mode, the latch remains in either of the two states above. The forbidden mode is to be avoided because the transisition from this mode to hold mode results in an unpredictable state. The SR latch is an asynchronous circuit. It has no input line for a central clock pulse. University College Cork Dept of Computer Science 11
12 The Clocked SR Flip-Flop Two modifications to the SR flip-flop: 1. Two AND gates and an input line for a central clock pulse CP are added. The hold mode can now be forced by CP = An inverter is added in order to avoid the forbidden mode. The circuit has now only one data input which is called Q. Q Q CP NOT(Q) Clocked SR flip-flop. long as CP = 1. The circuit is transparent as University College Cork Dept of Computer Science 12
13 Interpretation of the I/O Behaviour: When CP = 0, the circuit is always in hold mode. The input Q has no influence in this case. When CP = 1, the input Q directly influences the outputs: Q = Q and Q = Q. The circuit is transparent in this case. The clocked SR flip-flop is a synchronous circuit with a level-sensitive clock input. The mode of operation is similar to a weir or a lock (as in shipping) with only one gate. The closed gate corresponds to CP = 0 and the open gate corresponds to CP = 1. University College Cork Dept of Computer Science 13
14 The Master-Slave Flip-Flop The outputs of a (master) clocked SR flip-flop are concatenated with the inputs of a second (slave) SR flip-flop. The clock pulse of the slave is the inverse of the master clock pulse. Q Master Slave NOT(Q) CP Q Master-Slave flip-flop. The output Q is synchronized with the falling edge of the clock pulse CP. University College Cork Dept of Computer Science 14
15 Interpretation of the I/O Behaviour: At any time, only one of the two clocked SR latches is transparent while the other is not sensitive to input changes. Thus, the whole master-slave flip-flop is never transparent 1. The master-slave flip-flop is a synchronous circuit with an edge-sensitive clock input. The mode of operation is similar to a lock (as in shipping) with two gates. Both gates are never open at the same time so that the water levels are always kept separated. The master-slave flip-flop is a suitable buidling block for Moore- and Mealy-machines because the usage of edge-triggered flip-flops prevents the occurrence of undesired negative feedback loops. 1 The shown circuit is actually transparent during the short delay time of one inverter after the rising edge of the clock pulse. In real-world circuits this can be avoided by using gates with modified tresholds. University College Cork Dept of Computer Science 15
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