AIDA Update. presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh Liverpool STFC DL & RAL)
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1 AIDA Update presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh Liverpool STFC DL & RAL) Tom Davinson School of Physics & Astronomy The University of Edinburgh
2 AIDA: Introduction Advanced Implantation Detector Array (AIDA) UK collaboration: University of Edinburgh, University of Liverpool, STFC Daresbury Laboratory & STFC Rutherford Appleton Laboratory SuperFRS Exotic nuclei ~ MeV/u Implant decay correlations Multi-GeV implantation events Subsequent low-energy decays Tag events for gamma and neutron detector arrays Detector: multi-plane Si DSSD array wafer thickness 1mm 8cm x 8cm (128x128 strips) or 24cm x 8cm (384x128 strips) Instrumentation: ASIC low noise (<12keV FWHM), low threshold (0.25% FSR) 20GeV FSR plus ( 20MeV FSR or 1GeV FSR) fast overload recovery (~µs) spectroscopy performance time-stamping
3 AIDA Hardware Mezzanine: 4x 16 channel ASICs Cu cover EMI/RFI/light screen cooling FEE: 4x 16-bit ADC MUX readout (not visible) 8x octal 50MSPS 14-bit ADCs Xilinx Virtex 5 FPGA PowerPC 40x CPU core/linux OS DAQ FEE width: 8cm Prototype air cooling Production recirculating coolant Gbit ethernet, clock, JTAG ports Power
4 AIDA Mechanical Mechanical design for 8cm x 8cm and 24cm x 8cm DSSSDs is complete Evaluate performance of 8cm x 8cm design before proceeding to manufacture of 24cm x 8cm design Design compatible with BELEN, TAS, MONSTER, RISING, FATIMA etc. - Design drawings (PDF) available
5 AIDA: status DSSSD with sub-contractor (MSL) - 8cm x 8cm & 24 x 8cm mechanical samples - 4x 8cm x 8cm prototypes delivered - 10x 8cm x 8cm wafers + additional 0.5µm passivation production batch in progress QA, processing Production hardware (ASIC, FEE Mezzanine PCB, FEE PCB) delivered by sub-contractors FEE64 Mezzanine assembly - 78 completed and delivered FEE64 PCB - 50 OK - 19 (1 of 64) channels noisy, otherwise OK - 6 with faults requiring further tests FEE module assembly - 12 complete and tested OK - 20 queued
6 AIDA: status MACB timestamp distribution system for FEE modules - delivery complete Mechanical design and infrastructure (HV, PSUs, cooling etc.) - detector HV, FEE PSUs, cooling & FEE crates delivered - support assembly completed
7 AIDA: outlook AIDA production hardware was available for commissioning on schedule in 2011/Q3 Performance of 20GeV & 1GeV ranges meets specification - need to optimise DSSSD-FEE coupling for 20MeV range - progress very encouraging Basic data merge with MBS successfully demonstrated during AIDA+LYCCA test May further work required Continuing FEE firmware development work in progress - DSP (64 channel digital CFD being tested) DAQ software development work in progress - interface migrated from Tcl/Tk to XML/SOAP (web-based) - control and management of multiple FEE modules - timestamp-ordered data merge (GREAT format) Bottom line AIDA is ready and needs to be scheduled on FRS
8 AIDA: homepage
9 AIDA: DAQ main menu
10 AIDA: experiment control Note illustrates configuration controlling 8x FEE64 cards
11 AIDA: DAQ statistics
12 AIDA: preamplifier waveform capture
13 AIDA Plans
14 AIDA: Support Assembly All up tests in T4 laboratory STFC Daresbury Laboratory Note Julabo Recirculating Chiller to side of assembly
15 AIDA: MACB Timestamping hardware with HDMI cabling to AIDA FEE modules
16 AIDA: FEE Power Supply Power Supply Unit (bottom) controlled by Relay unit (top). Note Raspberry Pi on top of Relay Unit which provides remote control via web
17 AIDA: Relay Control
18 AIDA: MSL type BB Kapton cabling
19 AIDA: Adaptor PCB with Kapton Cabling
20 Acknowledgements My thanks to: STFC DL P. Coleman-Smith, M. Kogimtzis, I. Lazarus, S. Letts, P. Morrall, V. Pucknell, J. Simpson & J. Strachan STFC RAL D. Braga, M. Prydderch & S. Thomas University of Liverpool T. Grahn, P. Nolan, R. Page, S. Ritta-Antila & D. Seddon University of Edinburgh Z. Liu, G. Lotay & P. Woods University of Brighton O. Roberts GSI F. Amek, L. Cortes, J. Gerl, E. Merchan, S. Pietri et al.
21 AIDA: Project Partners The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson Further information: TDR - November 2008:
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