EB-GS2970. Evaluation Board User Guide. EB-GS2970 Evaluation Board User Guide May of 23

Transcription

1 May 0 of 3

2 Version ECR Date Changes and / or Modifications May 0 Changed A to A_ in Figure -: Power and AES Drivers Schematics February 009 Changes to Figure -: Top Level Schematic and Figure -: Equalizer and Cable Driver Schematics June 008 New document. Contents Overview Power (J)...5. Input (J) Switch Settings (SW)...6. Outputs Loop-Through (J5) Audio Output (J3 and Bs J9-J) Parallel Video Output (J6 and J7) JTAG/GSPI Header (JP) Lock and Data Error Status Modes of Operation...8. Schematics Top Level Schematic Equalizer and Cable Driver Schematics....3 GS970 Schematic.... Power and AES Drivers Board Layout.... Bill of Materials May 0 of 3

3 Overview Together with the Evaluation Board, this document serves as a guide for evaluating the GS970; a Gennum 3Gb/s, HD, SD Receiver. This document contains four main sections:... Evaluation Board Schematics. 3. Evaluation Board Layout.. Evaluation Board Bill of Materials The figure below shows a block diagram of the features and the functions of the. The board includes a power supply, a 3G- input, a 3G- loop-through output, a GS970 Receiver, a parallel video output connector, an audio output with four Bs for AES audio, a four-pin header for serial audio, a JTAG/GSPI header, a 7MHz crystal, a DIP switch and some status indication LEDs. The GS970 will automatically detect the input signal as SD-, HD- or 3G-. The input format may also be configured to DVB-ASI or Data-Through mode manually, through a DIP switch. The deserialized video is available on the parallel output connector (J6). The extracted audio is available as serial audio or AES on an audio header (J3), or as buffered AES only audio on the B connectors (J9-J). A serial digital loop-through output is also available. The also provides a JTAG interface and access to the GS970 s internal registers via GSPI. A GSPI dongle is included in the kit, to communicate with the GS970 through a USB connection.the GSPI dongle has the provision to control and monitor an additional EB97 board connected to the May 0 3 of 3

4 Power CD (GS978) 3G- Loop-Through Audio Header Audio O/P 3G- I/P EQ (GS97B) GS970 (Receiver) 8-ch Audio Audio Clocks PCLK 0-bit Video FVH AES Parallel Video O/P GSPI/5V DIP Switch GSPI/JTAG Header LEDs (Lock; Data Error) Block Diagram of the May 0 of 3

5 . Figure - shows the inputs, outputs and power connections for the. Power (J).8V/3.3V Jumper (JP7) Power Status LED (D) Lock Status Indicator (U) Data Error Status Indicator (U3) Input (J) Parallel Video Output (J6) CD O/P Jumper (JP) Loop-Through (J5) H, V & F Timing Signals (J7) DIP Switch (SW) JTAG/GSPI Header (JP) GSPI (J8) Serial Audio Output (J3) AES Audio Outputs (J9 - J ) Figure -: GS970 Evaluation Board (). Power (J) The requires a single +5V DC power supply. The board is powered through J. LED (D) indicates the power on/off state of the board. Through the use of jumper JP7, the GS970 I/O voltage can be selected as either.8v or 3.3V. If the and the EB-GS97 are connected together, one supply will power both boards. Therefore, the +5V DC power is only required on either the or the EB-GS May 0 5 of 3

6 . Input (J) The includes a single input. The applied stream will first pass through Gennum's GS97B Cable Equalizer before entering the input pins of the GS Switch Settings (SW) A DIP switch (SW) is populated on the, with each bit labelled on the silk-screen. This switch is used to set the operating modes of the GS970. The signal can be set HIGH by placing the switch to the One position (Closed). NOTE: Some signals are active LOW, so you will need to switch the bit OFF to activate the signal. Refer to Table - below for definitions of each bit. Table -: SW Settings Bit Name TIM86 SMPTE_BYPASSb DVB_ASI AUDIO_EN/DISb IOPROC_EN/DISb 0BIT/0BITb SDO_EN/DISb Description Connected to the GS970 TIM_86 pin. Used to select CEA-86 timing mode. When TIM_86 is HIGH, the device outputs CEA 86 timing signals (HSY/VSY/DE) instead of H:V:F digital timing signals. Connected to the GS970 SMPTE_BYPASS pin. Used to enable/disable all forms of encoding/decoding, descrambling, audio and A data detection and extraction and error detection and correction. When the AUTO/MAN bit in the Host Interface register is HIGH (Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW under all other conditions. When the AUTO/MAN bit in the Host Interface register is LOW, this pin is an INPUT. No SMPTE scrambling takes place, and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW. When SMPTE_BYPASS is set HIGH, the device carries out SMPTE descrambling and I/O processing. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. Connected to the GS970 DVB_ASI pin. Used to enable/disable DVB-ASI data decoding in manual mode. When the AUTO/MAN bit in the Host Interface is LOW, this pin is an input and when set HIGH the device will carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. When the AUTO/MAN bit in the Host Interface is HIGH (Default), DVB-ASI input is not supported. Connected to the GS970 AUDIO_EN/DIS pin. Enables or disables audio extraction. Connected to the GS970 IOPROC_EN/DIS pin. Used to enable or disable I/O processing features. When IOPROC_EN/DIS is HIGH, the I/O processing features of the device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing features of the device are disabled, and the latency of the device is LOW. Please refer to the Data Sheet for more information. Connected to the GS970 0bit/0bit pin. Used to select the output bus width. (HIGH = 0bit, LOW = 0bit) Connected to the GS970 SDO_EN/DIS pin. Used to enable/disable the serial digital output stage. When the SDO_EN/DIS is LOW, the serial digital output signals, SDO and SDO, remain static. When connected to logic HIGH, the serial digital output signals, SDO and SDO, are enabled. The SDO and SDO outputs will also be disabled when the RESET pin is LOW May 0 6 of 3

7 Table -: SW Settings Bit Name RC_BYPb FW_EN STANDBY Description Connected to the GS970 RC_BYP pin. When this pin is LOW, the serial digital output is the buffered version of the input serial data. When this pin is HIGH, the serial digital output is the reclocked version of the input serial data. Connected to the GS970 SW_EN pin. Used to enable switch-line locking. Please refer to the Data Sheet for more information. Connected to the GS970 STANDBY pin. When this pin is set HIGH, the device power is reduced, and placed into Standby mode.. Outputs.. Loop-Through (J5) A relocked or non-relocked buffered version of the input stream is available on the serial loop-through output (J5). It is designed to be SMPTE compliant for voltage level, rise/fall time and return loss at three rates (SD, HD and 3G) using the compensation network. The GS978 Cable Driver is necessary to guarantee return loss specification. The GS978 should be set to SD or HD mode; use jumper JP to select the mode. See Table - below. Table -: GS978 Cable Driver format JP Position Open Closed Status HD/3G SD If the loop-through is not required, disable the SDO through the SDO_EN/DIS DIP switch setting (SW). Doing this will also disable the GS978 Cable Driver... Audio Output (J3 and Bs J9-J) The extracted 8-channel audio, together with the Audio Master Clock generated by the GS970, is available on a 0-pin header (J3). For AES mode, AES-encoded CMOS-level signals are distributed through line drivers, and supplied to four B connectors (J9, J0, J and J). An audio output board can be connected to Serial Audio Output header (J3)...3 Parallel Video Output (J6 and J7) Parallel video data with the PCLK is available on a 8-pin connector (J6) and timing signals H, V and F are connected to a 0-pin connector (J7). This is a standard Gennum parallel interface, compatible with all Gennum evaluation boards May 0 7 of 3

8 .5 JTAG/GSPI Header (JP) The GS970 contains a set of internal status and configuration registers. These registers are available to the host via the GS970 s GSPI pins. Access to the applicable pins on the GS970 is provided using the JTAG/GSPI header. A GSPI dongle is provided for communication to the GSPI interface. If you have the and the EB-GS97 connected together, only one GSPI dongle is required, and can be connected to either of the boards..6 Lock and Data Error Status LED U indicates the lock status of the GS970, and LED U3 indicates data error. Both are bi-colour devices. See Table -3 below. Table -3: Lock and Data Error Status LED Green Red U (Lock Status) Locked Unlocked U3 (Data Error Status) No Error Detected Error Detected.7 Modes of Operation The GS970 supports four distinct modes of operation that can be set through the DIP switch or by programming internal registers through the GSPI. These modes are: SMPTE mode, Data-Through mode, DVB-ASI mode and Standby mode. The GS970 can automatically detect the format of the incoming signal when AUTO/MAN = HIGH. If the format of the incoming signal is not recognized, the GS970 defaults into SMPTE Bypass mode. Alternatively, the device may be forced into any of the four modes through the Host Interface (Address 0h). In SMPTE mode, the GS970 performs full SMPTE processing, and features a number of signal integrity checks and measurement capabilities. In DVB-ASI mode, 8b/0b decoding is applied to the received data stream. In SMPTE Bypass mode, all forms of SMPTE and DVB-ASI decoding are disabled, and the device can be used as a simple serial-to-parallel converter without incurring the latency penalties associated with SMPTE or DVB-ASI mode. The device can also operate in a lower power Standby mode. In this mode, no signal is generated at the output May 0 8 of 3

9 The DIP switch (SW) corresponds directly to pins on the GS970. Refer to the GS970 Data Sheet for a more detailed explanation of the modes of operation May 0 9 of 3

10 . Schematics. Top Level Schematic RESET RST S B3S-00P IOVDD_970 R8.5K C9 0.u TIM86 Pin _ctrl0 SMPTE_BYPASSb Pin _ctrl9 DVB_ASI Pin _ctrl8 AUDIO_EN/DISb Pin _ctrl7 IOPROC_EN/DISb Pin _ctrl6 0BIT/0BITb Pin _ctrl5 SDO_EN/DISb Pin _ctrl RC_BYb Pin _ctrl3 FW_EN Pin _ctrl STANDBY Pin _ctrl JTAG/HOSTb Pin _ctrl0 J UCBBJE0- INPUT EQ and CD Input GS970_ GS970_ RESET A_970 SDO_EN/DIS GS970_ACLK GS970_WCLK GS970_AOUT_ GS970_AOUT3_ SERIAL AUDIO J TSW L-D GS970_ACLK GS970_WCLK GS970_AOUT5_6 GS970_AOUT7_8 GS970_AMCLK GS970_AOUT5_6 GS970_AOUT7_8 SERIAL AUDIO OUT Figure -: Top Level Schematic May 0 J6 GS970_PCLK 6 35 VID_DAT_Out0 VID_DAT_Out VID_DAT_Out VID_DAT_Out3 VID_DAT_Out VID_DAT_Out5 VID_DAT_Out6 VID_DAT_Out7 VID_DAT_Out8 VID_DAT_Out9 VID_DAT_Out0 VID_DAT_Out VID_DAT_Out VID_DAT_Out3 VID_DAT_Out VID_DAT_Out5 VID_DAT_Out6 VID_DAT_Out7 VID_DAT_Out8 VID_DAT_Out IOVDD_ Lock TMMH--0-F-D-RA-ES MALE: TOP-SIDE J7 HVF0 HVF HVF HSMF-C65 SCLK N SDOUT CS0 GS970_H GS970_V GS970_F TMMH-05-0-F-D-RA MALE: TOP-SIDE J VCC_5V CS3 CS CS TMMH-05-0-F-D-RA 0 of 3 AES Ch _ BCJ-FPLV0 J 3 OUT J5 UCBBJE0- OUT GS978_ GS978_ 3 A_970 EQ and CD GS970_SD_EN/DIS AUDIO_Out[6:0] CS3 0K JTAG/HOSTb 0K CS 0K CS 0K R89 R90 R87 R88 AES Ch 3_ BCJ-FPLV0 J AES Ch 5_6 BCJ-FPLV0 J0 AES Ch 7_8 BCJ-FPLV0 J9 IOVDD_970 Power and AES driv ers AOUT_ AOUT3_ AOUT5_6 AOUT7_8 AES Ch _ AES Ch 3_ AES Ch 5_6 AES Ch 7_8 Power and AES driv ers GSPI JP TSW L-D VCCA VCCB 0 U K A red K 3 A green TR 6 TR0 OEb 7 A 3 A0 B0 B FXLTD5 Lock Data Error VID_DAT_Out[9:0] HVF[:0] IOVDD_970 GSPI[3:0] GSPI GSPI GSPI0 IOVDD_970 AUDIO_Out AUDIO_Out0 AUDIO_Out3 AUDIO_Out AUDIO_Out6 AUDIO_Out AUDIO_Out5 RESET RESET GS970_ GS970_ Lock Data Error GS970_PCLK VID_DAT_Out[9:0] HVF[:0] GSPI[3:0] GS970_SDO GS970_SDO AUDIO_Out [6:0] Pin _ctrl[0:0] GS970 T/Rb 5 VCCB 6 VCCA B0 B B B3 3 T/Rb 0 U6 T/Rb0 3 A0 5 A 6 A A3 7 T/Rb3 FXLTD5 GSPI3 OEb 9 8 CS0 IOVDD_970 TIM86 SMPTE_BYPASSb DVB_ASI AUDIO_EN/DISb IOPROC_EN/DISb 0BIT/0BITb SDO_EN/DISb RC_BYb FW_EN STANDBY SW SW DIP-0/SM Pin _ctrl[0:0] U RESET WDI R35 0K R36 0K GS970_AOUT_ RN3 7C6303 GS970_AOUT3_ MR Vcc 5 MAX683V R85 75R U Data Error HSMF-C65 K A red K 3 A green R86 75R U3

11 . Equalizer and Cable Driver Schematics EQ +3.3V EQ Power Decoupling & Filtering 6 3 C5 0n C6 0n +3.3V Input L3 R 6n 75R R5 75R C9 C5 u R6 37R u C5 70n C55 70n AGC AGC VCC VCC U6 GS97B VEE VEE VEE VEE TAB A_970 C8 u7 SDO C83 u7 SDO 0 8 MCLADJ MUTE 5 CD 7 BYPASS C56 0n C 0n R 0R C5 u R95 0R C6 C7 u 0n A_970 A_970 A_970 9 TAB A_970 CD +3.3V LOOP-THROUGH SD_EN/DIS SDO SDO +3.3V C7 0n A_970 SD_EN/DIS SDO SDO R8 9R9 R0 750R R9 9R VCC RSET DISABLE U7 GS978 TAB SD closed JP HD open R R9 75R 0 0K SD/HD SDO A_970 SDO 75-ohm traces C8 R3 0n 75R A_970 C50 u7 R L 5n6 R7 75R 75R A_970 C5 u7 OUT CD Power Decoupling & Filtering R9 0R C0 C C 0n u u R9 0R +3.3V C3 0n A_970 C57 0n A_970 A_970 Figure -: Equalizer and Cable Driver Schematics May 0 of 3

12 .3 GS970 Schematic Close to GS970 GS970 Power Decoupling & Filtering +.VA 3.3V R +3.3VA R7 05R +3.3VA 0R C8 C9 C0 0n u u R 0R +.V R0 0R C C5 C6 0n u u R9 0R 3.3V or.8v DNP R 0R C30 C3 C3 0n u 0n +.V C C5 C6 C7 0n 0n 0n 0n C 0n C7 0n C33 0n C C3 0n 0n A_970 +.VA C8 C9 0n 0n A_970 IO_VDD C3 C35 0n 0n Close to GS VA LB_CONT Settings: Floating or +3.3V or R9 DNP R DNP A3 C u A C 7n A TP7 R3 DNP B3 C3 6p TP8 H6 A_970 J6 C 6p K6 Y CS M Pin _ctrl0 TIM86 H5 Pin _ctrl[0:0] Pin _ctrl9 SMPTE_BYPASSb G7 Pin _ctrl8 DVB_ASI G8 Pin _ctrl7 AUDIO_EN/DISb H3 Pin _ctrl6 IOPROC_EN/DISbH8 Pin _ctrl5 0BIT/0BITb H7 Pin _ctrl SDO_EN/DISb J Pin _ctrl3 RC_BYb G3 Pin _ctrl FW_EN D7 Pin _ctrl STANDBY K Pin _ctrl0 JTAG/HOSTb D8 RESET C7 RESET GSPI3 SDOUT E7 GSPI N E8 GSPI SCLK F8 GSPI0 CS0 F7 GSPI[3:0] G F G R39 G DNP C8 33u A_970 LB_CONT VBG LF RSV XTAL_OUT XTAL XTAL TIM_86 SMPTE_BYPASS DVB_ASI AUDIO_EN/DIS IOPROC_EN/DIS 0BIT/0BIT SDO_EN/DIS RC_BYP FW_EN STANDBY JTAG/HOST RESET SDOUT_TDO N_TDI SCLK_TCK CS_TMS RSV RSV RSV RSV +.VA +.V IO_VDD A VCO_VDD B PLL_VDD C3 PLL_VDD C PLL_VDD A_VDD B H BUF_VDD E _VDD D6 CORE_VDD E6 CORE_VDD F6 CORE_VDD G6 CORE_VDD U5 GS970 A7 IO_VDD IO_VDD D0 IO_VDD G0 IO_VDD K7 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT DOUT3 DOUT DOUT DOUT0 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT DOUT3 DOUT DOUT DOUT0 PCLK STAT STAT STAT0 STAT3 STAT STAT5 AMCLK AOUT_/ AOUT_3/ AOUT_5/6 AOUT_7/8 ACLK WCLK B8 R6 R VID_DAT_Out9 A9 R7 R VID_DAT_Out8 A0 R8 R VID_DAT_Out7 B9 R9 R VID_DAT_Out6 B0 R30 R VID_DAT_Out5 C9 R3 R VID_DAT_Out C0 R3 R VID_DAT_Out3 C8 R33 R VID_DAT_Out E0 R0 R VID_DAT_Out E9 R R VID_DAT_Out0 F0 R3 R VID_DAT_Out9 F9 R R VID_DAT_Out8 H0R R VID_DAT_Out7 H9 R0 R VID_DAT_Out6 J0 R36 R VID_DAT_Out5 J9 R35 R VID_DAT_Out K0 R3 R VID_DAT_Out3 K9 R R VID_DAT_Out J8 R R VID_DAT_Out K8 R5 R VID_DAT_Out0 A8 R8 R PCLK B5 R R F HVF A6 R6 R V HVF A5 R7 R H HVF0 B6 Lock TP9 C5 TP8 Lock C6 Data Error TP0 Data Error K AMCLK AUDIO_Out 6 J3 AOUT_/ AUDIO_Out 5 K3 AOUT_3/ AUDIO_Out J5 AOUT_5/6 AUDIO_Out 3 K5 AOUT_7/8 AUDIO_Out J R37 R ACLK AUDIO_Out H R38 R WCLK AUDIO_Out 0 VID_DAT_Out[9:0] PCLK HVF[:0] Lock Data Error AUDIO_Out [6:0] C SDO K SDO SDO Close to pin C & D of GS970 C53 0n D F TERM VCO_ PLL_ PLL_ PLL_ B D E F C A_ D A_ D3 A_ E3 A_ F3 A_ H BUF_ E _ D5 CORE_ E5 CORE_ F5 CORE_ G5 CORE_ B7 IO_ D9 IO_ G9 IO_ J7 IO_ SDO J SDO SDO A_970 Figure -3: GS970 Schematic May 0 of 3

13 3. Power and AES Drivers POWER SUPPLIES AES AUDIO OUT C70 5V J 5V Input VCC_5V C36 EEV-FKCXP GS970_AOUT_ GS970_AOUT_ C9 0.u U7 3 A B 0R SN65LVDT 0.u Vcc 5 R AES Ch _ C58 0.u VCC_5V C87 u PWRGD_3V3 C86 u TPS70_RGW IN IN IN IN BIAS EN PG U OUT OUT OUT OUT FB SS Pad C85 0n R3 3.57K R6.5K C3 u VCC_5V R96 9.9K PWRGD_3V3 3 U5 6 VCCA VCCB 5 VCC_5V DIR R57 A B 0R SN7LVCT5DBVR D LNJ3G8PRA PWR GS970_AOUT3_ GS970_AOUT5_6 C93 GS970_AOUT3_ 3 0.u U8 A B U9 C9 GS970_AOUT5_6 3 A 0.u B 0R SN65LVDT 0R Vcc 5 R C63 0.u Vcc 5 R AES Ch 3_ AES Ch 5_6 SN65LVDT C0 u U LT30ES8-. IN SHDN P A_ OUT SENSE Heat sink on copper +.V 3 7 TP C39 33u +.V 500mA C90 C8 u 0.u U LT30ES8-.8 IN SHDN P A_ OUT SENSE Heat sink on copper mA VCC_.8V C88 33u GS970_AOUT7_8 U0 C95 GS970_AOUT7_8 3 A 0.u B 0R SN65LVDT C65 0.u Vcc 5 R AES Ch 7_8 Figure -: Power and AES Drivers Schematics May 0 3 of 3

14 3. Board Layout Figure 3-: Layer (Top Layer) May 0 of 3

15 Figure 3-: Layer (Ground) May 0 5 of 3

16 Figure 3-3: Layer 3 (Power) May 0 6 of 3

17 Figure 3-: Layer (Signal ) May 0 7 of 3

18 Figure 3-5: Layer 5 (Signal ) May 0 8 of 3

19 Figure 3-6: Layer 6 (Bottom Layer) May 0 9 of 3

20 . Bill of Materials Table -: Bill of Materials Quantity Reference Part 3 C3, C0, C86 μf Capacitor (805) 7 C, C7, C8, C0, C3, C, C30 0nF Capacitor (0603) C5, C6, C9, C0, C, C, C5, C6, C3, C87, C90 C, C, C3, C, C5, C6, C7, C7, C8, C9, C3, C33, C3, C35, C5, C6, C7, C8, C53, C56, C57, C85 μf Capacitor (0603) 0nF Capacitor (00) 3 C8, C39, C88 33μF Capacitor (0) C36 EEV-FKCXP (CT-CAP/PANA_FK_D8) C 7nF-70nF Capacitor (00) 3 C, C9, C5 μf Capacitor (00) C3, C 6pF Capacitor (0603) C50, C5, C8, C83.7μF Capacitor (0603) C5, C55 70nF Capacitor (00) 0 C58, C63, C65, C70, C8, C9, C9, C93, C9, C95 0.μF Capacitor (00) D ESD_6V (SOD53) D LNJ3G8PRA (06_LED) JP TSW L-D (BLKCON.00/VH/TMOE/W.00/0) JP JUMPER (HEADER_.00_X) JP7 BLKCON.00/VH/TMSQ/W.00/3 J, J5 UCBBJE0- (B_EDGEMNT _GHZ-POUR-LYR-ER3.8) J6 TMMH--0-F-D-RA-ES (HEADERMM_8_X) J7, J8 TMMH-05-0-F-D-RA (HEADERMM_0_X5) J9, J0, J, J BCJ-FPLV0 (B _EDGEMNT_RIGHT_ANGLE) J3 TSW L-D (HEADERMM_0_X5) May 0 0 of 3

21 Table -: Bill of Materials Quantity Reference Part J 5V Input (CON_WEID5MM PWR) L3 6.nH Inductor (00) L 5.6nH Inductor (00) RN, RN 7C630 (CT-7_6) RN3 7C6303 (CT-7_6) 9 R, R, R9, R0, R, R, R9, R9, R95 0Ω Resistor (0603) R3 3.57kΩ Resistor (0603) R6, R8.5kΩ Resistor (0603) R7 05Ω Resistor (0603) 0 R, R6, R7, R8, R0, R, R, R5, R37, R38 Ω Resistor (00) 6 R35, R36, R87, R88, R89, R90 0kΩ Resistor (00) R0 750Ω Resistor (00) 8 R, R, R3, R, R5, R7, R85, R86 75Ω Resistor (00) R6 37.Ω Resistor (00) R8, R9 9.9Ω Resistor (00) R57 0Ω Resistor (0603) R9 0kΩ Resistor (0603) R96 9.9kΩ Resistor (0603) SW SW DIP-0/SM (Through Hole) S B3S-00P 6 TP, TP7, TP8, TP8, TP9, TP0 Via (CT-TP) U MAX683V (SOT3-5) U LT30ES8-. (CT-SOIC_8) U5 GS970 Receiver (CT-BGA_00_X_.00) U6 GS97B Equalizer (CT-QFN_MM_6/WSHLD) U7 GS978 Cable Driver (CT-QFN_MM_6/WSHLD) U, U3 HSMF-C65 U TPS70_RGW (0-QFN) U5 SN7LVCT5DBVR (SOT3-6) U6 FXLTD5 (DQFN-MLP06E) May 0 of 3

22 Table -: Bill of Materials Quantity Reference Part U7, U8, U9, U0 SN65LVDT (SOT3-5) U LT30ES8-.8 (CT-SOIC_8) U FXLTD5 (MAC00A) Y CS M (SM/XTAL_6.0X3.5/) May 0 of 3

23 DOCUMENT IDENTIFICATION USER GUIDE Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Gennum assumes no liability for any errors in this document, or for the application or design described herein. Gennum reserves the right to make changes to the product or this document at any time without notice. GENNUM CORPORATE HEADQUARTERS 8 Harvester Road, Burlington, Ontario L7L 5M Canada CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION Phone: + (905) Fax: + (905) corporate@gennum.com OTTAWA 3 Herzberg Road, Suite 0 Kanata, Ontario KK A Canada Phone: + (63) Fax: + (63) CALGARY st St. N.W., Suite 0 Calgary, Alberta TL K7 Canada Phone: + (03) 8-67 UNITED KINGDOM North Building, Walden Court Parsonage Lane, Bishop s Stortford Hertfordshire, CM3 5DB United Kingdom Phone: Fax: INDIA #08(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar India Phone: +9 (67) Fax: +9 (67) SNOWBUSH IP - A DIVISION OF GENNUM 39 University Ave. Suite 700 Toronto, Ontario M5G Y8 Canada Phone: + (6) Fax: + (6) sales@snowbush.com Web Site: MEXICO 88-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 0900 Phone: + (6) JAPAN KK Shinjuku Green Tower Building 7F 6--, Nishi Shinjuku Shinjuku-ku, Tokyo, Japan Phone: +8 (03) Fax: +8 (03) gennum-japan@gennum.com Web Site: TAIWAN 6F-, No.5, Sec., Keelung Rd. Sinyi District, Taipei City 50 Taiwan R.O.C. Phone: (886) Fax: (886) gennum-taiwan@gennum.com GERMANY Hainbuchenstraße Muenchen (Munich), Germany Phone: Fax: gennum-germany@gennum.com NORTH AMERICA WESTERN REGION Bayshore Plaza 07 N st Street, Suite #300 San Jose, CA 953 United States Phone: + (08) Fax: + (08) naw_sales@gennum.com NORTH AMERICA EASTERN REGION 8 Harvester Road Burlington, Ontario L7L 5M Canada Phone: + (905) Fax: + (905) nae_sales@gennum.com KOREA 8F Jinnex Lakeview Bldg. 65-, Bangidong, Songpagu Seoul, Korea Phone: Fax: gennum-korea@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. Copyright 008 Gennum Corporation. All rights reserved May of 3