Low-Power Delay Buffer Design Using Asymmetric C-Element Gated Clock Strategy

Transcription

1 Low-Power Delay Buffer Design Using Asymmetric C-Element Gated Clock Strategy C.Aarthi Assistant Professor/ECE Sengunthar Engineering College Tiruchengode,Tamilnadu,India Dr. R. K.Gnanamurthy Professor & Principal S.K.P.Engineering College Tiruvannamalai,Tamilnadu,India Abstract--Implementation of Low power delay buffer uses several novel techniques to reduce power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the Asymmetric C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both Simulation results and experimental results show great improvement in power consumption. Index Terms Asymmetric C -Element, Gated driver tree, Ring Counter, Delay Buffer,DET Flip-Flops. 1. INTRODUCTION In the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power consideration was mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed considerations. Several factors have contributed to this trend. Perhaps the primary driving factor has been the remarkable success and growth of the class of personal computing devices (portable desktops, audio- and video-based multimedia products) and wireless communications systems (personal digital assistants and personal communicators) which demand high-speed computation and complex functionality with low power consumption. In many such products, delay buffers (line buffers, delay lines) make up a significant portion of their circuits. Such serial access memory is needed in temporary storage of signals that are being processed, e.g., delay of one line of video signals, delay of signals within a fast Fourier transform (FFT) architectures, and delay of signals in a delay correlator. Currently, most circuits adopt static random access memory (SRAM) plus some control/addressing logic to implement delay buffers. For smaller-length delay buffers, shift register can be used instead the former approach is convenient since SRAM compilers are readily available and they are optimized to generate memory modules with low power consumption and high operation speed with a compact cell size. Previously, a simplified and thus lower-power sequential addressing scheme for SRAM application in delay buffers is proposed. A ring counter is used to point to the target words to be writtenin and read-out. Since the ring counter is made up of an array of D-type flip-flops (DFFs) triggered by a global clock signal and all except one DFFs have a value of 0, it is possible to disable the clock signal to most DFFs. Such a gated-clock ring counter is implemented to compose a lowpower first-in first-out (FIFO) memory. In this delay buffer architecture, the double-edgetriggered (DET) flip-flops used instead of traditional DFFs in the ring counter to halve the operating clock frequency. A novel approach using the Asymmetric C-elements instead of the R S flip-flops in the control logic for generating the clockgating signals is adopted to avoid increasing the loading of the global clock signal. In addition to gating the clock signal going to the DET flip-flops in the ring counter, gated tree technique is used. The technique will greatly decrease the loading on distribution network of the clock signal for the ring counter and thus the overall power consumption. II. DELAY BUFFERS A. Delay Buffers Implemented by Shift Registers The simplest way to implement a delay buffer is to use shift registers which was used already. If the buffer length is N and the word-length is b, then a total of DFFs are required, and it can be quite large if a standard cell for DFF is used. In addition, this approach can consume huge amount of power since on the average Nb /2 binary signals make transitions in every clock cycle. As a result, this implementation is usually used in short delay buffers, where area and power are of less concern. Fig.1.Delay buffer implemented by shift registers B. Pointer based delay buffers For long delay buffers SRAM-based delay buffers used because of the compact SRAM cell size and small total area. Also, the power consumption is much less than shift registers because only two words are accessed in each clock cycle: one for write-in and the other for read-out. A binary counter can be used for address generation since the memory words are accessed sequentially. Though the SRAM-based delay buffers do away with many data transitions, there still can be considerable power consumption in the SRAM address decoder and the read/write circuits.

2 Fig.2.Pointer based delay buffer Fig.5.Timing Diagram of Ring counter with clock Gated by R-S Flip-Flop On the other hand, the successful propagation of 1 to the first DFF in the next block can henceforth shut down the unnecessary clock signal in the current block. Fig.3.Memory cell of Pointer based delay buffer In fact, since the memory words are accessed sequentially, we can use a ring counter with only one rotating active cell to point to the words for write-in and read-out. This method, known as the pointer-based scheme [5], is illustrated in Fid.2. The bottom roe of D-type Flip-flops is initialized with only one1 and all other DFFs are kept at 0.When the Clock edge triggers edge triggers the DFFs, this 1 signal is propagated forward. Consequently, the traditional binary address decoder can be replaced by this unary-coded ring counter. Compared to the shift register delay buffers, this approach propagates only one 1 in the ring counter instead of propagating -bit words. Obviously, with much less data transitions, the pointer-based delay buffers can save a lot of power. C.Gated-Clock Ring Counter using R-S Flip-Flop By observing the fact that only one of the DFFs in the ring counter is activated, the gated-clock technique has then been proposed to be applied to the DFFs in [6]. In their approach every eight DFFs in the ring counter are grouped into one block then, a gate signal is computed for each block to gate the frequently toggled clock signal when the block can be inactive so that unnecessary power wasted in clock signal transitions is saved. III.SYSTEM OVERVIEW In the proposed delay buffer, several power reduction techniques are adopted. Mainly, these circuit techniques are designed with a view to decreasing the loading on high fan-out nets, e.g., clock and read/write ports. Fig.6. proposed Low power delay buffer architecture A. Gated-Clock Ring Counter A ring counter is a type of counter composed of a circular Shift register. The output of the last shift register is fed to the input of the first register. The memory block utilizes ring-counter addressing scheme. In the ring counter, doubleedge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the Asymmetric C-element gated-clock strategy is proposed. The Asymmetric C-element, or Asymmetric C-gate, is a commonly used asynchronous logic component originally designed by David E.Muller. It applies logical Operations on the inputs and has hysteresis. Fig.4.Ring counter with clock gated by R-S Flip-Flop As shown in Fig. 4, when the input of the first DFF in when the input of the first DFF in a block is asserted, it sets the output of the R S flip- flop to 1 at the next clock edge. Thus, the incoming 1 can be trapped at the next clock edge. Here the Asymmetric C-Element shown in Fig.8.is utilized in the proposed work instead of Muller C-Element. The Muller C-element reflects the inputs when the states of all inputs match. The output then remains in this state until the inputs all transition to the other state. The Asymmetric C- elements are extended C-Elements which allow inputs which only effect the operation of the element when transitioning in one of the directions. Asymmetric inputs are attached to either the minus (-) or plus (+) strips of the symbol. The common inputs which effect both the transitions are connected to the centre of the symbol. When transitioning from zero to one the C-element will take into account the common and the asymmetric plus inputs.

3 All these inputs must be high for the up transition to take place. Similarly when transitioning from one to zero the C-element will take into account the common and the asymmetric minus inputs. All these inputs must be low for the down transition to happen. All gating signals are easily generated by a C-element taking inputs from some DET flip-flop outputs of the ring counter. In order to reduce more power, we replace DFFs by double-edgetriggered flip-flops and operate the ring counter at half speed. Fig.9. Circuit diagram of Double Edge triggered Flip-Flop The proposed ring counter with hierarchical clock gating and the control logic is shown in the above Fig.7. Each block contains one C-element to control the delivery of the local clock signal CLK to the DET flip-flops, and only the CKE signals along the path passing the global clock source to the local clock signal are active. The gate signal (CKE) can also be derived from the output of the DET flip-flops in the ring counter. In order to reduce more power, we replace DFFs by double-edge-triggered flip-flops and operate the ring counter at half speed. In order to further diminish the loading on the global clock signal ( CLK), we propose to use a driver tree distribution network for the global clock and activate only those drivers along the path from the clock source to the blocks that need to be driven by the clock. The gate signal for those drivers can be derived from the same clock gating signals of the blocks that they drive. In quad-tree driver architecture with four times more drivers in each level, all drivers need be activated if no gating is applied and the number of active driver is given by Fig.7. (a) Ring counter with clock gated by C-elements, (b) tree-structured clock drivers with gating, and (c) control logic for clock enable signals On the other hand, only 2log4M drivers are activated in the worst case for the proposed gated-clock tree when two drivers are activated in each of the log4m level. On the average, there are no more than (1+ (2/D)) log4m drivers that are turned on, D=N/M where is the number of DET flip-flops in one block. A quad tree is used for clock drivers, then for a length- N ring counter constituted by a total of N flip-flops partitioned in M blocks. Loading of a traditional ring counter N X LFF Loading of the proposed ring counter Fig.8. Circuit diagrams of Asymmetric C-element

4 Where LFF,LAND and LRS denote the loading of a D-type flipflop clock input, an AND gate input and an R S flip-flop clock input, respectively. B.Gated-Driver Tree The gated-driver tree technique used for the clock distribution networks can eliminate the power wasted on drivers. The tree-structured hierarchy of tri-state inverters used for delivering the input word to the addressed memory word. The gated-demultiplexer tree and a gated-multiplexer tree are used for the input and output driving circuitry to decrease the loading of the input and output data bus. To save area, the memory module of a delay buffer is often in the form of an SRAM array with input/output data bus as Special read/write circuitry, such as a sense amplifier, is needed for fast and low-power operations. However, of all the memory cells, only two words will be activated: one is written by the input data and the other is read to the output. Driving the input signal all the way to all memory cells seems to be a waste of Power. The same can be said for the read circuitry of the output port. In light of the previous gated-clock tree technique, we shall apply the same idea to the input driving/output sensing circuitry in the memory module of the delay buffer. The memory words are also grouped into blocks. Each memory block associates with one DET flip-flop block in the proposed ring counter and one DET flip-flop output addresses a corresponding memory word for read-out and at the same time addresses the word that was read one-clock earlier for write-in. With gated driver tree, it is Where LLatch and L Tri are the loading of one latch and one tri-state buffer, respectively. Fig.10. depicts the tree-structured hierarchy of tri-state inverters used for delivering the input word to the addressed memory word. A b -bit delay buffer needs b sets of the circuitry in the figure. The enable signal of the the jth tristate inverter at the ith level (E ij ) should be asserted when the 1 is within one of the blocks from index 1+(j-1)M/4 i to jm/4 i in the ring counter, where M is the number of blocks and a quad tree is assumed. These signals are generated by a C-element. Fig.11. Circuit diagram of Clock enable gated driver tree C.Memory Block The Memory block retrieves and stores the data according to the read/write circuit address. The standard 6-T SRAM cell is used in the delay buffer which is shown in Fig.12.The addressing data s coming from the Ring counter. For the write circuitry, in each level of the driver tree, only one driver along the path leading to the addressed memory word is activated. Similarly a tree of multiplexers and gated drivers comprise the read circuitry for the proposed delay buffer. Fig.10. Circuit diagram of Double Edge triggered Flip-Flop The loading of the input write circuitry Without gating strategy, it is Fig T SRAM Cell

5 IV.SIMULATIONS FOR SCALABILITY A delay buffer based on the proposed techniques is designed and implemented in µm CMOS technology. The standard 6-T SRAM cell is used in the delay buffer. Eight DET flipflops, eight memory words, and associated control logic are designed in a full-custom fashion and grouped as one block. We have simulated the proposed delay buffer with various lengths in 0.18µ m CMOS technology. The word-length is set to 8 bits. The area and power consumption are estimated from post layout simulation. Fig.15 Simulated results of (a) power and (b) area of various delay buffers versus different lengths Fig.13.Simulation of Proposed delay buffers. Fig.16.Comparison of Area, Power, delay of the Existing and proposed delay buffers. Fig.14.Simulation Power Report of Proposed delay buffers. Table-I (Power Consumption of the delay buffer with and without Asymmetric Clock gating Strategy) Existing Delay Proposed Delay Buffer Buffer Power(mw) Delay(ns) 10 6 In addition, the results are compared with the values provided by a commercial SRAM compiler in the same technology. Since in each clock cycle, one read and one write operations are necessary for the delay buffer of length N, either one twoport SRAM with N words or two one-port SRAMs each with N/2 words is required. For longer -length delay buffers and for more advanced technology, other leakage reduction Techniques such as the sleep transistors in SRAM (Latch) cells can help to reduce leakage power. V.CONCLUSION The low-power delay buffer architecture which was developed here adopts several novel techniques to reduce power consumption. The ring counter with clock gated by the Asymmetric C-elements can effectively eliminate the excessive data transition without increasing loading on the global clock signal. The gated-driver tree technique used for the clock distribution networks can eliminate the power wasted on drivers that need not be activated. Another gated-demultiplexer tree and a gated-multiplexer tree are used for the input and output driving circuitry to decrease the loading of the input and output data bus. All gating signals are easily generated by a

6 Asymmetric C-element taking inputs from some DET flip-flop outputs of the ring counter. Measurement results indicate that the proposed architecture consumes only about 13% to 17% of the conventional SRAM-based delay buffers in µm CMOS technology. Further simulations can also be done in nanometer CMOS technology. And cell size of the proposed delay buffer can be further reduced, making it very useful in all kinds of multimedia/communication signal processing applications. REFERENCES [1] W. Eberle et al., 80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band, IEEE J. Solid-State Circuits, vol. 36, no. 11, pp , Nov [2] M. L. Liou, P. H. Lin, C. J. Jan, S. C. Lin, and T. D. Chiueh, Design of an OFDM baseband receiver with space diversity, IEE Proc. Commun., vol. 153, no. 6, pp , Dec [3] G. Pastuszak, A high-performance architecture for embedded block coding in JPEG 2000, IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 9, pp , Sep [4] W. Li and L.Wanhammar, A pipeline FFT processor, in Proc. Workshop Signal Process. Syst. Design Implement., 1999, pp [5] E. K. Tsern and T. H. Meng, A low-power video-rate pyramid VQ decoder, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp , Nov [6] N. Shibata, M.Watanabe, and Y. Tanabe, A currentsensed high-speed and low-power first-in-first-out memory using a wordline/bitline- swapped dual-port SRAM cell, IEEE J. Solid-State circuits, vol. 37, no. 6, pp , Jun [7] E. Sutherland, Micropipelines, Commun. ACM, vol. 32, no. 6, pp , Jun [8] R. Hosain, L. D. Wronshi, and A. albicki, Low power design using double edge triggered flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI ) Syst., vol. 2, no. 2, pp , Jun [9] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y.Wang, B. Zheng, and M. Bohr, SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp , Apr [10]Buffer Insertion for Noise and Delay Optimization Charles J. Alpert, Member, IEEE, Anirudh Devgan, Member, IEEE, and Stephen T. Quay.IEEE transactions on computeraided design of integrated circuits and systems, vol. 18, no. 11, november 1999 [11]Variable Input Delay CMOS Logic for Low Power DesignTezaswi Raja, Member, IEEE, Vishwani D. Agrawal, Fellow, IEEE, and Michael L. Bushnell, Fellow, IEEE, IEEE transactions on very large scale integration (vlsi) systems, vol. 17, no. 10, october 2009 C.Aarthi has completed Bachelor of Engineering in the field of Electronics and Communication Engineering from Sri Ramakrishna Engineering College under Bharathiyar University. Master of Engineering in the field of VLSI Design under Anna University of Technology, Coimbatore. Pursuing Ph.D in the field Electronics and Communication Engineering under Anna University, Chennai. She is having more than 7 years of Experience in the field of Teaching. Currently she is working as a Assistant Professor in the Department of Electronics and Communication Engineering, Tiruchengode, Tamil nadu, India. Dr. R. K. Gnanamurthy has completed Bachelor of Engineering in the field of Electronics and Communication Engineering Under Bharathiar University, Coimbatore. Master of Engineering in the field of Microwave and Optical Engineering Under Madurai Kamaraj University, Madurai. Ph. D in the field of Information and Communication Engineering under Anna University Chennai. He is having more than 25 years of experience in the field of Teaching;He worked several institutions in the various designations Like Senior Lecturer, Assistant Professor, Professor and Head of the Department and Principal. Now He is working as a Principal, SKP Engineering College, Tiruvannamalai, Tamil nadu, India. He is the Life member of Indian Society for Technical Education and Computer Society of India Member of IIIE, India. And he also the Students Member of Institute of Electrical and Electronics (IEEE) (USA). He is the Chairman and Member of Board of studies in various universities. His Area of specialization is Wireless Sensor Networks and Mobile Computing. He guided 27 PG students and under his guide ship more than 13 students are doing their research.