P.Akila 1. P a g e 60

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1 Designing Clock System Using Power Optimization Techniques in Flipflop P.Akila 1 Assistant Professor-I 2 Department of Electronics and Communication Engineering PSR Rengasamy college of engineering for women Seval patti India. Abstract--- In many digital Very Large Scale Integration design, clock system is one of the most power consumption component. It consumes 30% to 60% of the total system power. As we are in need to reduce the power consumption on portable digital circuit because power budget is severely limited on portable digital circuit. To achieve this requirement, a clock system employing two techniques such as Dual Edge Triggered Sense Amplifier Flip Flop (DETSAFF) and Clock Gated Sense Amplifier Flip Flop (CGSAFF) is proposed. Dual Edge Triggering Sense Amplifier Flip flop will reduce the power consumption up to 30%. Clocked Gated Sense Amplifier Flip Flop (CG SAFF) is engaged when switching activity is less than 0.5. During zero input switching activity, CGSAFF offers up to 86% power saving. We can further reduce the power consumption of the clock system by using low swing differential conditional capturing flip-flop. Index Terms: Low power, High performance, Sense amplifier flip flop, clock gating. I. INTRODUTION Moore s law drives the VLSI technology to continuously increase the transistor densities, there are hundreds millions of transistors or even billions of transistors on a chip today, which results in increased power consumption of VLSI chip. Although the capacitances and the power supply scale down, the power consumption of the VLSI chip is still increasing continuously. Flip-Flops are extremely important circuit elements in all VLSI circuits. They are not only responsible for the correct timing, functionality and performance of the chip, but also they and other clock distribution networks consume a significant portion of the total power of the circuit. It is estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20% 45% of the total system power. Comparing to different elements in the VLSI circuits, flip-flops are the primary source of the power consumption in synchronous system. Moreover, flip-flops have a large impact on circuit speed. The performance of the Flip-Flop is an important element to determine the performance of the whole circuit. II. PROBLEM STATEMENT Power consumption and timing delays are the two important design parameters in high speed VLSI systems. In many digital very large scale integration (VLSI) designs, the clock system that includes clock distribution network and flip-flops, is one of the most power consumption components. It accounts for 30% to 60% of the total system power, where 90% of which is consumed by the flip-flops and the last branches of the clock distribution network that is driving the flip-flop, as clock frequency increases, the latency of the flip-flop or latch will play an even greater role in the overall cycle time. A Flip-Flop that synchronizes the state changes during a clock pulse transition is the edgetriggered flip-flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. As the clock frequency increase, pulse-triggered flip-flop tends to be popular as compared to conventional master-slave flip-flops. Because they employ time borrowing across cycle boundaries which results in zero or negative setup time. Moreover, the number of transistors we used in the pulse-triggered flip-flop is less than the number we used in the conventional master-slave flip-flops, so the simple structure of the pulse-triggered flip-flop leads to abetter power efficiency. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Because the clock frequency is determined by system specifications, the clock signal is constantly active, it makes timing components (latches and flip-flops) the most power consuming components in the VLSI system. Like the single-edge triggered flip-flop, the output of the flip-flop will follow the input D at the edge of the clock, the difference is that the dual-edge triggered flip-flop will cause a transition on both the positive edge of the clock pulse and the negative edge of the clock pulse. On the rising edge of the clock and the falling edge of the clock, the output is given the value of the D input at that moment. The output can only change at the clock edge, and if the input changes at other times, the output will be unaffected. The used of dual edge-triggered flip-flops can help to reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput. In other words, the dual-edge triggered flip-flop requires a lower clock frequency than the single-edge triggered flip-flop to achieve comparable performance. Therefore, the dual edge triggered flip flop offers the same data throughput of single edgetrigger flip-flops at half of the clock frequency, this thereafter translates to better performance in terms of both power dissipation and speed. P a g e 60

2 III. DETSAFF DESIGN A. Design of Pulse Generator When we plan to design a dual-edge triggered pulse generator, the most commonly used method is to use the inverter to generate the clock delay and use this little difference of the clock to generate the pulse. This pulse generator has improved two disadvantages of the pulse generator. The first improvement is that this pulse generator can produce two narrower pulses at both the rising edge and falling edge of the clock, this can help the flip-flop reduce the setup time and hold time effectively. The second improvement is that this pulse generator can produce a pulse which can get to the V dd, however, the pulse that produced in cannot get to the V dd, because of the delay which is generated by two inverters, the voltage of CLK2 is still low and CLK3 is still high, at this time, transistor N1 is on and P1 is off because of the high voltage of the CLK, transistor P2 is on because of the low voltage of CLK2, transistor N2 is on because of the high voltage of the CLK3, so the transistors N1, N2, P1 will transfer the high voltage to the point pulse, and pulse will rise at this time. After a very short time, the voltage of CLK2 will change to be high and the voltage of CLK3 will change to be low, transistor P1 is still off and transistor N1 is still on, but transistor P2 will turn off and transistor N2 will turn off because of the low voltage of CLK3, so the pulse will fall down at this time. In this very short period of time, this pulse generator generates a pulse at the rising edge of the clock. When CLK is from high to low(falling edge of the clock), because of the delay which is generated by the two inverters, the voltage of CLK2 is still high, at this time, transistor P1 is on and transistor N1 is off because of the low voltage of the CLK, transistor P2 is off because of the high voltage of CLK2, transistor N2 is off because of the low voltage of CLK3, so the transistor P1 will transfer the voltage of CLK2 to the point pulse, and pulse will rise to the V dd. After a very short time, the voltage of CLK2 will change to be low, and the voltage of CLK3 will change to be high, at this time, transistor P1 is still on and transistor N1 is still off, however, transistor P2 will turn on and transistor N2 will turn on, so transistors P1, P2, N2 will transfer the voltage of CLK to the point pulse, although the transistors P1 and P2 are not good candidates for transferring the low voltage, they can help the pulse to fall down quickly, and transistor N2 can help the pulse go the voltage of zero volt. In this very short period of time, this pulse generator generates a pulse at the falling edge of the clock. B. Design of Sensing Stage For a sense amplifier based flip-flop, in the evaluation phase, as soon as D is low, SB will be set to high, and if D is high, RB will be set to high. Therefore, the conditional precharging technique is applied in the sensing stage of DET-SAFF, to avoid redundant transitions at major internal nodes. Fig.1.DETSAFF (a) Pulse Generator (b) Sensing Stage (c) Latching Stage Two input controlled PMOS transistors, SP1 and SP2, are embedded in the precharge paths of nodes SB and RB, respectively. In this case, if D remains high for n cycles, SB may only be discharged in the first cycle. For the following (n-1) cycles, SB will be floating when PULS is low or fed to the low state DB when PULS is high. As for RB, it only needs to be precharged in the first cycle and remains at its high state for the remaining cycles. Since the precharging activity is conditionally controlled, the critical pull down path of SB and RB is simplified, consisting of only one signal transistor. This helps to reduce the discharging time significantly. As such, the resulting sensing stage possesses low-power and high-speed features. C. Design of latching stage To further improve the speed of the flip-flop, a fast symmetric latch is developed. The schematic of the latching stage of the flip-flop One big difference of this latching stage with other latch is that the input D and D can help charge or discharge Q and Q directly, in this way, the Clock-to-Q delay will reduce effectively. When the voltage of the pulse is high, if the voltage of the D is high and the voltage of D is low, transistor P1 is off and transistor P2, P3 and P4 are on, so transistor P3 and P4 will transfer the voltage V dd to the point Q, and the output of the flip-flop Q will follow the input D to change to be high. Moreover, transistor N1 and N2 will turn on at this time, so transistor N1 can transfer the low voltage to the point Q and transistor N2 will transfer the high voltage to the point Q, although transistor N2 is not a P a g e 61

3 good candidate for transferring the high voltage, it can help the point Q accelerate to go from low voltage to high voltage. In the whole process of the low-to-high transition of output Q, because of the voltage of the pulse is high, transistors P5 and P7 turn off, so the two inverters which are composed by transistor P6 and N3, transistor P8 and N4 stop working, in this way, we can save more power when the output is following the input D. When the voltage of the pulse is high, if the voltage of the D is low and the voltage of D is high, transistor P3 is off and transistor P1, P2 and P4 are on, so transistor P1 and P2 will transfer the voltage V dd to the point Q, at this time, transistor N1 and N2 are turning on and they will transfer the voltage of D and D to the point Q and Q respectively.. In the whole process of the high-to-low transition of the output Q, because of the voltage of the pulse is high, transistors P5 and P7 turn off, so the two inverters which are composed by transistor P6 and N3, transistor P8 and N4 stop working, in this way, we can save more power when the output is following the input D. When the voltage of the pulse is low, transistors P2, P4, N1 and N2 turn off, whatever the voltage of the output is high or low, V dd cannot be transferred to the point Q, and transistor N1 and N2 will not transfer the voltage of D and D to the point Q and QB either. When the voltage of the pulse change to high, then the two inverters will stop working and the output Q will follow the input data again. IV. DESIGN OF CGSAFF In order to eliminate the redundant transitions in the pulse generator, the CG-SAFF is constructed. It utilizes the DETSAFF design as a baseline and incorporates the clock gating technique. In CG-SAFF, the clock gating technique is implemented by embedding a control circuit in the explicit pulse generator so that the PULS signal generation is disabled in a redundant event. In order to compare the previous and current input values, two comparators are applied to produce signals X and Y, by using the differential inputs, D and DB, and the buffered outputs, Q1 and QB1, as control signals. If D is different from the output Q1 (Q), X will be pulled up to high and Y to low. Transistor CN3 is turned on to allow the clock signal to pass through as CL. CL is known as the gated clock. At the same time, CP1 is on and drive the CLK1 signal to high before the rising edge of the clock. At the rising edge of the clock, CL is high and its delayed signal CLK3 remains low. Therefore, transistor CN5 and the transmission gate are turned on, driving the PULS signal to high. After a short period, the transparent window is closed as CLK1 goes low and CLK3 is pulled up. Thus, a short transparent period is created at the rising edge of the clock. Note that signal CLK1 is used for pulse generation rather than CLK2. Such design aims to ensure that the flip-flop only captures the data at the triggering edge of the clock, thereby preventing race problems. Fig.2. Design of CGSAFF-Pulse Generator At the falling edge of the clock, CL is low and CLK3 is high. Transistor CP5 is selected and generates a high PULS signal. The sampling window is shut down once CLK3 is low. When the input D remains the same in consecutive clock cycles, X is low and Y is high. CL is pulled down by CN4 so that the corresponding CLK3 will be low regardless of the CLK signal. CLK1 may only be discharged at the first clock cycle and maintains its low state in the remaining clock cycles. As a result, the flip-flop will remain opaque and thus, the power can be saved. The sensing stage is the same as DET-SAFF. Since the generated PULS signal is more heavily loaded than that of DET-SAFF, a modified Nikolic s latch is used. The inner holding topology is modified to obtain buffered differential outputs, Q1 and QB1, with reduced load capacitances. In the clocking stage, Q1 and QB1 are used to generate X and Y instead of using Q and QB. This helps to improve the performance of CG-SAFF significantly. Fig.3. Design of Latching Stage IV. DESIGN OF LS-DCCFF Conditional capturing is used to minimize flip-flop power at low data switching activities by eliminating redundant internal transitions. In reduced swing inverters similar to the one presented in are used at the node fed by the low-swing sinusoidal clock signal. This is done to reduce short circuit power by minimizing the interval at which both the PMOS and NMOS of the inverter turn on simultaneously. The load PMOS transistor in the reduced swing inverters is always in saturation since. It lowers the P a g e 62

4 voltage at the source of the second PMOS in each inverter to approximately thus turning it off when the low-swing sinusoidal clock signal reaches its peak voltage. activity. It is very clearly predicted from the results that at higher switching activity DETSAFF provide better power reduction than at lower switching activity. Fig.6.Schematic Design of DETSAFF Fig.5.Design of Low Swing Differential Conditional Capturing Flipflop The peak voltage for the low-swing clock was chosen to be equal to 0.65 since the threshold voltage of the PMOS transistor is approximately V. From here on and for simplicity the term LS, FS refers to low-swing and fullswing, respectively. V. SIMULATION RESULTS Schematic design and simulation results of Dual Edge Triggered Sense Amplifier Flip Flop and clock gated sense amplifier are shown below. All the flip-flops were designed using Tanner 13.0v s, 0.25µm CMOS process technology, at an operating temperature of 27ºC and a supply voltage of 3.0 V. The power consumption of the flip flop is calculated as in terms of current and voltage across the padded output. Calculation for time delay and aperture time and power consumption for the DETSAFF is given below. And the results were analysed for higher and lower switching Fig.6. Simulation output d,clk,q and qb in DETSAFF Design T D-Q =T clock-q + T setup = 99ns T aperture =T hold + T setup = 26.4ns P a g e 63

5 T total = T D-Q + T aperture = 125.4ns suffered from greater power consumption at lower switching activity because pulse generator will generate For α= 0.75 P = 0.717µW (for T total = 125.4ns) pulse when the latching stage will not in a need of the pulse signal as redundant signal occur. So we are moving to For α=0.85 P = 0.8µW (for T total = 115ns) CGSAFF which efficient at lower switching activity But here the penalty of area is too high. By considering the fact For α=0.3 P = mw (for T total = 156ns) of larger silicon area, design low swing differential conditional capturing flipflop which provide better power reduction in clock system. REFERENCES Fig.5.Schematic Design of CGSAFF Fig.6 Simulation output at d,clk,q and QB of CGSAFF VI. CONCLUSION Clock system which plays an important role in portal digital designs. By using the design of ep dual-edge triggered sense amplifier flip-flop,clock gated sense amplifier flip flop and low swing differential conditional capturing flipflop we can reduce the power consumption of clock system at higher switching activity, lower switching activity and low swing inputs respectively. The explicit pulsed dual edge triggered sense amplifier flip flop is [1] Myint Wai Phyu, et al., Power efficient explicit pulsed Dual Edge Triggered Sense Amplifier Flip Flop, IEEE Transactions on VLSI System, vol.19, no.1,jan [2] P. Zhao, et al., Low Power Clock Branch Sharing Double Edge Triggered Flip Flop IEEE Transactions on VLSI System, vol. 15, no.7, pp ,Mar [3] C.K.The, et al., Conditional data mapping flipflops for Low power and High performance systems IEEE Transactions on VLSI System, vol. 14, no.12, pp , Dec [4] M. W. Phyu, W. L. Goh and K. S. Yeo, A Low-Power Static Dual Edge-Triggered Flip-Flop using an Output- Controlled Discharge Configuration, IEEE [5] A.G.M.Strollo, et al., A Novel High Speed Sense Amplifier Based Flip Flop IEEE Transactions on VLSI Systems, vol. 13 no.11, pp , Nov [6] P.Zhao, T.K.Darwish and M.A. Bayoumi, High Performance and Low Power Conditional Discharge Flip Flop, IEEE Transactions on VLSI Systems, vol.12, no.5, May [7] B.Schauwecker, et al., Dual Edge triggered NAND Keeper Flip Flop for High Performance VLSI, a new type of high bandwidth rf mems switch-toggle switch, June [8] B.S.Kong, et al., Conditional Capture flip flop for statical power reduction IEEE Journal on Solid state circuits., vol 36,no.8, pp , Aug [9] Nikola Nedovic, Marko Aleksic and Vojin G.Oklobdzija, Timing Characterization of Dual Edge Triggered Flip Flops, International Conference on Computer Design, ICCD 2001, Austin, Texas, September 23-26, [10] Borivoje Nikolic, et al., Improved Sense-Amplifier- Based Flip-Flop: Design and Measurements, IEEE journal of solid-state circuits, vol. 35, no. 6, June [11] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuit. New York: Wiley, [12] Vladimir Stojamovic and et al., Comparative Analysis of Master Slave Latches and Flip Flops for High Performance and Low power system, IEEE Journal on Solid State Circuits, vol.34, no.4, April [13] H.Kawaguchi and T.Sakurai, A Reduced Clock Swing Flipflop for 63% Power reduction, IEEE Journal on solid State Circuits, vol.33, no.v5, pp May P a g e 64