Design on AM-OLED display control ASIC with high gray scale levels

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1 J Shanghai Univ (Engl Ed), 2011, 15(4): Digital Object Identifier(DOI): /s Design on AM-OLED display control ASIC with high gray scale levels JI Yuan ( ) 1, RAN Feng (º ô) 1,2, XU Hong-guang (Å ½) 3, SHEN Wei-xing ( å ) 1, JI Wei-gui ( á ) 1, XU Mei-hua (ÅßÙ) 1 1. School of Mechatronics Engineering and Automation, Shanghai University, Shanghai , P. R. China 2. Micro-electronics Research and Development Center, Shanghai University, Shanghai , P. R. China 3. SVA ELECTRON Co., Ltd., Shanghai , P. R. China Shanghai University and Springer-Verlag Berlin Heidelberg 2011 Abstract The paper puts forward a method on controlling the AM-OLED panel to display image with high gray scale levels. It also gives an ASIC design sample to implement this method. A twenty sub-fields scan scheme has been taken into use in the chip to display 256 gray scale levels on a QVGA resolution AM-OLED display screen. The functions of image scaling and rotating have also been implemented for multiply application. The simulation and chip test result show that the chip design has met the design requirements. Keywords active matrix organic light emitting display (AM-OLED), ASIC design, gray scale level, sub-field, image scaling, image rotation Introduction There is great interest in organic light emitting display (OLED) technology in recent years. Characterized with its attribution on ultra high-lighting, wide view angle, thin body structure, fast reaction, low power and wide temperature adaptability, OLED is regarded as the next generation display in ubiquitous applications such as TV screen, desktop PC, lap-top monitor, PDA, video player, cell-phone, navigator, camera, and other industrial or medical application, and so on [1]. Distinguished with the drive strategy, OLED can be divided into passive matrix drive technology that is called PM-OLED and active matrix drive technology that is called AM- OLED. Due to the limitation on the panel structures and circuit functions of PM-OLED, it can be only used in small display size and low display resolution, such as simple digital and character display, while AM-OLED may provide high quality display content on image and video with high display resolution and high gray scale level. In order to make full use of the high performance of AM-OLED, it is critical to develop corresponding drive circuit [2]. There are already many researches focusing on the OLED drive circuit performance with different materials of driving cell [3 6]. Another main research aspect is the pixel drive circuit [7 10]. This article concentrates on the system control of a specified OLED panel, and put forward a design scheme on the control ASIC of the specified OLED panel by using a twenty sub-field scan scheme to generate 256 gray scale. The built-in rotating module and image size scaling module make it more convenient on practical display application. 1 Display gray scale technology One of the important criterions on display quality is the display gray scale level. High gray scale can generate abundant luminance and chrominance for the display image that is captured by human eyes. In a short period of time, the eyes feeling on brightness depends not only on the intensity of light, but also on the duration time of emitting light. Within a certain time, the longer the light is given, the stronger the sense of light intensity can be felt by eyes. Therefore, the display gray scale can be controlled by adjusting the light duration time if the light intensity keeps a certain value. Thus a gray scale level control strategy can be concluded from this. The total display time of a certain image frame can be divided into several different time pieces which are called sub-fields (SFs). The time duration of sub-fields can be dedicatedly designed so that they can be combined to form different expected display time that is corresponding to the level of display gray scale of any accuracy Received Mar.10, 2011; Revised June 5, 2011 Project supported by the Science and Technology Commission of Shanghai Municipality (Grant No ), and the Shanghai AM Foundation (Grant No ) Corresponding author RAN Feng, Ph D, Prof, ranfeng@shu.edu.cn

2 J Shanghai Univ (Engl Ed), 2011, 15(4): within device capacity. This strategy is called SF scan scheme on display gray scale. Since it only requires two states of OLED pixel, light or dark, the scheme can be implemented by digital logic circuit. It is useful for AM- OLED display system when combined with some image signal processing functions, such as image rotating or image size scaling. The traditional formulation of SF is described following. First, the active lighting time of an image frame is divided into several same time units which can be combined to form different lighting time pieces. The proportion of these time pieces is called time weight. Generally, time weight can be measured by data bit. The lighting time piece that corresponds to the time weight is called the SF. For example, in 256 gray scale level scan, each image frame is divided into 256 time units and can be optimized to 8 SFs, corresponding to 8-bit data. SF8:SF7:SF6:SF5:SF4:SF3:SF2: SF1 = 128:64:32:16:8:4:2:1. The actual display time of each different sub-field (t SF ) is calculated in (1) and (2): t SF = p2q 1 T S 1, (1) T = 1, f frame (2) where T represents the total display time of one frame, S the gray scale unit, p the bit value of the corresponding sub-field. The valid value of p is 0 or 1, representing the state of the SF, dark or light respectively. q is the time weight of the corresponding bit. In (2), f frame is the frame rate of display panel, usually Hz. However, if t SF is calculated with (1) directly, it may obtain an extremely small value at the lowest time weight. For example, when f frame = 100 Hz and S = 256, it can be inferred that t SF is only 39 µs at the lowest time weight (q = 1). The data transfer clock f data can be calculated by (3). H n and H blank are the horizontal pixel number and horizontal blanking time, V n and V blank the vertical pixel number and vertical blanking time, and B the transfer data bus width. In a QVGA ( ) resolution system with 8-bit data bus, f data is faster than 245 MHz. f data = (H n + H blank )(V n + V blank ). (3) t SF B The traditional scan scheme for 256 gray scale levels is shown in Fig.1. Generally, the pixel gray scale level of each chrominance is indicated by an 8-bit binary data (Bit 7 Bit 0). The pixel gray scale is generated by the combination of scan time T1 T8. T1 T8 is usually proportional to each other. Obviously, the actual data transfer time for lower bit such as T1 and T2 is limited. Fig.1 Traditional scan scheme for 256 gray scale level Another useful scan scheme is discussed in [11]. The scan efficiency is greatly improved, though the clock frequency is still fast in high resolution application. It is high cost to implement high clock frequency in general digital circuit. The clock frequency becomes ultra high when the image resolution is very large. In order to solve this problem, a 20-sub-field scan scheme is described here. It is shown in Fig.2 for 256 gray scale level. There are 19 T-frames for scan time period and one B-frame for frame blanking time period. The scan time for different gray scale level is weighted by the same scan time unit T. The scan time for the gray scale corresponding to the highest bit (Bit7) is split into 8 sub-fields (T71 T78) and Bit6 is split into 4 sub-fields (T61 T64), and so on. For T3 T0, only 1 2, 1 4, 1 8 and 1 16 of time unit T is valid respectively, with additional blanking time B3 to B0 in time unit T. The sequential can be adjusted for blink elimination. The B-frame is optional and used for frame blanking. As a result, the gray scale unit S is reduced from 256 to 20, but still keeps the proportion of all scan time. Bit7: Bit6:Bit5:Bit4:Bit3:Bit2:Bit1:Bit0=128:64:32:16:8:4:2:1. The minimum t SF is only 500 µs time and f data is only 19.2 MHz with QVGA@100 Hz frame rate and 8-bit data bus, H blank and V blank assuming 0, calculated by (1) to (2). Fig.2 20-sub-field scan scheme There are some other sub-field schemes similar to 20- sub-field scheme. For example, the time of T0 T7 can be split into more time pieces, leading to less blanking time (B0 B4) but larger gray scale unit S which increases clock frequency. Also, the time of T0 T7 can be split into less time pieces to decrease gray scale unit S, however this will increase blanking time and reduce luminance. 20-sub-field is a tradeoff scheme between the luminance and circuit clock frequency.

3 312 J Shanghai Univ (Engl Ed), 2011, 15(4): Function design for chip 2.1 Chip block diagram The chip is designed to generate the scan control signals and pixel data to drive the AM-OLED panel with QVGA resolution. The top block diagram of the chip is shown in Fig.3, including five modules: synchronization (SYN) module, image pre-processing (IPP) module, frame buffer (FB) module, timing generating and data output (TGDO) module and IIC interface module. Image data is transferred through SYN module. IPP module performs image re-sizing, rotating and data restructuring. Then the processed image data is stored to the FB in FB module. At last, the scan timing is generated by TGDO module and image data is read out repeatedly from FB. IIC module is used to accept configure information though IIC bus, thus design options and chip parameters may be written into the chip. 2.3 IPP module The IPP module is designed to process image data before storing to the FB. There are two main blocks in the module, the image size scaler block and image data restructuring block. The image size scaler is used to resize input image (see Fig.5). The 24-bit pixel data with red, green and blue, 8-bit respectively are input to horizontal scaler and the pixel data are interpolated in horizontal orientation. Either bi-linear or bi-cubic interpolation algorithm can be adopted depending on the balance between image quality and circuit cost [12 14]. Then the horizontally scaled data is stored to the row buffer. The number of row, one or two, depends on the interpolation algorithm. Finally the image data is vertically interpolated by the vertical scaler. Fig.5 Block diagram of image size scaler Fig.3 Top block diagram of control chip 2.2 SYN module The SYN module is designed to synchronize the chip external signal to the internal global clock domain. The external signal is input to the FIFO of SYN module and then read through the global clock gclk. All level sense signals will be transformed to edge sense signal. Figure 4 shows the signal waveform before and after synchronization. Next to the image size scaler block is the image data restructuring block. The image data is restructured for scan sequence. Inputing data is transferred by pixel sequence, while the output is by gray scale sequence. The data of the same gray scale weight will be transferred to OLED panel in one scan frame. The image data restructuring block is used to accomplish such transfer. Figure 6 shows the algorithm of this progress. Fig.6 Data transfer sequence for input and output Fig.4 Signal waveform before and after synchronization However, three scenarios are encountered in this block, normal, rotating clockwise and rotating anticlockwise (see Fig.7). The current data address is required to map to new address in accordance with the new location when image rotation function is set by ROTATE OPT shown in Fig.3. Rotation buffer is needed to realize this function. It consists of two separate single-port RAM or one dual-port RAM.

4 J Shanghai Univ (Engl Ed), 2011, 15(4): Fig.8 Block diagram of the FB module Fig.7 Data transfer sequence for input and output may read data within one panel (i.e, within one SRAM bank) during scanning one certain gray scale, without jumping to other panel. Since the AM-OLED screen requires parallel pixel data, the TGDO module read 8-bit data per clock in one panel. 2.4 FB module FB module contains the frame data storage buffer. Either SRAM or DRAM can be used here. SRAM can be easily integrated in this chip but costs a lot. DRAM costs a little in area but usually takes much effort to design. Generally DRAM cannot be integrated to this chip. A specified DRAM chip is needed and a dedicated DRAM controller is required integrated in the design. SRAM is preferred when image resolution is under QVGA. This chip selects SRAM as FB, which consists of eight single-port SRAMs with each data depth and bit width bit. These SRAMs are created by memory compiler of IBM 0.13 µm tech. The block diagram of the FB module is shown in Fig.8. Since the SRAM is single-port, the working time is divided into write window and read window, which is used by IPP module and TGDO module respectively. When signal writewindow is valid, the pixel data from IPP module (fbwrdata) is written to FB with the write address (fbwraddr). When the signal readwindow is valid, the data stored in FB is read to the data line TGDO (fbdataout) with the read address (scanaddr). The input pixel data transfers by pixel sequence. After converted in IPP module, the data is stored in FB by gray scale sequence. For 256 gray scale levels, there are 8 gray weight values making up 8 data panels called Bit 0-8 Panel, illustrated in Fig.9. Each panel contains the data with the same gray scale weight. Thus, the TGDO module is easy to calculate the read address and Fig.9 Data structure stored in frame buffer 2.5 TGDO module The TGDO module is used to generate the control signals required by OLED screen as well as transform the image pixel data with the final output SF timing. The block diagram is shown in Fig.10. The column counter, row counter and frame counter are used to

314 J Shanghai Univ (Engl Ed), 2011, 15(4): 310 315 Fig.10 Block diagram of TGDO module generate the scan control signal (scanctrl[7:0]) of the AM-OLED panel under the control of the output FSM.

5 314 J Shanghai Univ (Engl Ed), 2011, 15(4): Fig.10 Block diagram of TGDO module generate the scan control signal (scanctrl[7:0]) of the AM-OLED panel under the control of the output FSM. 3 Simulation, synthesis, place and route This design is simulated by Synopsys simulation tool VCS under Linux. The simulation results are shown in Figs.11 and 12. In Fig.11, signal SSP becomes high at the rising edge of GCK, indicating row scan start. Data (MB[7:0], MG[7:0] and MR[7:0]) transfer at every rising edge of SCK and falling edge of SCKB. In Fig.12, G1SP and G2SP indicate a vertical scan start and end. The frequency of pixel clock SCK in this design is only 22.1 MHz, with the values of H blank 20 and V blank 20 respectively. The design is designed by Synopsys tool DC and P&R tool Astro. Target library is IBM 0.13 µm techlib. The DC area is µm 2, while 85.6% used for internal SRAM. The post PR area is µm µm with total PAD. The max frequency of global clock is constrained by 80 MHz, and the setup slack is ns and hold slack is ns in typical environment after PR. 4 Conclusions As is shown in Fig.13, the chip (a) with the driving system board (b) may drive an AM-OLED panel with resolution QVGA, manufactured by Samsung (c) and SVA (d). With the 20-sub-field scan scheme, 256 levels of gray scale are displayed on the screen as expected. The functions of image scaling and rotating are also successfully implemented. This article brings up a 20-sub-field scan scheme to display 256 gray scale levels on AM-OLED screen, which is difficult to implement by traditional gray scale scan scheme, and gives a sample design for such scheme. The AM-OLED display with larger resolution may be driven by the same SF scheme but new challenges such as the size of the FB and the chip clock frequency should be taken into more consideration. Fig.11 Horizontal signal waveform (.fsdb file) Fig.12 Vertical signal waveform (.fsdb file)

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Overview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED)

Chapter 2 Overview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED) ---------------------------------------------------------------------------------------------------------------